no-OS
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ad796x_fmcz
src
platform
xilinx
parameters.h
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/***************************************************************************/
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#ifndef __PARAMETERS_H__
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#define __PARAMETERS_H__
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/******************************************************************************/
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/***************************** Include Files **********************************/
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/******************************************************************************/
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#include <xparameters.h>
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#include <xil_cache.h>
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#include <
xilinx_uart.h
>
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#include "
xilinx_gpio.h
"
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/******************************************************************************/
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/********************** Macros and Constants Definitions **********************/
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/******************************************************************************/
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#ifdef _XPARAMETERS_PS_H_
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#define UART_DEVICE_ID XPAR_XUARTPS_0_DEVICE_ID
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#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
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#ifdef XPS_BOARD_ZCU102
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#define UART_IRQ_ID XPAR_XUARTPS_0_INTR
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#else
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#define UART_IRQ_ID XPAR_XUARTPS_1_INTR
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#endif
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#else // _XPARAMETERS_PS_H_
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#define UART_DEVICE_ID XPAR_AXI_UART_DEVICE_ID
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#define INTC_DEVICE_ID XPAR_INTC_SINGLE_DEVICE_ID
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#define UART_IRQ_ID XPAR_AXI_INTC_AXI_UART_INTERRUPT_INTR
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#endif // _XPARAMETERS_PS_H_
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#define UART_EXTRA &iio_uart_extra_ip
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#define UART_OPS &xil_uart_ops
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extern
struct
xil_uart_init_param
iio_uart_extra_ip
;
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#define RX_CORE_BASEADDR XPAR_AXI_PULSAR_LVDS_BASEADDR
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#define RX_DMA_BASEADDR XPAR_AXI_PULSAR_LVDS_DMA_BASEADDR
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#define RX_CLKGEN_BASEADDR XPAR_REFERENCE_CLKGEN_BASEADDR
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#define AXI_PWMGEN_BASEADDR XPAR_AXI_PWM_GEN_BASEADDR
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#define ADC_DDR_BASEADDR XPAR_DDR_MEM_BASEADDR + 0x800000
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#define GPIO_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
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#define GPIO_OFFSET 32 + 54
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#define GPIO_EN0_FMC GPIO_OFFSET
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#define GPIO_EN1_FMC GPIO_OFFSET+1
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#define GPIO_EN2_FMC GPIO_OFFSET+2
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#define GPIO_EN3_FMC GPIO_OFFSET+3
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/* This value can be modified based on the number
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of samples needed to be stored in the device buffer
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and based on the available RAM memory of the platform */
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#define SAMPLES_PER_CHANNEL_PLATFORM 20000
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#define MAX_SIZE_BASE_ADDR (SAMPLES_PER_CHANNEL_PLATFORM * 4)
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#define UART_BAUDRATE 115200
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extern
struct
axi_pwm_init_param
axi_pwm_0_extra
;
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#define PWM_0_PERIOD_NS 200
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#define PWM_0_DUTY_NS 16
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#define PWM_0_PHASE 0
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#define PWM_1_PERIOD_NS 200
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#define PWM_1_DUTY_NS 144
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#define PWM_1_PHASE 0
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#define GPIO_OPS &xil_gpio_ops
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#define GPIO_EXTRA &xil_gpio_init
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#define DCACHE_INVALIDATE Xil_DCacheInvalidateRange
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#endif
/* __PARAMETERS_H__ */
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xilinx_uart.h
iio_uart_extra_ip
struct xil_uart_init_param iio_uart_extra_ip
Definition:
parameters.c:39
axi_pwm_0_extra
struct axi_pwm_init_param axi_pwm_0_extra
Definition:
common_data.c:81
xilinx_gpio.h
xil_uart_init_param
Structure holding the initialization parameters for Xilinx platform specific UART parameters.
Definition:
xilinx_uart.h:67
axi_pwm_init_param
Structure holding the initialization parameters for axi PWM.
Definition:
axi_pwm_extra.h:50
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