34#ifndef __PARAMETERS_H__
35#define __PARAMETERS_H__
37#include <xparameters.h>
41#ifdef _XPARAMETERS_PS_H_
42#define UART_DEVICE_ID XPAR_XUARTPS_0_DEVICE_ID
44#ifdef XPS_BOARD_ZCU102
45#define UART_IRQ_ID XPAR_XUARTPS_0_INTR
47#define UART_IRQ_ID XPAR_XUARTPS_1_INTR
51#define UART_DEVICE_ID XPAR_AXI_UART_DEVICE_ID
52#define UART_IRQ_ID XPAR_AXI_INTC_AXI_UART_INTERRUPT_INTR
55#define UART_EXTRA &iio_uart_extra_ip
56#define UART_OPS &xil_uart_ops
60#define RX_CORE_BASEADDR XPAR_AXI_PULSAR_LVDS_BASEADDR
61#define RX_DMA_BASEADDR XPAR_AXI_PULSAR_LVDS_DMA_BASEADDR
62#define RX_CLKGEN_BASEADDR XPAR_REFERENCE_CLKGEN_BASEADDR
63#define AXI_PWMGEN_BASEADDR XPAR_AXI_PWM_GEN_BASEADDR
64#define ADC_DDR_BASEADDR XPAR_DDR_MEM_BASEADDR + 0x800000
66#define GPIO_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
67#define GPIO_OFFSET 32 + 54
69#define GPIO_EN0_FMC GPIO_OFFSET
70#define GPIO_EN1_FMC GPIO_OFFSET+1
71#define GPIO_EN2_FMC GPIO_OFFSET+2
72#define GPIO_EN3_FMC GPIO_OFFSET+3
77#define SAMPLES_PER_CHANNEL_PLATFORM 20000
78#define MAX_SIZE_BASE_ADDR (SAMPLES_PER_CHANNEL_PLATFORM * 4)
80#define UART_BAUDRATE 115200
83#define PWM_0_PERIOD_NS 200
84#define PWM_0_DUTY_NS 16
87#define PWM_1_PERIOD_NS 200
88#define PWM_1_DUTY_NS 144
91#define GPIO_OPS &xil_gpio_ops
92#define GPIO_EXTRA &xil_gpio_init
94#define DCACHE_INVALIDATE Xil_DCacheInvalidateRange
struct axi_pwm_init_param axi_pwm_0_extra
Definition common_data.c:75
Structure holding the initialization parameters for axi PWM.
Definition axi_pwm_extra.h:44
Structure holding the initialization parameters for Xilinx platform specific UART parameters.
Definition xilinx_uart.h:56