no-OS
projects
ad796x_fmcz
src
platform
xilinx
parameters.h
Go to the documentation of this file.
1
/***************************************************************************/
40
#ifndef __PARAMETERS_H__
41
#define __PARAMETERS_H__
42
43
/******************************************************************************/
44
/***************************** Include Files **********************************/
45
/******************************************************************************/
46
#include <xparameters.h>
47
#include <xil_cache.h>
48
#include <
xilinx_uart.h
>
49
#include "
xilinx_gpio.h
"
50
/******************************************************************************/
51
/********************** Macros and Constants Definitions **********************/
52
/******************************************************************************/
53
#ifdef _XPARAMETERS_PS_H_
54
#define UART_DEVICE_ID XPAR_XUARTPS_0_DEVICE_ID
55
#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
56
57
#ifdef XPS_BOARD_ZCU102
58
#define UART_IRQ_ID XPAR_XUARTPS_0_INTR
59
#else
60
#define UART_IRQ_ID XPAR_XUARTPS_1_INTR
61
#endif
62
63
#else // _XPARAMETERS_PS_H_
64
#define UART_DEVICE_ID XPAR_AXI_UART_DEVICE_ID
65
#define INTC_DEVICE_ID XPAR_INTC_SINGLE_DEVICE_ID
66
#define UART_IRQ_ID XPAR_AXI_INTC_AXI_UART_INTERRUPT_INTR
67
#endif // _XPARAMETERS_PS_H_
68
69
#define UART_EXTRA &iio_uart_extra_ip
70
#define UART_OPS &xil_uart_ops
71
72
extern
struct
xil_uart_init_param
iio_uart_extra_ip
;
73
74
#define RX_CORE_BASEADDR XPAR_AXI_PULSAR_LVDS_BASEADDR
75
#define RX_DMA_BASEADDR XPAR_AXI_PULSAR_LVDS_DMA_BASEADDR
76
#define RX_CLKGEN_BASEADDR XPAR_REFERENCE_CLKGEN_BASEADDR
77
#define AXI_PWMGEN_BASEADDR XPAR_AXI_PWM_GEN_BASEADDR
78
#define ADC_DDR_BASEADDR XPAR_DDR_MEM_BASEADDR + 0x800000
79
80
#define GPIO_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
81
#define GPIO_OFFSET 32 + 54
82
83
#define GPIO_EN0_FMC GPIO_OFFSET
84
#define GPIO_EN1_FMC GPIO_OFFSET+1
85
#define GPIO_EN2_FMC GPIO_OFFSET+2
86
#define GPIO_EN3_FMC GPIO_OFFSET+3
87
88
/* This value can be modified based on the number
89
of samples needed to be stored in the device buffer
90
and based on the available RAM memory of the platform */
91
#define SAMPLES_PER_CHANNEL_PLATFORM 20000
92
#define MAX_SIZE_BASE_ADDR (SAMPLES_PER_CHANNEL_PLATFORM * 4)
93
94
#define UART_BAUDRATE 115200
95
96
extern
struct
axi_pwm_init_param
axi_pwm_0_extra
;
97
#define PWM_0_PERIOD_NS 200
98
#define PWM_0_DUTY_NS 16
99
#define PWM_0_PHASE 0
100
101
#define PWM_1_PERIOD_NS 200
102
#define PWM_1_DUTY_NS 144
103
#define PWM_1_PHASE 0
104
105
#define GPIO_OPS &xil_gpio_ops
106
#define GPIO_EXTRA &xil_gpio_init
107
108
#define DCACHE_INVALIDATE Xil_DCacheInvalidateRange
109
110
#endif
/* __PARAMETERS_H__ */
111
xilinx_uart.h
iio_uart_extra_ip
struct xil_uart_init_param iio_uart_extra_ip
Definition:
parameters.c:45
axi_pwm_0_extra
struct axi_pwm_init_param axi_pwm_0_extra
Definition:
common_data.c:87
xilinx_gpio.h
xil_uart_init_param
Structure holding the initialization parameters for Xilinx platform specific UART parameters.
Definition:
xilinx_uart.h:73
axi_pwm_init_param
Structure holding the initialization parameters for axi PWM.
Definition:
axi_pwm_extra.h:56
Generated by
1.8.17