Definitions specific to xilinx platform used by iio project. More...

#include <xparameters.h>
#include <xil_cache.h>
#include <xilinx_uart.h>
#include "xilinx_gpio.h"

Include dependency graph for parameters.h:

Macros
#define	UART_DEVICE_ID XPAR_AXI_UART_DEVICE_ID

#define	UART_IRQ_ID XPAR_AXI_INTC_AXI_UART_INTERRUPT_INTR

#define	UART_EXTRA &iio_uart_extra_ip

#define	UART_OPS &xil_uart_ops

#define	RX_CORE_BASEADDR XPAR_AXI_PULSAR_LVDS_BASEADDR

#define	RX_DMA_BASEADDR XPAR_AXI_PULSAR_LVDS_DMA_BASEADDR

#define	RX_CLKGEN_BASEADDR XPAR_REFERENCE_CLKGEN_BASEADDR

#define	AXI_PWMGEN_BASEADDR XPAR_AXI_PWM_GEN_BASEADDR

#define	ADC_DDR_BASEADDR XPAR_DDR_MEM_BASEADDR + 0x800000

#define	GPIO_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID

#define	GPIO_OFFSET 32 + 54

#define	GPIO_EN0_FMC GPIO_OFFSET

#define	GPIO_EN1_FMC GPIO_OFFSET+1

#define	GPIO_EN2_FMC GPIO_OFFSET+2

#define	GPIO_EN3_FMC GPIO_OFFSET+3

#define	SAMPLES_PER_CHANNEL_PLATFORM 20000

#define	MAX_SIZE_BASE_ADDR (SAMPLES_PER_CHANNEL_PLATFORM * 4)

#define	UART_BAUDRATE 115200

#define	PWM_0_PERIOD_NS 200

#define	PWM_0_DUTY_NS 16

#define	PWM_0_PHASE 0

#define	PWM_1_PERIOD_NS 200

#define	PWM_1_DUTY_NS 144

#define	PWM_1_PHASE 0

#define	GPIO_OPS &xil_gpio_ops

#define	GPIO_EXTRA &xil_gpio_init

#define	DCACHE_INVALIDATE Xil_DCacheInvalidateRange

Variables
struct xil_uart_init_param	iio_uart_extra_ip

struct axi_pwm_init_param	axi_pwm_0_extra

Detailed Description

Definitions specific to xilinx platform used by iio project.

Author: Axel Haslam (ahasl.nosp@m.am@b.nosp@m.aylib.nosp@m.re.c.nosp@m.om)

SPDX-License-Identifier: BSD-3-Clause

Macro Definition Documentation

◆ ADC_DDR_BASEADDR

#define ADC_DDR_BASEADDR XPAR_DDR_MEM_BASEADDR + 0x800000

◆ AXI_PWMGEN_BASEADDR

#define AXI_PWMGEN_BASEADDR XPAR_AXI_PWM_GEN_BASEADDR

◆ DCACHE_INVALIDATE

#define DCACHE_INVALIDATE Xil_DCacheInvalidateRange

◆ GPIO_DEVICE_ID

#define GPIO_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID

◆ GPIO_EN0_FMC

#define GPIO_EN0_FMC GPIO_OFFSET

◆ GPIO_EN1_FMC

#define GPIO_EN1_FMC GPIO_OFFSET+1

◆ GPIO_EN2_FMC

#define GPIO_EN2_FMC GPIO_OFFSET+2

◆ GPIO_EN3_FMC

#define GPIO_EN3_FMC GPIO_OFFSET+3

◆ GPIO_EXTRA

#define GPIO_EXTRA &xil_gpio_init

◆ GPIO_OFFSET

#define GPIO_OFFSET 32 + 54

◆ GPIO_OPS

#define GPIO_OPS &xil_gpio_ops

◆ MAX_SIZE_BASE_ADDR

#define MAX_SIZE_BASE_ADDR (SAMPLES_PER_CHANNEL_PLATFORM * 4)

◆ PWM_0_DUTY_NS

#define PWM_0_DUTY_NS 16

◆ PWM_0_PERIOD_NS

#define PWM_0_PERIOD_NS 200

◆ PWM_0_PHASE

#define PWM_0_PHASE 0

◆ PWM_1_DUTY_NS

#define PWM_1_DUTY_NS 144

◆ PWM_1_PERIOD_NS

#define PWM_1_PERIOD_NS 200

◆ PWM_1_PHASE

#define PWM_1_PHASE 0

◆ RX_CLKGEN_BASEADDR

#define RX_CLKGEN_BASEADDR XPAR_REFERENCE_CLKGEN_BASEADDR

◆ RX_CORE_BASEADDR

#define RX_CORE_BASEADDR XPAR_AXI_PULSAR_LVDS_BASEADDR

◆ RX_DMA_BASEADDR

#define RX_DMA_BASEADDR XPAR_AXI_PULSAR_LVDS_DMA_BASEADDR

◆ SAMPLES_PER_CHANNEL_PLATFORM

#define SAMPLES_PER_CHANNEL_PLATFORM 20000

◆ UART_BAUDRATE

#define UART_BAUDRATE 115200

◆ UART_DEVICE_ID

#define UART_DEVICE_ID XPAR_AXI_UART_DEVICE_ID

◆ UART_EXTRA

#define UART_EXTRA &iio_uart_extra_ip

◆ UART_IRQ_ID

#define UART_IRQ_ID XPAR_AXI_INTC_AXI_UART_INTERRUPT_INTR

◆ UART_OPS

#define UART_OPS &xil_uart_ops

Variable Documentation

◆ axi_pwm_0_extra

struct axi_pwm_init_param axi_pwm_0_extra

extern

◆ iio_uart_extra_ip

struct xil_uart_init_param iio_uart_extra_ip