ad9208_reg.h File Reference

AD9208 SPI Register Definition Header File. More...

#include "api_def.h"

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Macros
#define	AD9208_JESD_NOF_LANES   8
#define	AD9208_JESD_NOF_LINKS   2
#define	AD9208_JESD_NOF_SYNCOUTB   2
#define	AD9208_ADC_NOF_CH   2
#define	AD9208_ADC_CH_INDEX(x)
#define	AD9208_IF_CFG_A_REG   0x000
#define	AD9208_IF_CFG_B_REG   0x001
#define	AD9208_DEV_CFG_REG   0x002
#define	AD9208_PDN_MODE(x)
#define	AD9208_CHIP_TYPE_REG   0x003
#define	AD9208_PROD_ID_LSB_REG   0x004
#define	AD9208_PROD_ID_MSB_REG   0x005
#define	AD9208_CHIP_GRADE_REG   0x006
#define	AD9208_CH_INDEX_REG   0x008
#define	AD9208_CH_INDEX_SEL(x)
#define	AD9208_CHANNEL_PAGE_0   NO_OS_BIT(0)
#define	AD9208_CHANNEL_PAGE_1   NO_OS_BIT(1)
#define	AD9208_CHANNEL_PAGE_2   NO_OS_BIT(2)
#define	AD9208_CHANNEL_PAGE_3   NO_OS_BIT(3)
#define	AD9208_CHANNEL_PAGE_4   NO_OS_BIT(4)
#define	AD9208_CHANNEL_PAGE_5   NO_OS_BIT(5)
#define	AD9208_MAINDAC_PAGE_0   NO_OS_BIT(6)
#define	AD9208_MAINDAC_PAGE_1   NO_OS_BIT(7)
#define	AD9208_CHIP_SPI_XFER_REG   0x000F
#define	AD9208_CHIP_TRIGGER_SPI_XFER   NO_OS_BIT(0)
#define	AD9208_CHIP_PIN_CTRL0_REG   0x03F
#define	AD9208_CHIP_PDN_PIN_DISABLE   NO_OS_BIT(7)
#define	AD9208_CHIP_PIN_CTRL1_REG   0x040
#define	AD9208_CHIP_PDN_MODE(x)
#define	AD9208_CHIP_PIN_CTRL_MASK(x)
#define	AD9208_IP_CLK_CFG_REG   0x0108
#define	AD9208_IP_CLK_DIV(x)
#define	AD9208_IP_CLK_PHASE_ADJ_REG   0x0109
#define	AD9208_IP_CLK_PHASE_ADJ(x)
#define	AD9208_IP_CLK_STAT_REG   0x011B
#define	AD9208_IP_CLK_DCS1_REG   0x011C
#define	AD9208_IP_CLK_DCS2_REG   0x011E
#define	AD9208_SYSREF_CTRL_0_REG   0x0120
#define	AD9208_SYSREF_MODE_SEL(x)
#define	AD9208_SYSREF_CTRL_1_REG   0x0121
#define	AD9208_SYSREF_TRANSITION_SEL(x)
#define	AD9208_SYSREF_CLK_EDGE_SEL(x)
#define	AD9208_SYSREF_NSHOT_IGNORE(x)
#define	AD9208_SYSREF_CTRL_2_REG   0x0122
#define	AD9208_SYSREF_WIN_NEG(x)
#define	AD9208_SYSREF_WIN_POS(x)
#define	AD9208_SYSREF_CTRL_3_REG   0x0123
#define	AD9208_SYSREF_TS_DELAY(x)
#define	AD9208_SYSREF_STAT_0_REG   0x0128
#define	AD9208_SYSREF_STAT_1_REG   0x0129
#define	AD9208_SYSREF_STAT_2_REG   0x012A
#define	AD9208_BUFF_CFG_P_REG   0x1A4C
#define	AD9208_BUFF_CTRL_P(x)
#define	AD9208_BUFF_CFG_N_REG   0x1A4D
#define	AD9208_BUFF_CTRL_N(x)
#define	AD9208_CHIP_SYNC_MODE_REG   0x01FF
#define	AD9208_SYNC_TS_ENABLE   NO_OS_BIT(0)
#define	AD9208_ADC_MODE_REG   0x0200
#define	AD9208_ADC_MODE(x)
#define	AD9208_ADC_Q_IGNORE   NO_OS_BIT(5)
#define	AD9208_ADC_DCM_REG   0x0201
#define	AD9208_ADC_DCM_RATE(x)
#define	AD9208_DCM_NONE   0x0
#define	AD9208_DCM2_EN   NO_OS_BIT(0)
#define	AD9208_DCM4_EN   NO_OS_BIT(1)
#define	AD9208_DCM16_EN   NO_OS_BIT(2)
#define	AD9208_DCM3_EN   NO_OS_BIT(3)
#define	AD9208_FD_UT_LSB_REG   0x0247
#define	AD9208_FD_UT_LSB(x)
#define	AD9208_FD_UT_MSB_REG   0x0248
#define	AD9208_FD_UT_MSB(x)
#define	AD9208_FD_LT_LSB_REG   0x0249
#define	AD9208_FD_LT_LSB(x)
#define	AD9208_FD_LT_MSB_REG   0x024A
#define	AD9208_FD_LT_MSB(x)
#define	AD9208_FD_DWELL_LSB_REG   0x024B
#define	AD9208_FD_DWELL_LSB(x)
#define	AD9208_FD_DWELL_MSB_REG   0x024C
#define	AD9208_FD_DWELL_MSB(x)
#define	AD9208_DDC_SYNC_CTRL_REG   0x0300
#define	AD9208_DDC_UPDATE_MODE   NO_OS_BIT(7)
#define	AD9208_NCO_SOFT_RESET   NO_OS_BIT(4)
#define	AD9208_NCO_SYSREF_N_SHOT_MODE   NO_OS_BIT(1)
#define	AD9208_NCO_SYSREF_SYNC_EN   NO_OS_BIT(0)
#define	AD9208_DDCX_REG_OFFSET   0x20
#define	AD9208_DDCX_CTRL0_REG   0x0310
#define	AD9208_DDCX_MIXER_SEL   NO_OS_BIT(7)
#define	AD9208_DDCX_GAIN_SEL   NO_OS_BIT(6)
#define	AD9208_DDCX_NCO_IF_MODE(x)
#define	AD9208_DDCX_COMPLEX_TO_REAL   NO_OS_BIT(3)
#define	AD9208_DDCX_DCM_FILT_SEL_0(x)
#define	AD9208_DDCX_DATA_SEL_REG   0x0311
#define	AD9208_DDCX_DCM_FILT_SEL_1(x)
#define	AD9208_DDCX_Q_IP_CHB_SEL   NO_OS_BIT(2)
#define	AD9208_DDCX_I_IP_CHB_SEL   NO_OS_BIT(0)
#define	AD9208_DDCX_FTW0_REG   0x0316
#define	AD9208_DDCX_FTW1_REG   0x0317
#define	AD9208_DDCX_FTW2_REG   0x0318
#define	AD9208_DDCX_FTW3_REG   0x0319
#define	AD9208_DDCX_FTW4_REG   0x031A
#define	AD9208_DDCX_FTW5_REG   0x031B
#define	AD9208_DDCX_PO0_REG   0x031D
#define	AD9208_DDCX_PO1_REG   0x031E
#define	AD9208_DDCX_PO2_REG   0x031F
#define	AD9208_DDCX_PO3_REG   0x0320
#define	AD9208_DDCX_PO4_REG   0x0321
#define	AD9208_DDCX_PO5_REG   0x0322
#define	AD9208_DDCX_FRAC_REG_OFFSET   0x10
#define	AD9208_DDCX_MAW0_REG   0x0390
#define	AD9208_DDCX_MAW1_REG   0x0391
#define	AD9208_DDCX_MAW2_REG   0x0392
#define	AD9208_DDCX_MAW3_REG   0x0393
#define	AD9208_DDCX_MAW4_REG   0x0394
#define	AD9208_DDCX_MAW5_REG   0x0395
#define	AD9208_DDCX_MBW0_REG   0x0398
#define	AD9208_DDCX_MBW1_REG   0x0399
#define	AD9208_DDCX_MBW2_REG   0x039A
#define	AD9208_DDCX_MBW3_REG   0x039B
#define	AD9208_DDCX_MBW4_REG   0x039C
#define	AD9208_DDCX_MBW5_REG   0x039D
#define	AD9208_REG_TEST_MODE   0x0550
#define	AD9208_TESTMODE_OFF   0x0
#define	AD9208_TESTMODE_MIDSCALE_SHORT   0x1
#define	AD9208_TESTMODE_POS_FULLSCALE   0x2
#define	AD9208_TESTMODE_NEG_FULLSCALE   0x3
#define	AD9208_TESTMODE_ALT_CHECKERBOARD   0x4
#define	AD9208_TESTMODE_PN23_SEQ   0x5
#define	AD9208_TESTMODE_PN9_SEQ   0x6
#define	AD9208_TESTMODE_ONE_ZERO_TOGGLE   0x7
#define	AD9208_TESTMODE_USER   0x8
#define	AD9208_TESTMODE_RAMP   0xF
#define	AD9208_REG_OUTPUT_MODE   0x0561
#define	AD9208_OUTPUT_MODE_OFFSET_BINARY   0x0
#define	AD9208_OUTPUT_MODE_TWOS_COMPLEMENT   0x1
#define	AD9208_OP_MODE_CTRL_1_REG   0x0559
#define	AD9208_OP_MODE_CTRL_2_REG   0x055A
#define	AD9208_OP_CONV_CTRL_BIT_SEL(x)
#define	AD9208_OP_OVERANGE_CLR_REG   0x0562
#define	AD9208_OP_OVERANGE_STAT_REG   0x0563
#define	AD9208_JESD_LMFC_OFFSET_REG   0x0578
#define	AD9208_JESD_LMFC_OFFSET(x)
#define	AD9208_JESD_SERDES_PLL_CFG_REG   0x056E
#define	AD9208_JESD_SLR_CTRL(x)
#define	AD9208_JESD_SERDES_PLL_REG   0x056F
#define	AD9208_JESD_PLL_LOCK_STAT   NO_OS_BIT(7)
#define	AD9208_JESD_LINK_CTRL1_REG   0x0571
#define	AD9208_JESD_LINK_PDN   NO_OS_BIT(0)
#define	AD9208_JESD_ID_CFG_REG_OFFSET   0x3
#define	AD9208_JESD_DID_CFG_REG   0x0580
#define	AD9208_JESD_BID_CFG_REG   0x0581
#define	AD9208_JESD_BID(x)
#define	AD9208_JESD_LID0_CFG_REG   0x0583
#define	AD9208_JESD_LID0(x)
#define	AD9208_JESD_CFG_REG_OFFSET   0x8
#define	AD9208_JESD_L_SCR_CFG_REG   0x058B
#define	AD9208_JESD_SCR_EN   NO_OS_BIT(7)
#define	AD9208_JESD_LANES(x)
#define	AD9208_JESD_F_CFG_REG   0x058C
#define	AD9208_JESD_F(x)
#define	AD9208_JESD_K_CFG_REG   0x058D
#define	AD9208_JESD_K(x)
#define	AD9208_JESD_M_CFG_REG   0x058E
#define	AD9208_JESD_M(x)
#define	AD9208_JESD_CS_N_CFG_REG   0x058F
#define	AD9208_JESD_CS(x)
#define	AD9208_JESD_N(x)
#define	AD9208_JESD_SCV_NP_CFG_REG   0x0590
#define	AD9208_JESD_SUBCLASS(x)
#define	AD9208_JESD_NP(x)
#define	AD9208_JESD_S_CFG_REG   0x0591
#define	AD9208_JESD_S(x)
#define	AD9208_JESD_HD_CF_CFG_REG   0x0592
#define	AD9208_JESD_HD   NO_OS_BIT(7)
#define	AD9208_JESD_CF(x)
#define	AD9208_JESD_XBAR_CFG_REG_OFFSET   0x5
#define	AD9208_JESD_XBAR_CFG_REG   0x05B2
#define	AD9208_JESD_XBAR_LN_EVEN(x)
#define	AD9208_JESD_XBAR_LN_ODD(x)
#define	AD9208_DC_OFFSET_CAL_CTRL   0x0701
#define	AD9208_DC_OFFSET_CAL_EN   NO_OS_BIT(7)
#define	AD9208_VREF_CTRL_REG   0x18A6
#define	AD9208_EXT_VREF_MODE   NO_OS_BIT(0)
#define	AD9208_EXT_VCM_CTRL_REG   0x18E3
#define	AD9208_EXT_VCM_BUFF   NO_OS_BIT(6)
#define	AD9208_EXT_VCM_BUFF_CURR(x)
#define	AD9208_TEMP_DIODE_CTRL_REG   0x18E6
#define	AD9208_CENTRAL_DIODE_1X_EN   NO_OS_BIT(0)
#define	AD9208_CENTRAL_DIODE_20X_EN   NO_OS_BIT(1)
#define	AD9208_ANALOG_CFG_REG   0x1908
#define	AD9208_DC_COUPLE_EN(x)
#define	AD9208_FULL_SCALE_CFG_REG   0x1910
#define	AD9208_TRM_VREF(x)

Functions
int	ad9208_register_write_tbl (ad9208_handle_t *h, struct adi_reg_data *tbl, uint32_t count)
int	ad9208_register_read_block (ad9208_handle_t *h, const uint16_t address, uint8_t *data, uint32_t count)
int	ad9208_adc_select_ch (ad9208_handle_t *h, uint8_t ch)
int	ad9208_register_chip_transfer (ad9208_handle_t *h)
int	ad9208_is_sync_spi_update_enabled (ad9208_handle_t *h, uint8_t *enabled)

Detailed Description

AD9208 SPI Register Definition Header File.

Release 1.0.X

Copyright(c) 2017 Analog Devices, Inc. All Rights Reserved. This software is proprietary to Analog Devices, Inc. and its licensors. By using this software you agree to the terms of the associated Analog Devices Software License Agreement.

Macro Definition Documentation

AD9208_ADC_CH_INDEX

#define AD9208_ADC_CH_INDEX

(

x

)

Value:

(NO_OS_BIT(x)>>1)

AD9208_ADC_DCM_RATE

#define AD9208_ADC_DCM_RATE

(

x

)

Value:

(((x)&0xF)<<0)

AD9208_ADC_DCM_REG

#define AD9208_ADC_DCM_REG   0x0201

AD9208_ADC_MODE

#define AD9208_ADC_MODE

(

x

)

Value:

(((x)&0x3)<<0)

AD9208_ADC_MODE_REG

#define AD9208_ADC_MODE_REG   0x0200

AD9208_ADC_NOF_CH

#define AD9208_ADC_NOF_CH   2

AD9208_ADC_Q_IGNORE

#define AD9208_ADC_Q_IGNORE   NO_OS_BIT(5)

AD9208_ANALOG_CFG_REG

#define AD9208_ANALOG_CFG_REG   0x1908

AD9208_BUFF_CFG_N_REG

#define AD9208_BUFF_CFG_N_REG   0x1A4D

AD9208_BUFF_CFG_P_REG

#define AD9208_BUFF_CFG_P_REG   0x1A4C

AD9208_BUFF_CTRL_N

#define AD9208_BUFF_CTRL_N

(

x

)

Value:

(((x)&0x3F)<<0)

AD9208_BUFF_CTRL_P

#define AD9208_BUFF_CTRL_P

(

x

)

Value:

(((x)&0x3F)<<0)

AD9208_CENTRAL_DIODE_1X_EN

#define AD9208_CENTRAL_DIODE_1X_EN   NO_OS_BIT(0)

AD9208_CENTRAL_DIODE_20X_EN

#define AD9208_CENTRAL_DIODE_20X_EN   NO_OS_BIT(1)

AD9208_CH_INDEX_REG

#define AD9208_CH_INDEX_REG   0x008

AD9208_CH_INDEX_SEL

#define AD9208_CH_INDEX_SEL

(

x

)

Value:

(((x)&0x3)<<0)

AD9208_CHANNEL_PAGE_0

#define AD9208_CHANNEL_PAGE_0   NO_OS_BIT(0)

AD9208_CHANNEL_PAGE_1

#define AD9208_CHANNEL_PAGE_1   NO_OS_BIT(1)

AD9208_CHANNEL_PAGE_2

#define AD9208_CHANNEL_PAGE_2   NO_OS_BIT(2)

AD9208_CHANNEL_PAGE_3

#define AD9208_CHANNEL_PAGE_3   NO_OS_BIT(3)

AD9208_CHANNEL_PAGE_4

#define AD9208_CHANNEL_PAGE_4   NO_OS_BIT(4)

AD9208_CHANNEL_PAGE_5

#define AD9208_CHANNEL_PAGE_5   NO_OS_BIT(5)

AD9208_CHIP_GRADE_REG

#define AD9208_CHIP_GRADE_REG   0x006

AD9208_CHIP_PDN_MODE

#define AD9208_CHIP_PDN_MODE

(

x

)

Value:

(((x)&0xC0)<<6)

AD9208_CHIP_PDN_PIN_DISABLE

#define AD9208_CHIP_PDN_PIN_DISABLE   NO_OS_BIT(7)

AD9208_CHIP_PIN_CTRL0_REG

#define AD9208_CHIP_PIN_CTRL0_REG   0x03F

AD9208_CHIP_PIN_CTRL1_REG

#define AD9208_CHIP_PIN_CTRL1_REG   0x040

AD9208_CHIP_PIN_CTRL_MASK

#define AD9208_CHIP_PIN_CTRL_MASK

(

x

)

Value:

(0x07 << (3 * (x)))

AD9208_CHIP_SPI_XFER_REG

#define AD9208_CHIP_SPI_XFER_REG   0x000F

AD9208_CHIP_SYNC_MODE_REG

#define AD9208_CHIP_SYNC_MODE_REG   0x01FF

AD9208_CHIP_TRIGGER_SPI_XFER

#define AD9208_CHIP_TRIGGER_SPI_XFER   NO_OS_BIT(0)

AD9208_CHIP_TYPE_REG

#define AD9208_CHIP_TYPE_REG   0x003

AD9208_DC_COUPLE_EN

#define AD9208_DC_COUPLE_EN

(

x

)

Value:

(((x)&0x1)<<2)

AD9208_DC_OFFSET_CAL_CTRL

#define AD9208_DC_OFFSET_CAL_CTRL   0x0701

AD9208_DC_OFFSET_CAL_EN

#define AD9208_DC_OFFSET_CAL_EN   NO_OS_BIT(7)

AD9208_DCM16_EN

#define AD9208_DCM16_EN   NO_OS_BIT(2)

AD9208_DCM2_EN

#define AD9208_DCM2_EN   NO_OS_BIT(0)

AD9208_DCM3_EN

#define AD9208_DCM3_EN   NO_OS_BIT(3)

AD9208_DCM4_EN

#define AD9208_DCM4_EN   NO_OS_BIT(1)

AD9208_DCM_NONE

#define AD9208_DCM_NONE   0x0

AD9208_DDC_SYNC_CTRL_REG

#define AD9208_DDC_SYNC_CTRL_REG   0x0300

AD9208_DDC_UPDATE_MODE

#define AD9208_DDC_UPDATE_MODE   NO_OS_BIT(7)

AD9208_DDCX_COMPLEX_TO_REAL

#define AD9208_DDCX_COMPLEX_TO_REAL   NO_OS_BIT(3)

AD9208_DDCX_CTRL0_REG

#define AD9208_DDCX_CTRL0_REG   0x0310

AD9208_DDCX_DATA_SEL_REG

#define AD9208_DDCX_DATA_SEL_REG   0x0311

AD9208_DDCX_DCM_FILT_SEL_0

#define AD9208_DDCX_DCM_FILT_SEL_0

(

x

)

Value:

(((x)&0x7)<<0)

AD9208_DDCX_DCM_FILT_SEL_1

#define AD9208_DDCX_DCM_FILT_SEL_1

(

x

)

Value:

(((x)&0xF)<<4)

AD9208_DDCX_FRAC_REG_OFFSET

#define AD9208_DDCX_FRAC_REG_OFFSET   0x10

AD9208_DDCX_FTW0_REG

#define AD9208_DDCX_FTW0_REG   0x0316

AD9208_DDCX_FTW1_REG

#define AD9208_DDCX_FTW1_REG   0x0317

AD9208_DDCX_FTW2_REG

#define AD9208_DDCX_FTW2_REG   0x0318

AD9208_DDCX_FTW3_REG

#define AD9208_DDCX_FTW3_REG   0x0319

AD9208_DDCX_FTW4_REG

#define AD9208_DDCX_FTW4_REG   0x031A

AD9208_DDCX_FTW5_REG

#define AD9208_DDCX_FTW5_REG   0x031B

AD9208_DDCX_GAIN_SEL

#define AD9208_DDCX_GAIN_SEL   NO_OS_BIT(6)

AD9208_DDCX_I_IP_CHB_SEL

#define AD9208_DDCX_I_IP_CHB_SEL   NO_OS_BIT(0)

AD9208_DDCX_MAW0_REG

#define AD9208_DDCX_MAW0_REG   0x0390

AD9208_DDCX_MAW1_REG

#define AD9208_DDCX_MAW1_REG   0x0391

AD9208_DDCX_MAW2_REG

#define AD9208_DDCX_MAW2_REG   0x0392

AD9208_DDCX_MAW3_REG

#define AD9208_DDCX_MAW3_REG   0x0393

AD9208_DDCX_MAW4_REG

#define AD9208_DDCX_MAW4_REG   0x0394

AD9208_DDCX_MAW5_REG

#define AD9208_DDCX_MAW5_REG   0x0395

AD9208_DDCX_MBW0_REG

#define AD9208_DDCX_MBW0_REG   0x0398

AD9208_DDCX_MBW1_REG

#define AD9208_DDCX_MBW1_REG   0x0399

AD9208_DDCX_MBW2_REG

#define AD9208_DDCX_MBW2_REG   0x039A

AD9208_DDCX_MBW3_REG

#define AD9208_DDCX_MBW3_REG   0x039B

AD9208_DDCX_MBW4_REG

#define AD9208_DDCX_MBW4_REG   0x039C

AD9208_DDCX_MBW5_REG

#define AD9208_DDCX_MBW5_REG   0x039D

AD9208_DDCX_MIXER_SEL

#define AD9208_DDCX_MIXER_SEL   NO_OS_BIT(7)

AD9208_DDCX_NCO_IF_MODE

#define AD9208_DDCX_NCO_IF_MODE

(

x

)

Value:

(((x)&0x3)<<4)

AD9208_DDCX_PO0_REG

#define AD9208_DDCX_PO0_REG   0x031D

AD9208_DDCX_PO1_REG

#define AD9208_DDCX_PO1_REG   0x031E

AD9208_DDCX_PO2_REG

#define AD9208_DDCX_PO2_REG   0x031F

AD9208_DDCX_PO3_REG

#define AD9208_DDCX_PO3_REG   0x0320

AD9208_DDCX_PO4_REG

#define AD9208_DDCX_PO4_REG   0x0321

AD9208_DDCX_PO5_REG

#define AD9208_DDCX_PO5_REG   0x0322

AD9208_DDCX_Q_IP_CHB_SEL

#define AD9208_DDCX_Q_IP_CHB_SEL   NO_OS_BIT(2)

AD9208_DDCX_REG_OFFSET

#define AD9208_DDCX_REG_OFFSET   0x20

AD9208_DEV_CFG_REG

#define AD9208_DEV_CFG_REG   0x002

AD9208_EXT_VCM_BUFF

#define AD9208_EXT_VCM_BUFF   NO_OS_BIT(6)

AD9208_EXT_VCM_BUFF_CURR

#define AD9208_EXT_VCM_BUFF_CURR

(

x

)

Value:

(((x)&0x3F) << 0)

AD9208_EXT_VCM_CTRL_REG

#define AD9208_EXT_VCM_CTRL_REG   0x18E3

AD9208_EXT_VREF_MODE

#define AD9208_EXT_VREF_MODE   NO_OS_BIT(0)

AD9208_FD_DWELL_LSB

#define AD9208_FD_DWELL_LSB

(

x

)

Value:

(((x)&0xFF)<<0)

AD9208_FD_DWELL_LSB_REG

#define AD9208_FD_DWELL_LSB_REG   0x024B

AD9208_FD_DWELL_MSB

#define AD9208_FD_DWELL_MSB

(

x

)

Value:

(((x>>8)&0xFF)<<0)

AD9208_FD_DWELL_MSB_REG

#define AD9208_FD_DWELL_MSB_REG   0x024C

AD9208_FD_LT_LSB

#define AD9208_FD_LT_LSB

(

x

)

Value:

(((x)&0xFF)<<0)

AD9208_FD_LT_LSB_REG

#define AD9208_FD_LT_LSB_REG   0x0249

AD9208_FD_LT_MSB

#define AD9208_FD_LT_MSB

(

x

)

Value:

(((x>>8)&0x1F)<<0)

AD9208_FD_LT_MSB_REG

#define AD9208_FD_LT_MSB_REG   0x024A

AD9208_FD_UT_LSB

#define AD9208_FD_UT_LSB

(

x

)

Value:

(((x)&0xFF)<<0)

AD9208_FD_UT_LSB_REG

#define AD9208_FD_UT_LSB_REG   0x0247

AD9208_FD_UT_MSB

#define AD9208_FD_UT_MSB

(

x

)

Value:

(((x>>8)&0x1F)<<0)

AD9208_FD_UT_MSB_REG

#define AD9208_FD_UT_MSB_REG   0x0248

AD9208_FULL_SCALE_CFG_REG

#define AD9208_FULL_SCALE_CFG_REG   0x1910

AD9208_IF_CFG_A_REG

#define AD9208_IF_CFG_A_REG   0x000

AD9208_IF_CFG_B_REG

#define AD9208_IF_CFG_B_REG   0x001

AD9208_IP_CLK_CFG_REG

#define AD9208_IP_CLK_CFG_REG   0x0108

AD9208_IP_CLK_DCS1_REG

#define AD9208_IP_CLK_DCS1_REG   0x011C

AD9208_IP_CLK_DCS2_REG

#define AD9208_IP_CLK_DCS2_REG   0x011E

AD9208_IP_CLK_DIV

#define AD9208_IP_CLK_DIV

(

x

)

Value:

(((x)&0x3)<<0)

AD9208_IP_CLK_PHASE_ADJ

#define AD9208_IP_CLK_PHASE_ADJ

(

x

)

Value:

(((x)&0xF)<<0)

AD9208_IP_CLK_PHASE_ADJ_REG

#define AD9208_IP_CLK_PHASE_ADJ_REG   0x0109

AD9208_IP_CLK_STAT_REG

#define AD9208_IP_CLK_STAT_REG   0x011B

AD9208_JESD_BID

#define AD9208_JESD_BID

(

x

)

Value:

(((x)&0xF)<<0)

AD9208_JESD_BID_CFG_REG

#define AD9208_JESD_BID_CFG_REG   0x0581

AD9208_JESD_CF

#define AD9208_JESD_CF

(

x

)

Value:

(((x)&0x1F)<<0)

AD9208_JESD_CFG_REG_OFFSET

#define AD9208_JESD_CFG_REG_OFFSET   0x8

AD9208_JESD_CS

#define AD9208_JESD_CS

(

x

)

Value:

(((x)&0x3)<<6)

AD9208_JESD_CS_N_CFG_REG

#define AD9208_JESD_CS_N_CFG_REG   0x058F

AD9208_JESD_DID_CFG_REG

#define AD9208_JESD_DID_CFG_REG   0x0580

AD9208_JESD_F

#define AD9208_JESD_F

(

x

)

Value:

(((x)&0xF)<<0)

AD9208_JESD_F_CFG_REG

#define AD9208_JESD_F_CFG_REG   0x058C

AD9208_JESD_HD

#define AD9208_JESD_HD   NO_OS_BIT(7)

AD9208_JESD_HD_CF_CFG_REG

#define AD9208_JESD_HD_CF_CFG_REG   0x0592

AD9208_JESD_ID_CFG_REG_OFFSET

#define AD9208_JESD_ID_CFG_REG_OFFSET   0x3

AD9208_JESD_K

#define AD9208_JESD_K

(

x

)

Value:

(((x)&0x1F)<<0)

AD9208_JESD_K_CFG_REG

#define AD9208_JESD_K_CFG_REG   0x058D

AD9208_JESD_L_SCR_CFG_REG

#define AD9208_JESD_L_SCR_CFG_REG   0x058B

AD9208_JESD_LANES

#define AD9208_JESD_LANES

(

x

)

Value:

(((x)&0x1F)<<0)

AD9208_JESD_LID0

#define AD9208_JESD_LID0

(

x

)

Value:

(((x)&0x1F)<<0)

AD9208_JESD_LID0_CFG_REG

#define AD9208_JESD_LID0_CFG_REG   0x0583

AD9208_JESD_LINK_CTRL1_REG

#define AD9208_JESD_LINK_CTRL1_REG   0x0571

AD9208_JESD_LINK_PDN

#define AD9208_JESD_LINK_PDN   NO_OS_BIT(0)

AD9208_JESD_LMFC_OFFSET

#define AD9208_JESD_LMFC_OFFSET

(

x

)

Value:

(((x)&0x1F)>>0)

AD9208_JESD_LMFC_OFFSET_REG

#define AD9208_JESD_LMFC_OFFSET_REG   0x0578

AD9208_JESD_M

#define AD9208_JESD_M

(

x

)

Value:

(((x)&0x7)<<0)

AD9208_JESD_M_CFG_REG

#define AD9208_JESD_M_CFG_REG   0x058E

AD9208_JESD_N

#define AD9208_JESD_N

(

x

)

Value:

(((x)&0x1F)<<0)

AD9208_JESD_NOF_LANES

#define AD9208_JESD_NOF_LANES   8

AD9208_JESD_NOF_LINKS

#define AD9208_JESD_NOF_LINKS   2

AD9208_JESD_NOF_SYNCOUTB

#define AD9208_JESD_NOF_SYNCOUTB   2

AD9208_JESD_NP

#define AD9208_JESD_NP

(

x

)

Value:

(((x)&0x1F)<<0)

AD9208_JESD_PLL_LOCK_STAT

#define AD9208_JESD_PLL_LOCK_STAT   NO_OS_BIT(7)

AD9208_JESD_S

#define AD9208_JESD_S

(

x

)

Value:

(((x)&0x1F)<<0)

AD9208_JESD_S_CFG_REG

#define AD9208_JESD_S_CFG_REG   0x0591

AD9208_JESD_SCR_EN

#define AD9208_JESD_SCR_EN   NO_OS_BIT(7)

AD9208_JESD_SCV_NP_CFG_REG

#define AD9208_JESD_SCV_NP_CFG_REG   0x0590

AD9208_JESD_SERDES_PLL_CFG_REG

#define AD9208_JESD_SERDES_PLL_CFG_REG   0x056E

AD9208_JESD_SERDES_PLL_REG

#define AD9208_JESD_SERDES_PLL_REG   0x056F

AD9208_JESD_SLR_CTRL

#define AD9208_JESD_SLR_CTRL

(

x

)

Value:

(((x)&0xF)<<4)

AD9208_JESD_SUBCLASS

#define AD9208_JESD_SUBCLASS

(

x

)

Value:

(((x)&0x7)<<5)

AD9208_JESD_XBAR_CFG_REG

#define AD9208_JESD_XBAR_CFG_REG   0x05B2

AD9208_JESD_XBAR_CFG_REG_OFFSET

#define AD9208_JESD_XBAR_CFG_REG_OFFSET   0x5

AD9208_JESD_XBAR_LN_EVEN

#define AD9208_JESD_XBAR_LN_EVEN

(

x

)

Value:

(((x)&0x7) << 0)

AD9208_JESD_XBAR_LN_ODD

#define AD9208_JESD_XBAR_LN_ODD

(

x

)

Value:

(((x)&0x7) << 4)

AD9208_MAINDAC_PAGE_0

#define AD9208_MAINDAC_PAGE_0   NO_OS_BIT(6)

AD9208_MAINDAC_PAGE_1

#define AD9208_MAINDAC_PAGE_1   NO_OS_BIT(7)

AD9208_NCO_SOFT_RESET

#define AD9208_NCO_SOFT_RESET   NO_OS_BIT(4)

AD9208_NCO_SYSREF_N_SHOT_MODE

#define AD9208_NCO_SYSREF_N_SHOT_MODE   NO_OS_BIT(1)

AD9208_NCO_SYSREF_SYNC_EN

#define AD9208_NCO_SYSREF_SYNC_EN   NO_OS_BIT(0)

AD9208_OP_CONV_CTRL_BIT_SEL

#define AD9208_OP_CONV_CTRL_BIT_SEL

(

x

)

Value:

(((x)&0xF)>>0)

AD9208_OP_MODE_CTRL_1_REG

#define AD9208_OP_MODE_CTRL_1_REG   0x0559

AD9208_OP_MODE_CTRL_2_REG

#define AD9208_OP_MODE_CTRL_2_REG   0x055A

AD9208_OP_OVERANGE_CLR_REG

#define AD9208_OP_OVERANGE_CLR_REG   0x0562

AD9208_OP_OVERANGE_STAT_REG

#define AD9208_OP_OVERANGE_STAT_REG   0x0563

AD9208_OUTPUT_MODE_OFFSET_BINARY

#define AD9208_OUTPUT_MODE_OFFSET_BINARY   0x0

AD9208_OUTPUT_MODE_TWOS_COMPLEMENT

#define AD9208_OUTPUT_MODE_TWOS_COMPLEMENT   0x1

AD9208_PDN_MODE

#define AD9208_PDN_MODE

(

x

)

Value:

(((x)&0x3)<<0)

AD9208_PROD_ID_LSB_REG

#define AD9208_PROD_ID_LSB_REG   0x004

AD9208_PROD_ID_MSB_REG

#define AD9208_PROD_ID_MSB_REG   0x005

AD9208_REG_OUTPUT_MODE

#define AD9208_REG_OUTPUT_MODE   0x0561

AD9208_REG_TEST_MODE

#define AD9208_REG_TEST_MODE   0x0550

AD9208_SYNC_TS_ENABLE

#define AD9208_SYNC_TS_ENABLE   NO_OS_BIT(0)

AD9208_SYSREF_CLK_EDGE_SEL

#define AD9208_SYSREF_CLK_EDGE_SEL

(

x

)

Value:

(((x)&0x1)<<3)

AD9208_SYSREF_CTRL_0_REG

#define AD9208_SYSREF_CTRL_0_REG   0x0120

AD9208_SYSREF_CTRL_1_REG

#define AD9208_SYSREF_CTRL_1_REG   0x0121

AD9208_SYSREF_CTRL_2_REG

#define AD9208_SYSREF_CTRL_2_REG   0x0122

AD9208_SYSREF_CTRL_3_REG

#define AD9208_SYSREF_CTRL_3_REG   0x0123

AD9208_SYSREF_MODE_SEL

#define AD9208_SYSREF_MODE_SEL

(

x

)

Value:

(((x)&0x3)<<1)

AD9208_SYSREF_NSHOT_IGNORE

#define AD9208_SYSREF_NSHOT_IGNORE

(

x

)

Value:

(((x)&0xF)<<0)

AD9208_SYSREF_STAT_0_REG

#define AD9208_SYSREF_STAT_0_REG   0x0128

AD9208_SYSREF_STAT_1_REG

#define AD9208_SYSREF_STAT_1_REG   0x0129

AD9208_SYSREF_STAT_2_REG

#define AD9208_SYSREF_STAT_2_REG   0x012A

AD9208_SYSREF_TRANSITION_SEL

#define AD9208_SYSREF_TRANSITION_SEL

(

x

)

Value:

(((x)&0x1)<<4)

AD9208_SYSREF_TS_DELAY

#define AD9208_SYSREF_TS_DELAY

(

x

)

Value:

(((x)&0x7F)<<0)

AD9208_SYSREF_WIN_NEG

#define AD9208_SYSREF_WIN_NEG

(

x

)

Value:

(((x)&0x3)<<2)

AD9208_SYSREF_WIN_POS

#define AD9208_SYSREF_WIN_POS

(

x

)

Value:

(((x)&0x3)<<0)

AD9208_TEMP_DIODE_CTRL_REG

#define AD9208_TEMP_DIODE_CTRL_REG   0x18E6

AD9208_TESTMODE_ALT_CHECKERBOARD

#define AD9208_TESTMODE_ALT_CHECKERBOARD   0x4

AD9208_TESTMODE_MIDSCALE_SHORT

#define AD9208_TESTMODE_MIDSCALE_SHORT   0x1

AD9208_TESTMODE_NEG_FULLSCALE

#define AD9208_TESTMODE_NEG_FULLSCALE   0x3

AD9208_TESTMODE_OFF

#define AD9208_TESTMODE_OFF   0x0

AD9208_TESTMODE_ONE_ZERO_TOGGLE

#define AD9208_TESTMODE_ONE_ZERO_TOGGLE   0x7

AD9208_TESTMODE_PN23_SEQ

#define AD9208_TESTMODE_PN23_SEQ   0x5

AD9208_TESTMODE_PN9_SEQ

#define AD9208_TESTMODE_PN9_SEQ   0x6

AD9208_TESTMODE_POS_FULLSCALE

#define AD9208_TESTMODE_POS_FULLSCALE   0x2

AD9208_TESTMODE_RAMP

#define AD9208_TESTMODE_RAMP   0xF

AD9208_TESTMODE_USER

#define AD9208_TESTMODE_USER   0x8

AD9208_TRM_VREF

#define AD9208_TRM_VREF

(

x

)

Value:

(((x)&0xF)<<0)

AD9208_VREF_CTRL_REG

#define AD9208_VREF_CTRL_REG   0x18A6

Function Documentation

ad9208_adc_select_ch()

int ad9208_adc_select_ch	(	ad9208_handle_t *	h,
		uint8_t	ch )

ad9208_is_sync_spi_update_enabled()

int ad9208_is_sync_spi_update_enabled	(	ad9208_handle_t *	h,
		uint8_t *	enabled )

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ad9208_register_chip_transfer()

int ad9208_register_chip_transfer

(

ad9208_handle_t *

h

)

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ad9208_register_read_block()

int ad9208_register_read_block	(	ad9208_handle_t *	h,
		const uint16_t	address,
		uint8_t *	data,
		uint32_t	count )

ad9208_register_write_tbl()

int ad9208_register_write_tbl	(	ad9208_handle_t *	h,
		struct adi_reg_data *	tbl,
		uint32_t	count )

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