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33 #ifndef __AD9361_UTIL_H__
34 #define __AD9361_UTIL_H__
45 #include "app_config.h"
50 #define CLK_IGNORE_UNUSED NO_OS_BIT(3)
51 #define CLK_GET_RATE_NOCACHE NO_OS_BIT(6)
53 #if defined(HAVE_VERBOSE_MESSAGES)
54 #define dev_err(dev, format, ...) ({printf(format, ## __VA_ARGS__);printf("\n"); })
55 #define dev_warn(dev, format, ...) ({printf(format, ## __VA_ARGS__);printf("\n"); })
56 #if defined(HAVE_DEBUG_MESSAGES)
57 #define dev_dbg(dev, format, ...) ({printf(format, ## __VA_ARGS__);printf("\n"); })
59 #define dev_dbg(dev, format, ...) ({ if (0) printf(format, ## __VA_ARGS__); })
61 #define printk(format, ...) printf(format, ## __VA_ARGS__)
63 #define dev_err(dev, format, ...) ({ if (0) printf(format, ## __VA_ARGS__); })
64 #define dev_warn(dev, format, ...) ({ if (0) printf(format, ## __VA_ARGS__); })
65 #define dev_dbg(dev, format, ...) ({ if (0) printf(format, ## __VA_ARGS__); })
66 #define printk(format, ...) ({ if (0) printf(format, ## __VA_ARGS__); })
94 typedef SSIZE_T ssize_t;
95 #define strsep(s, ct) 0
96 #define snprintf(s, n, format, ...) 0
97 #define __func__ __FUNCTION__
110 int32_t
ilog2(int32_t x);
uint32_t pcore_version
Definition: ad9361_util.h:79
int32_t ad9361_spi_read(struct no_os_spi_desc *spi, uint32_t reg)
Definition: ad9361.c:735
Driver for the Analog Devices AXI-ADC-CORE module.
uint8_t pp_conf[3]
Definition: ad9361.h:3061
int32_t ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable)
Definition: ad9361_conv.c:107
int32_t no_os_clk_set_rate(struct ad9361_rf_phy *phy, struct refclk_scale *clk_priv, uint32_t rate)
clk_set_rate
Definition: ad9361_util.c:116
@ BB_REFCLK
Definition: ad9361.h:3261
Definition: ad9361_util.h:87
#define dev_err(dev, format,...)
Definition: ad9361_util.h:63
int32_t ad9361_clk_factor_round_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t *prate)
Definition: ad9361.c:6507
struct no_os_clk * clks[NUM_AD9361_CLKS]
Definition: ad9361.h:3346
int32_t clk_prepare_enable(struct no_os_clk *clk)
clk_prepare_enable
Definition: ad9361_util.c:49
uint32_t clk_get_rate(struct ad9361_rf_phy *phy, struct refclk_scale *clk_priv)
clk_get_rate
Definition: ad9361_util.c:61
@ BE_VERBOSE
Definition: ad9361.h:3308
#define ADI_REG_ID
Definition: ad9361_conv.c:50
struct axiadc_state * adc_state
Definition: ad9361.h:3403
void ad9361_ensm_restore_state(struct ad9361_rf_phy *phy, uint8_t ensm_state)
Definition: ad9361.c:2069
@ T1_CLK
Definition: ad9361.h:3272
int32_t no_os_clk_set_rate(struct ad9361_rf_phy *phy, struct refclk_scale *clk_priv, uint32_t rate)
clk_set_rate
Definition: ad9361_util.c:116
int32_t axi_adc_write(struct axi_adc *adc, uint32_t reg_addr, uint32_t reg_data)
AXI ADC Data Write.
Definition: axi_adc_core.c:71
#define printk(format,...)
Definition: ad9361_util.h:66
void ad9361_ensm_force_state(struct ad9361_rf_phy *phy, uint8_t ensm_state)
Definition: ad9361.c:1989
#define AXI_ADC_RSTN
Definition: axi_adc_core.h:47
Definition: ad9361.h:3414
uint8_t id_no
Definition: ad9361_util.h:74
Header file of Delay functions.
void * ERR_PTR(long error)
ERR_PTR.
Definition: ad9361_util.c:308
int32_t ilog2(int32_t x)
ilog2
Definition: ad9361_util.c:249
#define REG_TX_CLOCK_DATA_DELAY
Definition: ad9361.h:52
Definition: ad9361_util.h:72
AXI ADC Device Descriptor.
Definition: axi_adc_core.h:122
int32_t ad9361_tx_mute(struct ad9361_rf_phy *phy, uint32_t state)
Definition: ad9361.c:1706
Definition: no_os_clk.h:64
struct no_os_spi_desc * spi
Definition: ad9361.h:3336
#define LVDS_MODE
Definition: ad9361.h:702
#define AXI_ADC_REG_STATUS
Definition: axi_adc_core.h:65
Definition: ad9361_util.h:69
uint8_t rx_clk_data_delay
Definition: ad9361.h:3062
void * ERR_PTR(long error)
ERR_PTR.
Definition: ad9361_util.c:308
int32_t ilog2(int32_t x)
ilog2
Definition: ad9361_util.c:249
#define AXI_ADC_ENABLE
Definition: axi_adc_core.h:87
AD9361 Header file of Util driver.
enum ad9361_clocks parent_source
Definition: ad9361.h:3420
@ RX_RFPLL_DUMMY
Definition: ad9361.h:3277
struct no_os_clk * clk_refin
Definition: ad9361.h:3345
#define NO_OS_ARRAY_SIZE(x)
Definition: no_os_util.h:49
uint32_t ad9361_rfpll_recalc_rate(struct refclk_scale *clk_priv)
Definition: ad9361.c:7010
@ BIST_DISABLE
Definition: ad9361.h:3317
int32_t ad9361_rfpll_dummy_set_rate(struct refclk_scale *clk_priv, uint32_t rate)
Definition: ad9361.c:6995
int32_t ad9361_set_trx_clock_chain(struct ad9361_rf_phy *phy, uint32_t *rx_path_clks, uint32_t *tx_path_clks)
Definition: ad9361.c:4640
uint8_t tx_clk_data_delay
Definition: ad9361.h:3063
#define AXI_ADC_REG_DELAY(l)
Definition: axi_adc_core.h:112
int32_t ad9361_rfpll_round_rate(struct refclk_scale *clk_priv, uint32_t rate)
Definition: ad9361.c:7052
#define AXI_ADC_REG_RSTN
Definition: axi_adc_core.h:45
@ DO_IDELAY
Definition: ad9361.h:3310
#define ENSM_STATE_FDD
Definition: ad9361.h:761
@ RX_SAMPL_CLK
Definition: ad9361.h:3269
@ BIST_INJ_RX
Definition: ad9361.h:3319
#define NO_OS_BITS_PER_LONG
Definition: ad9361_util.c:44
int32_t ad9361_spi_write(struct no_os_spi_desc *spi, uint32_t reg, uint32_t val)
Definition: ad9361.c:811
int32_t ad9361_find_opt(uint8_t *field, uint32_t size, uint32_t *ret_start)
Definition: ad9361.c:982
@ TX_RFPLL
Definition: ad9361.h:3280
void no_os_mdelay(uint32_t msecs)
Wait until msecs milliseconds passed.
Definition: aducm3029_delay.c:126
uint8_t ad9361_ensm_get_state(struct ad9361_rf_phy *phy)
Definition: ad9361.c:1976
int32_t ad9361_set_trx_clock_chain_freq(struct ad9361_rf_phy *phy, uint32_t freq)
Definition: ad9361.c:4888
char * name
Definition: ad9361_util.h:83
#define AXI_ADC_PN_OOS
Definition: axi_adc_core.h:91
@ RESTORE_DEFAULT
Definition: ad9361.h:3313
int32_t ad9361_rfpll_set_rate(struct refclk_scale *clk_priv, uint32_t rate)
Definition: ad9361.c:7094
Header file of AD9361 Driver.
@ RX_REFCLK
Definition: ad9361.h:3262
Definition: ad9361_util.h:82
#define PCORE_VERSION_MAJOR(version)
Definition: ad9361_conv.c:53
Definition: ad9361_util.h:77
@ SKIP_STORE_RESULT
Definition: ad9361.h:3312
@ TX_REFCLK
Definition: ad9361.h:3263
int32_t ad9361_set_ensm_mode(struct ad9361_rf_phy *phy, bool fdd, bool pinctrl)
Definition: ad9361.c:4908
int32_t ad9361_clk_factor_set_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t parent_rate)
Definition: ad9361.c:6541
void axi_adc_idelay_set(struct axi_adc *adc, uint32_t lane, uint32_t val)
Set input/output delay primitive for specific interface line.
Definition: axi_adc_core.c:192
void ad9361_ensm_restore_prev_state(struct ad9361_rf_phy *phy)
Definition: ad9361.c:2124
int32_t axi_adc_read(struct axi_adc *adc, uint32_t reg_addr, uint32_t *reg_data)
AXI ADC Data read.
Definition: axi_adc_core.c:55
int32_t ad9361_bist_prbs(struct ad9361_rf_phy *phy, enum ad9361_bist_mode mode)
Definition: ad9361.c:1184
uint32_t ad9361_clk_factor_recalc_rate(struct refclk_scale *clk_priv, uint32_t parent_rate)
Definition: ad9361.c:6489
#define AXI_ADC_REG_CHAN_CNTRL_2(c)
Definition: axi_adc_core.h:100
enum ad9361_clocks source
Definition: ad9361.h:3419
uint32_t ad9361_rfpll_int_recalc_rate(struct refclk_scale *clk_priv, uint32_t parent_rate)
Definition: ad9361.c:6778
@ T2_CLK
Definition: ad9361.h:3271
int32_t ad9361_bist_loopback(struct ad9361_rf_phy *phy, int32_t mode)
Definition: ad9361.c:1125
#define ENSM_STATE_ALERT
Definition: ad9361.h:756
struct axi_adc * rx_adc
Definition: ad9361.h:3342
#define AXI_ADC_REG_CHAN_STATUS(c)
Definition: axi_adc_core.h:89
uint32_t clk_get_rate(struct ad9361_rf_phy *phy, struct refclk_scale *clk_priv)
clk_get_rate
Definition: ad9361_util.c:61
@ R2_CLK
Definition: ad9361.h:3266
#define AXI_ADC_REG_CHAN_CNTRL(c)
Definition: axi_adc_core.h:79
Definition: ad9361.h:3334
uint32_t find_first_bit(uint32_t word)
find_first_bit
Definition: ad9361_util.c:280
@ AXI_ADC_PN_CUSTOM
Definition: axi_adc_core.h:163
#define AXI_ADC_FORMAT_ENABLE
Definition: axi_adc_core.h:85
bool bbpll_initialized
Definition: ad9361.h:3411
uint32_t find_first_bit(uint32_t word)
find_first_bit
Definition: ad9361_util.c:280
@ CLKTF_CLK
Definition: ad9361.h:3273
struct refclk_scale * ref_clk_scale[NUM_AD9361_CLKS]
Definition: ad9361.h:3347
@ RX_RFPLL
Definition: ad9361.h:3279
@ DAC_CLK
Definition: ad9361.h:3270
int32_t ad9361_rfpll_int_set_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t parent_rate)
Definition: ad9361.c:6863
#define AXI_ADC_R1_MODE
Definition: axi_adc_core.h:50
int32_t ad9361_bbpll_set_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t parent_rate)
Definition: ad9361.c:6639
dig_tune_flags
Definition: ad9361.h:3307
@ TX_RFPLL_INT
Definition: ad9361.h:3276
uint32_t scratch_reg[16]
Definition: ad9361_util.h:89
int32_t axi_adc_set_pnsel(struct axi_adc *adc, uint32_t chan, enum axi_adc_pn_sel sel)
Set AXI ADC PN sequence.
Definition: axi_adc_core.c:115
#define AXI_ADC_STATUS
Definition: axi_adc_core.h:69
#define NO_OS_BIT(x)
Definition: no_os_util.h:45
@ DO_ODELAY
Definition: ad9361.h:3311
#define AXI_ADC_MMCM_RSTN
Definition: axi_adc_core.h:46
@ TX_RFPLL_DUMMY
Definition: ad9361.h:3278
#define AXI_ADC_DCFILT_OFFSET(x)
Definition: axi_adc_core.h:95
int32_t ad9361_dig_interface_timing_analysis(struct ad9361_rf_phy *phy, char *buf, int32_t buflen)
Definition: ad9361_conv.c:282
struct device dev
Definition: ad9361_util.h:73
@ R1_CLK
Definition: ad9361.h:3267
#define dev_dbg(dev, format,...)
Definition: ad9361_util.h:65
#define AXI_ADC_REG_CHAN_CNTRL_1(c)
Definition: axi_adc_core.h:94
int32_t ad9361_post_setup(struct ad9361_rf_phy *phy)
Definition: ad9361_conv.c:599
@ ADC_CLK
Definition: ad9361.h:3265
@ RX_RFPLL_INT
Definition: ad9361.h:3275
#define REG_RX_CLOCK_DATA_DELAY
Definition: ad9361.h:51
int32_t ad9361_bbpll_round_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t *prate)
Definition: ad9361.c:6599
uint32_t ad9361_bbpll_recalc_rate(struct refclk_scale *clk_priv, uint32_t parent_rate)
Definition: ad9361.c:6572
int32_t ad9361_dig_tune(struct ad9361_rf_phy *phy, uint32_t max_freq, enum dig_tune_flags flags)
Definition: ad9361_conv.c:519
int32_t bist_config
Definition: ad9361.h:3405
#define AXI_ADC_IQCOR_ENB
Definition: axi_adc_core.h:81
int32_t ad9361_rfpll_int_round_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t *prate)
Definition: ad9361.c:6834
int32_t clk_prepare_enable(struct no_os_clk *clk)
clk_prepare_enable
Definition: ad9361_util.c:49
@ BBPLL_CLK
Definition: ad9361.h:3264
#define DATA_CLK_DELAY(x)
Definition: ad9361.h:632
struct ad9361_phy_platform_data * pdata
Definition: ad9361.h:3353
#define REG_BIST_CONFIG
Definition: ad9361.h:564
@ CLKRF_CLK
Definition: ad9361.h:3268
uint32_t ad9361_rfpll_dummy_recalc_rate(struct refclk_scale *clk_priv)
Definition: ad9361.c:6982
#define AXI_ADC_PN_ERR
Definition: axi_adc_core.h:90
Header file of Common Driver.
int32_t bist_loopback_mode
Definition: ad9361.h:3404
@ BE_MOREVERBOSE
Definition: ad9361.h:3309
uint32_t rate
Definition: common.h:53
#define AXI_ADC_FORMAT_SIGNEXT
Definition: axi_adc_core.h:83
uint32_t int_sqrt(uint32_t x)
int_sqrt
Definition: ad9361_util.c:224
@ NUM_AD9361_CLKS
Definition: ad9361.h:3281
struct ad9361_rf_phy * phy
Definition: ad9361_util.h:78
@ AXI_ADC_PN9
Definition: axi_adc_core.h:157
#define RX_DATA_DELAY(x)
Definition: ad9361.h:633
int32_t num_channels
Definition: ad9361_util.h:84
uint32_t int_sqrt(uint32_t x)
int_sqrt
Definition: ad9361_util.c:224
struct axiadc_converter * adc_conv
Definition: ad9361.h:3402
struct axiadc_chip_info * chip_info
Definition: ad9361_util.h:88
@ TX_SAMPL_CLK
Definition: ad9361.h:3274
#define AXI_ADC_REG_CNTRL
Definition: axi_adc_core.h:49