no-OS
ad9361_util.h
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1 /***************************************************************************/
33 #ifndef __AD9361_UTIL_H__
34 #define __AD9361_UTIL_H__
35 
36 /******************************************************************************/
37 /***************************** Include Files **********************************/
38 /******************************************************************************/
39 #include <limits.h>
40 #include <stdint.h>
41 #include <stdio.h>
42 #include <stdlib.h>
43 #include "ad9361.h"
44 #include "common.h"
45 #include "app_config.h"
46 
47 /******************************************************************************/
48 /********************** Macros and Constants Definitions **********************/
49 /******************************************************************************/
50 #define CLK_IGNORE_UNUSED NO_OS_BIT(3)
51 #define CLK_GET_RATE_NOCACHE NO_OS_BIT(6)
52 
53 #if defined(HAVE_VERBOSE_MESSAGES)
54 #define dev_err(dev, format, ...) ({printf(format, ## __VA_ARGS__);printf("\n"); })
55 #define dev_warn(dev, format, ...) ({printf(format, ## __VA_ARGS__);printf("\n"); })
56 #if defined(HAVE_DEBUG_MESSAGES)
57 #define dev_dbg(dev, format, ...) ({printf(format, ## __VA_ARGS__);printf("\n"); })
58 #else
59 #define dev_dbg(dev, format, ...) ({ if (0) printf(format, ## __VA_ARGS__); })
60 #endif
61 #define printk(format, ...) printf(format, ## __VA_ARGS__)
62 #else
63 #define dev_err(dev, format, ...) ({ if (0) printf(format, ## __VA_ARGS__); })
64 #define dev_warn(dev, format, ...) ({ if (0) printf(format, ## __VA_ARGS__); })
65 #define dev_dbg(dev, format, ...) ({ if (0) printf(format, ## __VA_ARGS__); })
66 #define printk(format, ...) ({ if (0) printf(format, ## __VA_ARGS__); })
67 #endif
68 
69 struct device {
70 };
71 
72 struct spi_device {
73  struct device dev;
74  uint8_t id_no;
75 };
76 
77 struct axiadc_state {
78  struct ad9361_rf_phy *phy;
79  uint32_t pcore_version;
80 };
81 
83  char *name;
84  int32_t num_channels;
85 };
86 
89  uint32_t scratch_reg[16];
90 };
91 
92 #ifdef WIN32
93 #include "basetsd.h"
94 typedef SSIZE_T ssize_t;
95 #define strsep(s, ct) 0
96 #define snprintf(s, n, format, ...) 0
97 #define __func__ __FUNCTION__
98 #endif
99 
100 /******************************************************************************/
101 /************************ Functions Declarations ******************************/
102 /******************************************************************************/
103 int32_t clk_prepare_enable(struct no_os_clk *clk);
104 uint32_t clk_get_rate(struct ad9361_rf_phy *phy,
105  struct refclk_scale *clk_priv);
106 int32_t no_os_clk_set_rate(struct ad9361_rf_phy *phy,
107  struct refclk_scale *clk_priv,
108  uint32_t rate);
109 uint32_t int_sqrt(uint32_t x);
110 int32_t ilog2(int32_t x);
111 uint32_t find_first_bit(uint32_t word);
112 void * ERR_PTR(long error);
113 
114 #endif
axiadc_state::pcore_version
uint32_t pcore_version
Definition: ad9361_util.h:79
ad9361_spi_read
int32_t ad9361_spi_read(struct no_os_spi_desc *spi, uint32_t reg)
Definition: ad9361.c:735
axi_adc_core.h
Driver for the Analog Devices AXI-ADC-CORE module.
ad9361_phy_platform_data::port_ctrl
struct port_control port_ctrl
Definition: ad9361.h:3207
port_control::pp_conf
uint8_t pp_conf[3]
Definition: ad9361.h:3061
ad9361_hdl_loopback
int32_t ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable)
Definition: ad9361_conv.c:107
no_os_clk_set_rate
int32_t no_os_clk_set_rate(struct ad9361_rf_phy *phy, struct refclk_scale *clk_priv, uint32_t rate)
clk_set_rate
Definition: ad9361_util.c:116
BB_REFCLK
@ BB_REFCLK
Definition: ad9361.h:3261
axiadc_converter
Definition: ad9361_util.h:87
dev_err
#define dev_err(dev, format,...)
Definition: ad9361_util.h:63
ad9361_clk_factor_round_rate
int32_t ad9361_clk_factor_round_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t *prate)
Definition: ad9361.c:6507
ad9361_rf_phy::clks
struct no_os_clk * clks[NUM_AD9361_CLKS]
Definition: ad9361.h:3346
clk_prepare_enable
int32_t clk_prepare_enable(struct no_os_clk *clk)
clk_prepare_enable
Definition: ad9361_util.c:49
clk_get_rate
uint32_t clk_get_rate(struct ad9361_rf_phy *phy, struct refclk_scale *clk_priv)
clk_get_rate
Definition: ad9361_util.c:61
BE_VERBOSE
@ BE_VERBOSE
Definition: ad9361.h:3308
ADI_REG_ID
#define ADI_REG_ID
Definition: ad9361_conv.c:50
ad9361_rf_phy::adc_state
struct axiadc_state * adc_state
Definition: ad9361.h:3403
ad9361_ensm_restore_state
void ad9361_ensm_restore_state(struct ad9361_rf_phy *phy, uint8_t ensm_state)
Definition: ad9361.c:2069
T1_CLK
@ T1_CLK
Definition: ad9361.h:3272
no_os_clk_set_rate
int32_t no_os_clk_set_rate(struct ad9361_rf_phy *phy, struct refclk_scale *clk_priv, uint32_t rate)
clk_set_rate
Definition: ad9361_util.c:116
axi_adc_write
int32_t axi_adc_write(struct axi_adc *adc, uint32_t reg_addr, uint32_t reg_data)
AXI ADC Data Write.
Definition: axi_adc_core.c:71
printk
#define printk(format,...)
Definition: ad9361_util.h:66
ad9361_ensm_force_state
void ad9361_ensm_force_state(struct ad9361_rf_phy *phy, uint8_t ensm_state)
Definition: ad9361.c:1989
AXI_ADC_RSTN
#define AXI_ADC_RSTN
Definition: axi_adc_core.h:47
refclk_scale
Definition: ad9361.h:3414
spi_device::id_no
uint8_t id_no
Definition: ad9361_util.h:74
no_os_delay.h
Header file of Delay functions.
ad9361_phy_platform_data::dig_interface_tune_skipmode
uint8_t dig_interface_tune_skipmode
Definition: ad9361.h:3181
ERR_PTR
void * ERR_PTR(long error)
ERR_PTR.
Definition: ad9361_util.c:308
ilog2
int32_t ilog2(int32_t x)
ilog2
Definition: ad9361_util.c:249
REG_TX_CLOCK_DATA_DELAY
#define REG_TX_CLOCK_DATA_DELAY
Definition: ad9361.h:52
spi_device
Definition: ad9361_util.h:72
axi_adc
AXI ADC Device Descriptor.
Definition: axi_adc_core.h:122
ad9361_tx_mute
int32_t ad9361_tx_mute(struct ad9361_rf_phy *phy, uint32_t state)
Definition: ad9361.c:1706
no_os_clk
Definition: no_os_clk.h:64
ad9361_rf_phy::spi
struct no_os_spi_desc * spi
Definition: ad9361.h:3336
LVDS_MODE
#define LVDS_MODE
Definition: ad9361.h:702
AXI_ADC_REG_STATUS
#define AXI_ADC_REG_STATUS
Definition: axi_adc_core.h:65
device
Definition: ad9361_util.h:69
port_control::rx_clk_data_delay
uint8_t rx_clk_data_delay
Definition: ad9361.h:3062
ERR_PTR
void * ERR_PTR(long error)
ERR_PTR.
Definition: ad9361_util.c:308
ilog2
int32_t ilog2(int32_t x)
ilog2
Definition: ad9361_util.c:249
AXI_ADC_ENABLE
#define AXI_ADC_ENABLE
Definition: axi_adc_core.h:87
ad9361_util.h
AD9361 Header file of Util driver.
refclk_scale::parent_source
enum ad9361_clocks parent_source
Definition: ad9361.h:3420
RX_RFPLL_DUMMY
@ RX_RFPLL_DUMMY
Definition: ad9361.h:3277
ad9361_rf_phy::clk_refin
struct no_os_clk * clk_refin
Definition: ad9361.h:3345
NO_OS_ARRAY_SIZE
#define NO_OS_ARRAY_SIZE(x)
Definition: no_os_util.h:49
ad9361_rfpll_recalc_rate
uint32_t ad9361_rfpll_recalc_rate(struct refclk_scale *clk_priv)
Definition: ad9361.c:7010
BIST_DISABLE
@ BIST_DISABLE
Definition: ad9361.h:3317
ad9361_rfpll_dummy_set_rate
int32_t ad9361_rfpll_dummy_set_rate(struct refclk_scale *clk_priv, uint32_t rate)
Definition: ad9361.c:6995
ad9361_set_trx_clock_chain
int32_t ad9361_set_trx_clock_chain(struct ad9361_rf_phy *phy, uint32_t *rx_path_clks, uint32_t *tx_path_clks)
Definition: ad9361.c:4640
port_control::tx_clk_data_delay
uint8_t tx_clk_data_delay
Definition: ad9361.h:3063
AXI_ADC_REG_DELAY
#define AXI_ADC_REG_DELAY(l)
Definition: axi_adc_core.h:112
ad9361_rfpll_round_rate
int32_t ad9361_rfpll_round_rate(struct refclk_scale *clk_priv, uint32_t rate)
Definition: ad9361.c:7052
AXI_ADC_REG_RSTN
#define AXI_ADC_REG_RSTN
Definition: axi_adc_core.h:45
DO_IDELAY
@ DO_IDELAY
Definition: ad9361.h:3310
ENSM_STATE_FDD
#define ENSM_STATE_FDD
Definition: ad9361.h:761
RX_SAMPL_CLK
@ RX_SAMPL_CLK
Definition: ad9361.h:3269
BIST_INJ_RX
@ BIST_INJ_RX
Definition: ad9361.h:3319
NO_OS_BITS_PER_LONG
#define NO_OS_BITS_PER_LONG
Definition: ad9361_util.c:44
ad9361_spi_write
int32_t ad9361_spi_write(struct no_os_spi_desc *spi, uint32_t reg, uint32_t val)
Definition: ad9361.c:811
ad9361_find_opt
int32_t ad9361_find_opt(uint8_t *field, uint32_t size, uint32_t *ret_start)
Definition: ad9361.c:982
ad9361_phy_platform_data::tx_path_clks
uint32_t tx_path_clks[NUM_TX_CLOCKS]
Definition: ad9361.h:3191
TX_RFPLL
@ TX_RFPLL
Definition: ad9361.h:3280
no_os_mdelay
void no_os_mdelay(uint32_t msecs)
Wait until msecs milliseconds passed.
Definition: aducm3029_delay.c:126
ad9361_ensm_get_state
uint8_t ad9361_ensm_get_state(struct ad9361_rf_phy *phy)
Definition: ad9361.c:1976
ad9361_set_trx_clock_chain_freq
int32_t ad9361_set_trx_clock_chain_freq(struct ad9361_rf_phy *phy, uint32_t freq)
Definition: ad9361.c:4888
axiadc_chip_info::name
char * name
Definition: ad9361_util.h:83
AXI_ADC_PN_OOS
#define AXI_ADC_PN_OOS
Definition: axi_adc_core.h:91
RESTORE_DEFAULT
@ RESTORE_DEFAULT
Definition: ad9361.h:3313
ad9361_rfpll_set_rate
int32_t ad9361_rfpll_set_rate(struct refclk_scale *clk_priv, uint32_t rate)
Definition: ad9361.c:7094
ad9361.h
Header file of AD9361 Driver.
RX_REFCLK
@ RX_REFCLK
Definition: ad9361.h:3262
axiadc_chip_info
Definition: ad9361_util.h:82
PCORE_VERSION_MAJOR
#define PCORE_VERSION_MAJOR(version)
Definition: ad9361_conv.c:53
axiadc_state
Definition: ad9361_util.h:77
SKIP_STORE_RESULT
@ SKIP_STORE_RESULT
Definition: ad9361.h:3312
TX_REFCLK
@ TX_REFCLK
Definition: ad9361.h:3263
ad9361_set_ensm_mode
int32_t ad9361_set_ensm_mode(struct ad9361_rf_phy *phy, bool fdd, bool pinctrl)
Definition: ad9361.c:4908
ad9361_clk_factor_set_rate
int32_t ad9361_clk_factor_set_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t parent_rate)
Definition: ad9361.c:6541
axi_adc_idelay_set
void axi_adc_idelay_set(struct axi_adc *adc, uint32_t lane, uint32_t val)
Set input/output delay primitive for specific interface line.
Definition: axi_adc_core.c:192
ad9361_ensm_restore_prev_state
void ad9361_ensm_restore_prev_state(struct ad9361_rf_phy *phy)
Definition: ad9361.c:2124
axi_adc_read
int32_t axi_adc_read(struct axi_adc *adc, uint32_t reg_addr, uint32_t *reg_data)
AXI ADC Data read.
Definition: axi_adc_core.c:55
ad9361_bist_prbs
int32_t ad9361_bist_prbs(struct ad9361_rf_phy *phy, enum ad9361_bist_mode mode)
Definition: ad9361.c:1184
ad9361_clk_factor_recalc_rate
uint32_t ad9361_clk_factor_recalc_rate(struct refclk_scale *clk_priv, uint32_t parent_rate)
Definition: ad9361.c:6489
AXI_ADC_REG_CHAN_CNTRL_2
#define AXI_ADC_REG_CHAN_CNTRL_2(c)
Definition: axi_adc_core.h:100
refclk_scale::source
enum ad9361_clocks source
Definition: ad9361.h:3419
ad9361_rfpll_int_recalc_rate
uint32_t ad9361_rfpll_int_recalc_rate(struct refclk_scale *clk_priv, uint32_t parent_rate)
Definition: ad9361.c:6778
T2_CLK
@ T2_CLK
Definition: ad9361.h:3271
ad9361_bist_loopback
int32_t ad9361_bist_loopback(struct ad9361_rf_phy *phy, int32_t mode)
Definition: ad9361.c:1125
ENSM_STATE_ALERT
#define ENSM_STATE_ALERT
Definition: ad9361.h:756
ad9361_rf_phy::rx_adc
struct axi_adc * rx_adc
Definition: ad9361.h:3342
AXI_ADC_REG_CHAN_STATUS
#define AXI_ADC_REG_CHAN_STATUS(c)
Definition: axi_adc_core.h:89
clk_get_rate
uint32_t clk_get_rate(struct ad9361_rf_phy *phy, struct refclk_scale *clk_priv)
clk_get_rate
Definition: ad9361_util.c:61
R2_CLK
@ R2_CLK
Definition: ad9361.h:3266
AXI_ADC_REG_CHAN_CNTRL
#define AXI_ADC_REG_CHAN_CNTRL(c)
Definition: axi_adc_core.h:79
ad9361_phy_platform_data::rx2tx2
bool rx2tx2
Definition: ad9361.h:3162
ad9361_rf_phy
Definition: ad9361.h:3334
find_first_bit
uint32_t find_first_bit(uint32_t word)
find_first_bit
Definition: ad9361_util.c:280
AXI_ADC_PN_CUSTOM
@ AXI_ADC_PN_CUSTOM
Definition: axi_adc_core.h:163
ad9361_phy_platform_data::fdd
bool fdd
Definition: ad9361.h:3163
AXI_ADC_FORMAT_ENABLE
#define AXI_ADC_FORMAT_ENABLE
Definition: axi_adc_core.h:85
ad9361_rf_phy::bbpll_initialized
bool bbpll_initialized
Definition: ad9361.h:3411
find_first_bit
uint32_t find_first_bit(uint32_t word)
find_first_bit
Definition: ad9361_util.c:280
CLKTF_CLK
@ CLKTF_CLK
Definition: ad9361.h:3273
ad9361_rf_phy::ref_clk_scale
struct refclk_scale * ref_clk_scale[NUM_AD9361_CLKS]
Definition: ad9361.h:3347
RX_RFPLL
@ RX_RFPLL
Definition: ad9361.h:3279
DAC_CLK
@ DAC_CLK
Definition: ad9361.h:3270
ad9361_rfpll_int_set_rate
int32_t ad9361_rfpll_int_set_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t parent_rate)
Definition: ad9361.c:6863
AXI_ADC_R1_MODE
#define AXI_ADC_R1_MODE
Definition: axi_adc_core.h:50
ad9361_bbpll_set_rate
int32_t ad9361_bbpll_set_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t parent_rate)
Definition: ad9361.c:6639
dig_tune_flags
dig_tune_flags
Definition: ad9361.h:3307
TX_RFPLL_INT
@ TX_RFPLL_INT
Definition: ad9361.h:3276
axiadc_converter::scratch_reg
uint32_t scratch_reg[16]
Definition: ad9361_util.h:89
ad9361_phy_platform_data::ensm_pin_ctrl
bool ensm_pin_ctrl
Definition: ad9361.h:3168
axi_adc_set_pnsel
int32_t axi_adc_set_pnsel(struct axi_adc *adc, uint32_t chan, enum axi_adc_pn_sel sel)
Set AXI ADC PN sequence.
Definition: axi_adc_core.c:115
AXI_ADC_STATUS
#define AXI_ADC_STATUS
Definition: axi_adc_core.h:69
NO_OS_BIT
#define NO_OS_BIT(x)
Definition: no_os_util.h:45
DO_ODELAY
@ DO_ODELAY
Definition: ad9361.h:3311
AXI_ADC_MMCM_RSTN
#define AXI_ADC_MMCM_RSTN
Definition: axi_adc_core.h:46
TX_RFPLL_DUMMY
@ TX_RFPLL_DUMMY
Definition: ad9361.h:3278
AXI_ADC_DCFILT_OFFSET
#define AXI_ADC_DCFILT_OFFSET(x)
Definition: axi_adc_core.h:95
ad9361_dig_interface_timing_analysis
int32_t ad9361_dig_interface_timing_analysis(struct ad9361_rf_phy *phy, char *buf, int32_t buflen)
Definition: ad9361_conv.c:282
spi_device::dev
struct device dev
Definition: ad9361_util.h:73
R1_CLK
@ R1_CLK
Definition: ad9361.h:3267
dev_dbg
#define dev_dbg(dev, format,...)
Definition: ad9361_util.h:65
AXI_ADC_REG_CHAN_CNTRL_1
#define AXI_ADC_REG_CHAN_CNTRL_1(c)
Definition: axi_adc_core.h:94
ad9361_post_setup
int32_t ad9361_post_setup(struct ad9361_rf_phy *phy)
Definition: ad9361_conv.c:599
ADC_CLK
@ ADC_CLK
Definition: ad9361.h:3265
RX_RFPLL_INT
@ RX_RFPLL_INT
Definition: ad9361.h:3275
REG_RX_CLOCK_DATA_DELAY
#define REG_RX_CLOCK_DATA_DELAY
Definition: ad9361.h:51
ad9361_bbpll_round_rate
int32_t ad9361_bbpll_round_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t *prate)
Definition: ad9361.c:6599
ad9361_bbpll_recalc_rate
uint32_t ad9361_bbpll_recalc_rate(struct refclk_scale *clk_priv, uint32_t parent_rate)
Definition: ad9361.c:6572
ad9361_dig_tune
int32_t ad9361_dig_tune(struct ad9361_rf_phy *phy, uint32_t max_freq, enum dig_tune_flags flags)
Definition: ad9361_conv.c:519
ad9361_rf_phy::bist_config
int32_t bist_config
Definition: ad9361.h:3405
AXI_ADC_IQCOR_ENB
#define AXI_ADC_IQCOR_ENB
Definition: axi_adc_core.h:81
ad9361_rfpll_int_round_rate
int32_t ad9361_rfpll_int_round_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t *prate)
Definition: ad9361.c:6834
clk_prepare_enable
int32_t clk_prepare_enable(struct no_os_clk *clk)
clk_prepare_enable
Definition: ad9361_util.c:49
BBPLL_CLK
@ BBPLL_CLK
Definition: ad9361.h:3264
ad9361_phy_platform_data::rx_path_clks
uint32_t rx_path_clks[NUM_RX_CLOCKS]
Definition: ad9361.h:3190
DATA_CLK_DELAY
#define DATA_CLK_DELAY(x)
Definition: ad9361.h:632
ad9361_rf_phy::pdata
struct ad9361_phy_platform_data * pdata
Definition: ad9361.h:3353
REG_BIST_CONFIG
#define REG_BIST_CONFIG
Definition: ad9361.h:564
CLKRF_CLK
@ CLKRF_CLK
Definition: ad9361.h:3268
ad9361_rfpll_dummy_recalc_rate
uint32_t ad9361_rfpll_dummy_recalc_rate(struct refclk_scale *clk_priv)
Definition: ad9361.c:6982
AXI_ADC_PN_ERR
#define AXI_ADC_PN_ERR
Definition: axi_adc_core.h:90
common.h
Header file of Common Driver.
ad9361_rf_phy::bist_loopback_mode
int32_t bist_loopback_mode
Definition: ad9361.h:3404
BE_MOREVERBOSE
@ BE_MOREVERBOSE
Definition: ad9361.h:3309
no_os_clk::rate
uint32_t rate
Definition: common.h:53
AXI_ADC_FORMAT_SIGNEXT
#define AXI_ADC_FORMAT_SIGNEXT
Definition: axi_adc_core.h:83
int_sqrt
uint32_t int_sqrt(uint32_t x)
int_sqrt
Definition: ad9361_util.c:224
NUM_AD9361_CLKS
@ NUM_AD9361_CLKS
Definition: ad9361.h:3281
axiadc_state::phy
struct ad9361_rf_phy * phy
Definition: ad9361_util.h:78
AXI_ADC_PN9
@ AXI_ADC_PN9
Definition: axi_adc_core.h:157
RX_DATA_DELAY
#define RX_DATA_DELAY(x)
Definition: ad9361.h:633
axiadc_chip_info::num_channels
int32_t num_channels
Definition: ad9361_util.h:84
int_sqrt
uint32_t int_sqrt(uint32_t x)
int_sqrt
Definition: ad9361_util.c:224
ad9361_rf_phy::adc_conv
struct axiadc_converter * adc_conv
Definition: ad9361.h:3402
axiadc_converter::chip_info
struct axiadc_chip_info * chip_info
Definition: ad9361_util.h:88
TX_SAMPL_CLK
@ TX_SAMPL_CLK
Definition: ad9361.h:3274
AXI_ADC_REG_CNTRL
#define AXI_ADC_REG_CNTRL
Definition: axi_adc_core.h:49