Go to the documentation of this file.
39 #ifndef __AD9361_UTIL_H__
40 #define __AD9361_UTIL_H__
51 #include "app_config.h"
56 #define CLK_IGNORE_UNUSED NO_OS_BIT(3)
57 #define CLK_GET_RATE_NOCACHE NO_OS_BIT(6)
59 #if defined(HAVE_VERBOSE_MESSAGES)
60 #define dev_err(dev, format, ...) ({printf(format, ## __VA_ARGS__);printf("\n"); })
61 #define dev_warn(dev, format, ...) ({printf(format, ## __VA_ARGS__);printf("\n"); })
62 #if defined(HAVE_DEBUG_MESSAGES)
63 #define dev_dbg(dev, format, ...) ({printf(format, ## __VA_ARGS__);printf("\n"); })
65 #define dev_dbg(dev, format, ...) ({ if (0) printf(format, ## __VA_ARGS__); })
67 #define printk(format, ...) printf(format, ## __VA_ARGS__)
69 #define dev_err(dev, format, ...) ({ if (0) printf(format, ## __VA_ARGS__); })
70 #define dev_warn(dev, format, ...) ({ if (0) printf(format, ## __VA_ARGS__); })
71 #define dev_dbg(dev, format, ...) ({ if (0) printf(format, ## __VA_ARGS__); })
72 #define printk(format, ...) ({ if (0) printf(format, ## __VA_ARGS__); })
100 typedef SSIZE_T ssize_t;
101 #define strsep(s, ct) 0
102 #define snprintf(s, n, format, ...) 0
103 #define __func__ __FUNCTION__
116 int32_t
ilog2(int32_t x);
uint32_t pcore_version
Definition: ad9361_util.h:85
int32_t ad9361_spi_read(struct no_os_spi_desc *spi, uint32_t reg)
Definition: ad9361.c:741
Driver for the Analog Devices AXI-ADC-CORE module.
uint8_t pp_conf[3]
Definition: ad9361.h:3067
int32_t ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable)
Definition: ad9361_conv.c:113
int32_t no_os_clk_set_rate(struct ad9361_rf_phy *phy, struct refclk_scale *clk_priv, uint32_t rate)
clk_set_rate
Definition: ad9361_util.c:122
@ BB_REFCLK
Definition: ad9361.h:3267
Definition: ad9361_util.h:93
#define dev_err(dev, format,...)
Definition: ad9361_util.h:69
int32_t ad9361_clk_factor_round_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t *prate)
Definition: ad9361.c:6513
struct no_os_clk * clks[NUM_AD9361_CLKS]
Definition: ad9361.h:3352
int32_t clk_prepare_enable(struct no_os_clk *clk)
clk_prepare_enable
Definition: ad9361_util.c:55
uint32_t clk_get_rate(struct ad9361_rf_phy *phy, struct refclk_scale *clk_priv)
clk_get_rate
Definition: ad9361_util.c:67
@ BE_VERBOSE
Definition: ad9361.h:3314
#define ADI_REG_ID
Definition: ad9361_conv.c:56
struct axiadc_state * adc_state
Definition: ad9361.h:3409
void ad9361_ensm_restore_state(struct ad9361_rf_phy *phy, uint8_t ensm_state)
Definition: ad9361.c:2075
@ T1_CLK
Definition: ad9361.h:3278
int32_t no_os_clk_set_rate(struct ad9361_rf_phy *phy, struct refclk_scale *clk_priv, uint32_t rate)
clk_set_rate
Definition: ad9361_util.c:122
int32_t axi_adc_write(struct axi_adc *adc, uint32_t reg_addr, uint32_t reg_data)
AXI ADC Data Write.
Definition: axi_adc_core.c:77
#define printk(format,...)
Definition: ad9361_util.h:72
void ad9361_ensm_force_state(struct ad9361_rf_phy *phy, uint8_t ensm_state)
Definition: ad9361.c:1995
#define AXI_ADC_RSTN
Definition: axi_adc_core.h:53
Definition: ad9361.h:3420
uint8_t id_no
Definition: ad9361_util.h:80
Header file of Delay functions.
void * ERR_PTR(long error)
ERR_PTR.
Definition: ad9361_util.c:314
int32_t ilog2(int32_t x)
ilog2
Definition: ad9361_util.c:255
#define REG_TX_CLOCK_DATA_DELAY
Definition: ad9361.h:58
Definition: ad9361_util.h:78
AXI ADC Device Descriptor.
Definition: axi_adc_core.h:128
int32_t ad9361_tx_mute(struct ad9361_rf_phy *phy, uint32_t state)
Definition: ad9361.c:1712
Definition: no_os_clk.h:70
struct no_os_spi_desc * spi
Definition: ad9361.h:3342
#define LVDS_MODE
Definition: ad9361.h:708
#define AXI_ADC_REG_STATUS
Definition: axi_adc_core.h:71
Definition: ad9361_util.h:75
uint8_t rx_clk_data_delay
Definition: ad9361.h:3068
void * ERR_PTR(long error)
ERR_PTR.
Definition: ad9361_util.c:314
int32_t ilog2(int32_t x)
ilog2
Definition: ad9361_util.c:255
#define AXI_ADC_ENABLE
Definition: axi_adc_core.h:93
AD9361 Header file of Util driver.
enum ad9361_clocks parent_source
Definition: ad9361.h:3426
@ RX_RFPLL_DUMMY
Definition: ad9361.h:3283
struct no_os_clk * clk_refin
Definition: ad9361.h:3351
#define NO_OS_ARRAY_SIZE(x)
Definition: no_os_util.h:53
uint32_t ad9361_rfpll_recalc_rate(struct refclk_scale *clk_priv)
Definition: ad9361.c:7016
@ BIST_DISABLE
Definition: ad9361.h:3323
int32_t ad9361_rfpll_dummy_set_rate(struct refclk_scale *clk_priv, uint32_t rate)
Definition: ad9361.c:7001
int32_t ad9361_set_trx_clock_chain(struct ad9361_rf_phy *phy, uint32_t *rx_path_clks, uint32_t *tx_path_clks)
Definition: ad9361.c:4646
uint8_t tx_clk_data_delay
Definition: ad9361.h:3069
#define AXI_ADC_REG_DELAY(l)
Definition: axi_adc_core.h:118
int32_t ad9361_rfpll_round_rate(struct refclk_scale *clk_priv, uint32_t rate)
Definition: ad9361.c:7058
#define AXI_ADC_REG_RSTN
Definition: axi_adc_core.h:51
@ DO_IDELAY
Definition: ad9361.h:3316
#define ENSM_STATE_FDD
Definition: ad9361.h:767
@ RX_SAMPL_CLK
Definition: ad9361.h:3275
@ BIST_INJ_RX
Definition: ad9361.h:3325
#define NO_OS_BITS_PER_LONG
Definition: ad9361_util.c:50
int32_t ad9361_spi_write(struct no_os_spi_desc *spi, uint32_t reg, uint32_t val)
Definition: ad9361.c:817
int32_t ad9361_find_opt(uint8_t *field, uint32_t size, uint32_t *ret_start)
Definition: ad9361.c:988
@ TX_RFPLL
Definition: ad9361.h:3286
void no_os_mdelay(uint32_t msecs)
Wait until msecs milliseconds passed.
Definition: aducm3029_delay.c:132
uint8_t ad9361_ensm_get_state(struct ad9361_rf_phy *phy)
Definition: ad9361.c:1982
int32_t ad9361_set_trx_clock_chain_freq(struct ad9361_rf_phy *phy, uint32_t freq)
Definition: ad9361.c:4894
char * name
Definition: ad9361_util.h:89
#define AXI_ADC_PN_OOS
Definition: axi_adc_core.h:97
@ RESTORE_DEFAULT
Definition: ad9361.h:3319
int32_t ad9361_rfpll_set_rate(struct refclk_scale *clk_priv, uint32_t rate)
Definition: ad9361.c:7100
Header file of AD9361 Driver.
@ RX_REFCLK
Definition: ad9361.h:3268
Definition: ad9361_util.h:88
#define PCORE_VERSION_MAJOR(version)
Definition: ad9361_conv.c:59
Definition: ad9361_util.h:83
@ SKIP_STORE_RESULT
Definition: ad9361.h:3318
@ TX_REFCLK
Definition: ad9361.h:3269
int32_t ad9361_set_ensm_mode(struct ad9361_rf_phy *phy, bool fdd, bool pinctrl)
Definition: ad9361.c:4914
int32_t ad9361_clk_factor_set_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t parent_rate)
Definition: ad9361.c:6547
void axi_adc_idelay_set(struct axi_adc *adc, uint32_t lane, uint32_t val)
Set input/output delay primitive for specific interface line.
Definition: axi_adc_core.c:198
void ad9361_ensm_restore_prev_state(struct ad9361_rf_phy *phy)
Definition: ad9361.c:2130
int32_t axi_adc_read(struct axi_adc *adc, uint32_t reg_addr, uint32_t *reg_data)
AXI ADC Data read.
Definition: axi_adc_core.c:61
int32_t ad9361_bist_prbs(struct ad9361_rf_phy *phy, enum ad9361_bist_mode mode)
Definition: ad9361.c:1190
uint32_t ad9361_clk_factor_recalc_rate(struct refclk_scale *clk_priv, uint32_t parent_rate)
Definition: ad9361.c:6495
#define AXI_ADC_REG_CHAN_CNTRL_2(c)
Definition: axi_adc_core.h:106
enum ad9361_clocks source
Definition: ad9361.h:3425
uint32_t ad9361_rfpll_int_recalc_rate(struct refclk_scale *clk_priv, uint32_t parent_rate)
Definition: ad9361.c:6784
@ T2_CLK
Definition: ad9361.h:3277
int32_t ad9361_bist_loopback(struct ad9361_rf_phy *phy, int32_t mode)
Definition: ad9361.c:1131
#define ENSM_STATE_ALERT
Definition: ad9361.h:762
struct axi_adc * rx_adc
Definition: ad9361.h:3348
#define AXI_ADC_REG_CHAN_STATUS(c)
Definition: axi_adc_core.h:95
uint32_t clk_get_rate(struct ad9361_rf_phy *phy, struct refclk_scale *clk_priv)
clk_get_rate
Definition: ad9361_util.c:67
@ R2_CLK
Definition: ad9361.h:3272
#define AXI_ADC_REG_CHAN_CNTRL(c)
Definition: axi_adc_core.h:85
Definition: ad9361.h:3340
uint32_t find_first_bit(uint32_t word)
find_first_bit
Definition: ad9361_util.c:286
@ AXI_ADC_PN_CUSTOM
Definition: axi_adc_core.h:169
#define AXI_ADC_FORMAT_ENABLE
Definition: axi_adc_core.h:91
bool bbpll_initialized
Definition: ad9361.h:3417
uint32_t find_first_bit(uint32_t word)
find_first_bit
Definition: ad9361_util.c:286
@ CLKTF_CLK
Definition: ad9361.h:3279
struct refclk_scale * ref_clk_scale[NUM_AD9361_CLKS]
Definition: ad9361.h:3353
@ RX_RFPLL
Definition: ad9361.h:3285
@ DAC_CLK
Definition: ad9361.h:3276
int32_t ad9361_rfpll_int_set_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t parent_rate)
Definition: ad9361.c:6869
#define AXI_ADC_R1_MODE
Definition: axi_adc_core.h:56
int32_t ad9361_bbpll_set_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t parent_rate)
Definition: ad9361.c:6645
dig_tune_flags
Definition: ad9361.h:3313
@ TX_RFPLL_INT
Definition: ad9361.h:3282
uint32_t scratch_reg[16]
Definition: ad9361_util.h:95
int32_t axi_adc_set_pnsel(struct axi_adc *adc, uint32_t chan, enum axi_adc_pn_sel sel)
Set AXI ADC PN sequence.
Definition: axi_adc_core.c:121
#define AXI_ADC_STATUS
Definition: axi_adc_core.h:75
#define NO_OS_BIT(x)
Definition: no_os_util.h:51
@ DO_ODELAY
Definition: ad9361.h:3317
#define AXI_ADC_MMCM_RSTN
Definition: axi_adc_core.h:52
@ TX_RFPLL_DUMMY
Definition: ad9361.h:3284
#define AXI_ADC_DCFILT_OFFSET(x)
Definition: axi_adc_core.h:101
int32_t ad9361_dig_interface_timing_analysis(struct ad9361_rf_phy *phy, char *buf, int32_t buflen)
Definition: ad9361_conv.c:288
struct device dev
Definition: ad9361_util.h:79
@ R1_CLK
Definition: ad9361.h:3273
#define dev_dbg(dev, format,...)
Definition: ad9361_util.h:71
#define AXI_ADC_REG_CHAN_CNTRL_1(c)
Definition: axi_adc_core.h:100
int32_t ad9361_post_setup(struct ad9361_rf_phy *phy)
Definition: ad9361_conv.c:605
@ ADC_CLK
Definition: ad9361.h:3271
@ RX_RFPLL_INT
Definition: ad9361.h:3281
#define REG_RX_CLOCK_DATA_DELAY
Definition: ad9361.h:57
int32_t ad9361_bbpll_round_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t *prate)
Definition: ad9361.c:6605
uint32_t ad9361_bbpll_recalc_rate(struct refclk_scale *clk_priv, uint32_t parent_rate)
Definition: ad9361.c:6578
int32_t ad9361_dig_tune(struct ad9361_rf_phy *phy, uint32_t max_freq, enum dig_tune_flags flags)
Definition: ad9361_conv.c:525
int32_t bist_config
Definition: ad9361.h:3411
#define AXI_ADC_IQCOR_ENB
Definition: axi_adc_core.h:87
int32_t ad9361_rfpll_int_round_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t *prate)
Definition: ad9361.c:6840
int32_t clk_prepare_enable(struct no_os_clk *clk)
clk_prepare_enable
Definition: ad9361_util.c:55
@ BBPLL_CLK
Definition: ad9361.h:3270
#define DATA_CLK_DELAY(x)
Definition: ad9361.h:638
struct ad9361_phy_platform_data * pdata
Definition: ad9361.h:3359
#define REG_BIST_CONFIG
Definition: ad9361.h:570
@ CLKRF_CLK
Definition: ad9361.h:3274
uint32_t ad9361_rfpll_dummy_recalc_rate(struct refclk_scale *clk_priv)
Definition: ad9361.c:6988
#define AXI_ADC_PN_ERR
Definition: axi_adc_core.h:96
Header file of Common Driver.
int32_t bist_loopback_mode
Definition: ad9361.h:3410
@ BE_MOREVERBOSE
Definition: ad9361.h:3315
uint32_t rate
Definition: common.h:59
#define AXI_ADC_FORMAT_SIGNEXT
Definition: axi_adc_core.h:89
uint32_t int_sqrt(uint32_t x)
int_sqrt
Definition: ad9361_util.c:230
@ NUM_AD9361_CLKS
Definition: ad9361.h:3287
struct ad9361_rf_phy * phy
Definition: ad9361_util.h:84
@ AXI_ADC_PN9
Definition: axi_adc_core.h:163
#define RX_DATA_DELAY(x)
Definition: ad9361.h:639
int32_t num_channels
Definition: ad9361_util.h:90
uint32_t int_sqrt(uint32_t x)
int_sqrt
Definition: ad9361_util.c:230
struct axiadc_converter * adc_conv
Definition: ad9361.h:3408
struct axiadc_chip_info * chip_info
Definition: ad9361_util.h:94
@ TX_SAMPL_CLK
Definition: ad9361.h:3280
#define AXI_ADC_REG_CNTRL
Definition: axi_adc_core.h:55