ad9361.h File Reference

Header file of AD9361 Driver. More...

#include <stdint.h>
#include "no_os_gpio.h"
#include "common.h"
#include "ad9361_ext_band_ctrl.h"

Include dependency graph for ad9361.h:

Classes
struct	gain_table_info
struct	rf_gain_ctrl
struct	gain_control
struct	auxdac_control
struct	rssi_control
struct	rx_gain_info
struct	port_control
struct	ctrl_outs_control
struct	elna_control
struct	auxadc_control
struct	gpo_control
struct	tx_monitor_control
struct	ad9361_phy_platform_data
struct	rf_rx_gain
struct	rf_rssi
struct	SynthLUT
struct	ad9361_debugfs_entry
struct	ad9361_fastlock_entry
struct	ad9361_fastlock
struct	ad9361_rf_phy
struct	refclk_scale
struct	ad9361_dig_tune_data

Macros
#define	REG_SPI_CONF   0x000 /* SPI Configuration */
#define	REG_MULTICHIP_SYNC_AND_TX_MON_CTRL   0x001 /* Multi-Chip Sync and Tx Mon Control */
#define	REG_TX_ENABLE_FILTER_CTRL   0x002 /* Tx Enable & Filter Control */
#define	REG_RX_ENABLE_FILTER_CTRL   0x003 /* Rx Enable & Filter Control */
#define	REG_INPUT_SELECT   0x004 /* Input Select */
#define	REG_RFPLL_DIVIDERS   0x005 /* RFPLL Dividers */
#define	REG_RX_CLOCK_DATA_DELAY   0x006 /* Rx Clock & Data Delay */
#define	REG_TX_CLOCK_DATA_DELAY   0x007 /* Tx Clock & Data Delay */
#define	REG_CLOCK_ENABLE   0x009 /* Clock Enable */
#define	REG_BBPLL   0x00A /* BBPLL */
#define	REG_TEMP_OFFSET   0x00B /* Offset */
#define	REG_START_TEMP_READING   0x00C /* Start Temp Reading */
#define	REG_TEMP_SENSE2   0x00D /* Temp Sense2 */
#define	REG_TEMPERATURE   0x00E /* Temperature */
#define	REG_TEMP_SENSOR_CONFIG   0x00F /* Temp Sensor Config */
#define	REG_PARALLEL_PORT_CONF_1   0x010 /* Parallel Port Configuration 1 */
#define	REG_PARALLEL_PORT_CONF_2   0x011 /* Parallel Port Configuration 2 */
#define	REG_PARALLEL_PORT_CONF_3   0x012 /* Parallel Port Configuration 3 */
#define	REG_ENSM_MODE   0x013 /* ENSM Mode */
#define	REG_ENSM_CONFIG_1   0x014 /* ENSM Config 1 */
#define	REG_ENSM_CONFIG_2   0x015 /* ENSM Config 2 */
#define	REG_CALIBRATION_CTRL   0x016 /* Calibration Control */
#define	REG_STATE   0x017 /* State */
#define	REG_AUXDAC_1_WORD   0x018 /* AuxDAC 1 Word */
#define	REG_AUXDAC_2_WORD   0x019 /* AuxDAC 2 Word */
#define	REG_AUXDAC_1_CONFIG   0x01A /* AuxDAC 1 Config */
#define	REG_AUXDAC_2_CONFIG   0x01B /* AuxDAC 2 Config */
#define	REG_AUXADC_CLOCK_DIVIDER   0x01C /* AuxADC Clock Divider */
#define	REG_AUXADC_CONFIG   0x01D /* Aux ADC Config */
#define	REG_AUXADC_WORD_MSB   0x01E /* AuxADC Word MSB */
#define	REG_AUXADC_LSB   0x01F /* AuxADC LSB */
#define	REG_AUTO_GPO   0x020 /* Auto GPO */
#define	REG_AGC_GAIN_LOCK_DELAY   0x021 /* AGC Gain Lock Delay */
#define	REG_AGC_ATTACK_DELAY   0x022 /* AGC Attack Delay */
#define	REG_AUXDAC_ENABLE_CTRL   0x023 /* AuxDAC Enable Control */
#define	REG_RX_LOAD_SYNTH_DELAY   0x024 /* RX Load Synth Delay */
#define	REG_TX_LOAD_SYNTH_DELAY   0x025 /* TX Load Synth Delay */
#define	REG_EXTERNAL_LNA_CTRL   0x026 /* External LNA control */
#define	REG_GPO_FORCE_AND_INIT   0x027 /* GPO Force and Init */
#define	REG_GPO0_RX_DELAY   0x028 /* GPO0 Rx delay */
#define	REG_GPO1_RX_DELAY   0x029 /* GPO1 Rx delay */
#define	REG_GPO2_RX_DELAY   0x02A /* GPO2 Rx delay */
#define	REG_GPO3_RX_DELAY   0x02B /* GPO3 Rx delay */
#define	REG_GPO0_TX_DELAY   0x02C /* GPO0 Tx Delay */
#define	REG_GPO1_TX_DELAY   0x02D /* GPO1 Tx Delay */
#define	REG_GPO2_TX_DELAY   0x02E /* GPO2 Tx Delay */
#define	REG_GPO3_TX_DELAY   0x02F /* GPO3 Tx Delay */
#define	REG_AUXDAC1_RX_DELAY   0x030 /* AuxDAC1 Rx Delay */
#define	REG_AUXDAC1_TX_DELAY   0x031 /* AuxDAC1 Tx Delay */
#define	REG_AUXDAC2_RX_DELAY   0x032 /* AuxDAC2 Rx Delay */
#define	REG_AUXDAC2_TX_DELAY   0x033 /* AuxDAC2 Tx Delay */
#define	REG_CTRL_OUTPUT_POINTER   0x035 /* Control Output Pointer */
#define	REG_CTRL_OUTPUT_ENABLE   0x036 /* Control Output Enable */
#define	REG_PRODUCT_ID   0x037 /* Product ID */
#define	REG_REFERENCE_CLOCK_CYCLES   0x03A /* Reference Clock Cycles */
#define	REG_DIGITAL_IO_CTRL   0x03B /* Digital I/O Control */
#define	REG_LVDS_BIAS_CTRL   0x03C /* LVDS Bias control */
#define	REG_LVDS_INVERT_CTRL1   0x03D /* LVDS Invert control1 */
#define	REG_LVDS_INVERT_CTRL2   0x03E /* LVDS Invert control2 */
#define	REG_SDM_CTRL_1   0x03F /* SDM Control 1 */
#define	REG_FRACT_BB_FREQ_WORD_1   0x041 /* Fractional BB Freq Word 1 */
#define	REG_FRACT_BB_FREQ_WORD_2   0x042 /* Fractional BB Freq Word 2 */
#define	REG_FRACT_BB_FREQ_WORD_3   0x043 /* Fractional BB Freq Word 3 */
#define	REG_INTEGER_BB_FREQ_WORD   0x044 /* Integer BB Freq Word */
#define	REG_CLOCK_CTRL   0x045 /* Clock Control */
#define	REG_CP_CURRENT   0x046 /* CP Current */
#define	REG_CP_BLEED_CURRENT   0x047 /* CP Bleed Current */
#define	REG_LOOP_FILTER_1   0x048 /* Loop Filter 1 */
#define	REG_LOOP_FILTER_2   0x049 /* Loop Filter 2 */
#define	REG_LOOP_FILTER_3   0x04A /* Loop Filter 3 */
#define	REG_VCO_CTRL   0x04B /* VCO Control */
#define	REG_VCO_PROGRAM_1   0x04C
#define	REG_VCO_PROGRAM_2   0x04D
#define	REG_SDM_CTRL   0x04E /* SDM Control */
#define	REG_RX_SYNTH_POWER_DOWN_OVERRIDE   0x050 /* Rx Synth Power Down Override */
#define	REG_TX_SYNTH_POWER_DOWN_OVERRIDE   0x051 /* TX Synth Power Down Override */
#define	REG_RX_ANALOG_POWER_DOWN_OVERRIDE_1   0x052 /* Rx Analog Power Down Override 1 */
#define	REG_RX_ANALOG_POWER_DOWN_OVERRIDE_2   0x053 /* Rx Analog Power Down Override 2 */
#define	REG_RX1_ADC_POWER_DOWN_OVERRIDE   0x054 /* Rx1 ADC Power Down Override */
#define	REG_RX2_ADC_POWER_DOWN_OVERRIDE   0x055 /* Rx2 ADC Power Down Override */
#define	REG_TX_ANALOG_POWER_DOWN_OVERRIDE_1   0x056 /* Tx Analog Power Down Override 1 */
#define	REG_ANALOG_POWER_DOWN_OVERRIDE   0x057 /* Analog Power Down Override */
#define	REG_MISC_POWER_DOWN_OVERRIDE   0x058 /* Misc Power Down Override */
#define	REG_CH_1_OVERFLOW   0x05E /* CH 1 Overflow */
#define	REG_CH_2_OVERFLOW   0x05F /* CH 2 Overflow */
#define	REG_TX_FILTER_COEF_ADDR   0x060 /* TX Filter Coefficient Address */
#define	REG_TX_FILTER_COEF_WRITE_DATA_1   0x061 /* TX Filter Coefficient Write Data 1 */
#define	REG_TX_FILTER_COEF_WRITE_DATA_2   0x062 /* TX Filter Coefficient Write Data 2 */
#define	REG_TX_FILTER_COEF_READ_DATA_1   0x063 /* TX Filter Coefficient Read Data 1 */
#define	REG_TX_FILTER_COEF_READ_DATA_2   0x064 /* TX Filter Coefficient Read Data 2 */
#define	REG_TX_FILTER_CONF   0x065 /* TX Filter Configuration */
#define	REG_TX_MON_LOW_GAIN   0x067 /* Tx Mon Low Gain */
#define	REG_TX_MON_HIGH_GAIN   0x068 /* Tx Mon High Gain */
#define	REG_TX_MON_DELAY   0x069 /* Tx Mon Delay */
#define	REG_TX_LEVEL_THRESH   0x06A /* Tx Level Threshold */
#define	REG_TX_RSSI1   0x06B /* TX RSSI1 */
#define	REG_TX_RSSI2   0x06C /* TX RSSI2 */
#define	REG_TX_RSSI_LSB   0x06D /* TX RSSI LSB */
#define	REG_TPM_MODE_ENABLE   0x06E /* TPM Mode Enable */
#define	REG_TX_MON_TEMP_GAIN_COEF   0x06F /* Temp Gain Coefficient */
#define	REG_TX_MON_1_CONFIG   0x070 /* Tx Mon 1 Config */
#define	REG_TX_MON_2_CONFIG   0x071 /* Tx Mon 2 Config */
#define	REG_TX1_ATTEN_0   0x073 /* Tx1 Atten 0 */
#define	REG_TX1_ATTEN_1   0x074 /* Tx1 Atten 1 */
#define	REG_TX2_ATTEN_0   0x075 /* Tx2 Atten 0 */
#define	REG_TX2_ATTEN_1   0x076 /* Tx2 Atten 1 */
#define	REG_TX_ATTEN_OFFSET   0x077 /* Tx Atten Offset */
#define	REG_TX_ATTEN_THRESH   0x078 /* Tx Atten Threshold */
#define	REG_TX1_DIG_ATTEN   0x079 /* Tx1 Dig Attenuation */
#define	REG_TX2_DIG_ATTEN   0x07C /* Tx2 Dig Attenuation */
#define	REG_TX1_SYMBOL_ATTEN   0x07F /* TX1 Symbol Attenuation */
#define	REG_TX2_SYMBOL_ATTEN   0x080 /* TX2 Symbol Attenuation */
#define	REG_TX_SYMBOL_ATTEN_CONFIG   0x081 /* TX Symbol Atten Config */
#define	REG_TX1_OUT_1_PHASE_CORR   0x08E /* Tx1 Out 1 Phase Corr */
#define	REG_TX1_OUT_1_GAIN_CORR   0x08F /* Tx1 Out 1 Gain Corr */
#define	REG_TX2_OUT_1_PHASE_CORR   0x090 /* Tx2 Out 1 Phase Corr */
#define	REG_TX2_OUT_1_GAIN_CORR   0x091 /* Tx2 Out 1 Gain Corr */
#define	REG_TX1_OUT_1_OFFSET_I   0x092 /* Tx1 Out 1 Offset I */
#define	REG_TX1_OUT_1_OFFSET_Q   0x093 /* Tx1 Out 1 Offset Q */
#define	REG_TX2_OUT_1_OFFSET_I   0x094 /* Tx2 Out 1 Offset I */
#define	REG_TX2_OUT_1_OFFSET_Q   0x095 /* Tx2 Out 1 Offset Q */
#define	REG_TX1_OUT_2_PHASE_CORR   0x096 /* Tx1 Out 2 Phase Corr */
#define	REG_TX1_OUT_2_GAIN_CORR   0x097 /* Tx1 Out 2 Gain Corr */
#define	REG_TX2_OUT_2_PHASE_CORR   0x098 /* Tx2 Out 2 Phase Corr */
#define	REG_TX2_OUT_2_GAIN_CORR   0x099 /* Tx2 Out 2 Gain Corr */
#define	REG_TX1_OUT_2_OFFSET_I   0x09A /* Tx1 Out 2 Offset I */
#define	REG_TX1_OUT_2_OFFSET_Q   0x09B /* Tx1 Out 2 Offset Q */
#define	REG_TX2_OUT_2_OFFSET_I   0x09C /* Tx2 Out 2 Offset I */
#define	REG_TX2_OUT_2_OFFSET_Q   0x09D /* Tx2 Out 2 Offset Q */
#define	REG_TX_FORCE_BITS   0x09F /* Force Bits */
#define	REG_QUAD_CAL_NCO_FREQ_PHASE_OFFSET   0x0A0 /* Quad Cal NCO Freq & Phase Offset */
#define	REG_QUAD_CAL_CTRL   0x0A1 /* Quad Cal Control */
#define	REG_KEXP_1   0x0A2 /* Kexp 1 */
#define	REG_KEXP_2   0x0A3 /* Kexp 2 */
#define	REG_QUAD_SETTLE_COUNT   0x0A4 /* QUAD Settle count */
#define	REG_MAG_FTEST_THRESH   0x0A5 /* Mag. Ftest Thresh */
#define	REG_MAG_FTEST_THRESH_2   0x0A6 /* Mag. Ftest Thresh 2 */
#define	REG_QUAD_CAL_STATUS_TX1   0x0A7 /* Quad cal status Tx1 */
#define	REG_QUAD_CAL_STATUS_TX2   0x0A8 /* Quad cal status Tx2 */
#define	REG_QUAD_CAL_COUNT   0x0A9 /* Quad cal Count */
#define	REG_TX_QUAD_FULL_LMT_GAIN   0x0AA /* Tx Quad Full/LMT Gain */
#define	REG_SQUARER_CONFIG   0x0AB /* Squarer Config */
#define	REG_TX_QUAD_CAL_ATTEN   0x0AC /* TX Quad Cal Atten */
#define	REG_THRESH_ACCUM   0x0AD /* Thresh Accum */
#define	REG_TX_QUAD_LPF_GAIN   0x0AE /* Tx Quad LPF Gain */
#define	REG_TXDAC_VDS_I   0x0B0 /* TxDAC Vds I */
#define	REG_TXDAC_VDS_Q   0x0B1 /* TxDAC Vds Q */
#define	REG_TXDAC_GN_I   0x0B2 /* TxDAC gn I */
#define	REG_TXDAC_GN_Q   0x0B3 /* TxDAC gn Q */
#define	REG_TXBBF_OPAMP_A   0x0C0 /* TxBBF OpAmp A */
#define	REG_TXBBF_OPAMP_B   0x0C1 /* TxBBF OpAmp B */
#define	REG_TX_BBF_R1   0x0C2 /* Tx BBF R1 */
#define	REG_TX_BBF_R2   0x0C3 /* Tx BBF R2 */
#define	REG_TX_BBF_R3   0x0C4 /* Tx BBF R3 */
#define	REG_TX_BBF_R4   0x0C5 /* Tx BBF R4 */
#define	REG_TX_BBF_RP   0x0C6 /* Tx BBF RP */
#define	REG_TX_BBF_C1   0x0C7 /* Tx BBF C1 */
#define	REG_TX_BBF_C2   0x0C8 /* Tx BBF C2 */
#define	REG_TX_BBF_CP   0x0C9 /* Tx BBF Cp */
#define	REG_TX_TUNE_CTRL   0x0CA /* Tx Tune Control */
#define	REG_TX_BBF_R2B   0x0CB /* Tx BBF R2b */
#define	REG_TX_BBF_TUNE   0x0CC /* Tx BBF Tune */
#define	REG_CONFIG0   0x0D0 /* Config0 */
#define	REG_RESISTOR   0x0D1 /* Resistor */
#define	REG_CAPACITOR   0x0D2 /* Capacitor */
#define	REG_LO_CM   0x0D3 /* LO CM */
#define	REG_TX_BBF_TUNE_DIVIDER   0x0D6 /* TX BBF Tune Divider */
#define	REG_TX_BBF_TUNE_MODE   0x0D7 /* TX BBF Tune Mode */
#define	REG_RX_FILTER_COEF_ADDR   0x0F0 /* Rx Filter Coeff Addr */
#define	REG_RX_FILTER_COEF_DATA_1   0x0F1 /* Rx Filter Coeff Data 1 */
#define	REG_RX_FILTER_COEF_DATA_2   0x0F2 /* Rx Filter Coeff Data 2 */
#define	REG_RX_FILTER_COEF_READ_DATA_1   0x0F3 /* Rx Filter Coeff Read Data 1 */
#define	REG_RX_FILTER_COEF_READ_DATA_2   0x0F4 /* Rx Filter Coeff Read Data 2 */
#define	REG_RX_FILTER_CONFIG   0x0F5 /* Rx Filter Config */
#define	REG_RX_FILTER_GAIN   0x0F6 /* Rx Filter Gain */
#define	REG_AGC_CONFIG_1   0x0FA /* AGC Config1 */
#define	REG_AGC_CONFIG_2   0x0FB /* AGC config2 */
#define	REG_AGC_CONFIG_3   0x0FC /* AGC Config3 */
#define	REG_MAX_LMT_FULL_GAIN   0x0FD /* Max LMT/Full Gain */
#define	REG_PEAK_WAIT_TIME   0x0FE /* Peak Wait Time */
#define	REG_DIGITAL_GAIN   0x100 /* Digital Gain */
#define	REG_AGC_LOCK_LEVEL   0x101 /* AGC Lock Level */
#define	REG_ADC_NOISE_CORRECTION_FACTOR   0x102 /* ADC noise Correction Factor */
#define	REG_GAIN_STP_CONFIG1   0x103 /* Gain Step Config1 */
#define	REG_ADC_SMALL_OVERLOAD_THRESH   0x104 /* ADC Small Overload Threshold */
#define	REG_ADC_LARGE_OVERLOAD_THRESH   0x105 /* ADC Large Overload Threshold */
#define	REG_GAIN_STP_CONFIG_2   0x106 /* Gain Step Config 2 */
#define	REG_SMALL_LMT_OVERLOAD_THRESH   0x107 /* Small LMT Overload Threshold */
#define	REG_LARGE_LMT_OVERLOAD_THRESH   0x108 /* Large LMT Overload Threshold */
#define	REG_RX1_MANUAL_LMT_FULL_GAIN   0x109 /* Rx1 Manual LMT/Full Gain */
#define	REG_RX1_MANUAL_LPF_GAIN   0x10A /* Rx1 Manual LPF gain */
#define	REG_RX1_MANUAL_DIGITALFORCED_GAIN   0x10B /* Rx1 Manual Digital/Forced Gain */
#define	REG_RX2_MANUAL_LMT_FULL_GAIN   0x10C /* Rx2 Manual LMT/Full Gain */
#define	REG_RX2_MANUAL_LPF_GAIN   0x10D /* Rx2 Manual LPF Gain */
#define	REG_RX2_MANUAL_DIGITALFORCED_GAIN   0x10E /* Rx2 Manual Digital/Forced Gain */
#define	REG_FAST_CONFIG_1   0x110 /* Config 1 */
#define	REG_FAST_CONFIG_2_SETTLING_DELAY   0x111 /* Config 2 & Settling Delay */
#define	REG_FAST_ENERGY_LOST_THRESH   0x112 /* Energy Lost Threshold */
#define	REG_FAST_STRONGER_SIGNAL_THRESH   0x113 /* Stronger Signal Threshold */
#define	REG_FAST_LOW_POWER_THRESH   0x114 /* Low Power Threshold */
#define	REG_FAST_STRONG_SIGNAL_FREEZE   0x115 /* Strong Signal Freeze */
#define	REG_FAST_FINAL_OVER_RANGE_AND_OPT_GAIN   0x116 /* Final Over Range and Opt Gain */
#define	REG_FAST_ENERGY_DETECT_COUNT   0x117 /* Energy Detect Count */
#define	REG_FAST_AGCLL_UPPER_LIMIT   0x118 /* AGCLL Upper Limit */
#define	REG_FAST_GAIN_LOCK_EXIT_COUNT   0x119 /* Gain Lock Exit Count */
#define	REG_FAST_INITIAL_LMT_GAIN_LIMIT   0x11A /* Initial LMT Gain Limit */
#define	REG_FAST_INCREMENT_TIME   0x11B /* Increment Time */
#define	REG_AGC_INNER_LOW_THRESH   0x120 /* AGC Inner Low Threshold */
#define	REG_LMT_OVERLOAD_COUNTERS   0x121 /* LMT Overload Counters */
#define	REG_ADC_OVERLOAD_COUNTERS   0x122 /* ADC Overload Counters */
#define	REG_GAIN_STP1   0x123 /* Gain Step1 */
#define	REG_GAIN_UPDATE_COUNTER1   0x124 /* Gain Update Counter1 */
#define	REG_GAIN_UPDATE_COUNTER2   0x125 /* Gain Update Counter2 */
#define	REG_DIGITAL_SAT_COUNTER   0x128 /* Digital Sat Counter */
#define	REG_OUTER_POWER_THRESHS   0x129 /* Outer Power Thresholds */
#define	REG_GAIN_STP_2   0x12A /* Gain Step 2 */
#define	REG_EXT_LNA_HIGH_GAIN   0x12C /* Ext LNA High Gain */
#define	REG_EXT_LNA_LOW_GAIN   0x12D /* Ext LNA Low Gain */
#define	REG_GAIN_TABLE_ADDRESS   0x130 /* Gain Table Address */
#define	REG_GAIN_TABLE_WRITE_DATA1   0x131 /* Gain Table Write Data1 */
#define	REG_GAIN_TABLE_WRITE_DATA2   0x132 /* Gain Table Write Data2 */
#define	REG_GAIN_TABLE_WRITE_DATA3   0x133 /* Gain Table Write Data 3 */
#define	REG_GAIN_TABLE_READ_DATA1   0x134 /* Gain Table Read Data 1 */
#define	REG_GAIN_TABLE_READ_DATA2   0x135 /* Gain Table Read Data 2 */
#define	REG_GAIN_TABLE_READ_DATA3   0x136 /* Gain Table Read Data 3 */
#define	REG_GAIN_TABLE_CONFIG   0x137 /* Gain Table Config */
#define	REG_GM_SUB_TABLE_ADDRESS   0x138 /* Gm Sub Table Address */
#define	REG_GM_SUB_TABLE_GAIN_WRITE   0x139 /* Gm Sub Table Gain Word Write */
#define	REG_GM_SUB_TABLE_BIAS_WRITE   0x13A /* Gm Sub Table Bias Word Write */
#define	REG_GM_SUB_TABLE_CTRL_WRITE   0x13B /* Gm Sub Table Control Word Write */
#define	REG_GM_SUB_TABLE_GAIN_READ   0x13C /* Gm Sub Table Gain Word Read */
#define	REG_GM_SUB_TABLE_BIAS_READ   0x13D /* Gm Sub Table Bias Word Read */
#define	REG_GM_SUB_TABLE_CTRL_READ   0x13E /* Gm Sub Table Control Word Read */
#define	REG_GM_SUB_TABLE_CONFIG   0x13F /* Gm Sub Table Config */
#define	REG_WORD_ADDRESS   0x140 /* Word Address */
#define	REG_GAIN_DIFF_WORDERROR_WRITE   0x141 /* Gain Diff Word/Error Write */
#define	REG_GAIN_ERROR_READ   0x142 /* Gain Error Read */
#define	REG_CONFIG   0x143 /* Config */
#define	REG_LNA_GAIN_DIFF_READ_BACK   0x144 /* LNA Gain Diff Read Back */
#define	REG_MAX_MIXER_CALIBRATION_GAIN_INDEX   0x145 /* Max Mixer Calibration Gain Index */
#define	REG_TEMP_GAIN_COEF   0x146 /* Temp Gain Coefficient */
#define	REG_SETTLE_TIME   0x147 /* Settle Time */
#define	REG_MEASURE_DURATION   0x148 /* Measure Duration */
#define	REG_CAL_TEMP_SENSOR_WORD   0x149 /* Cal Temp sensor word */
#define	REG_MEASURE_DURATION_01   0x150 /* Measure Duration 0&1 */
#define	REG_MEASURE_DURATION_23   0x151 /* Measure Duration 2&3 */
#define	REG_RSSI_WEIGHT_0   0x152 /* RSSI Weight 0 */
#define	REG_RSSI_WEIGHT_1   0x153 /* RSSI Weight 1 */
#define	REG_RSSI_WEIGHT_2   0x154 /* RSSI Weight 2 */
#define	REG_RSSI_WEIGHT_3   0x155 /* RSSI Weight 3 */
#define	REG_RSSI_DELAY   0x156 /* RSSI delay */
#define	REG_RSSI_WAIT_TIME   0x157 /* RSSI wait time */
#define	REG_RSSI_CONFIG   0x158 /* RSSI Config */
#define	REG_ADC_MEASURE_DURATION_01   0x159 /* ADC Measure Duration 0&1 */
#define	REG_ADC_WEIGHT_0   0x15A /* ADC Weight 0 */
#define	REG_ADC_WEIGHT_1   0x15B /* ADC Weight 1 */
#define	REG_DEC_POWER_MEASURE_DURATION_0   0x15C /* Dec Power Measure Duration 0 */
#define	REG_LNA_GAIN   0x15D /* LNA Gain */
#define	REG_CH1_ADC_POWER   0x160 /* CH1 ADC Power */
#define	REG_CH1_RX_FILTER_POWER   0x161 /* CH1 Rx filter Power */
#define	REG_CH2_ADC_POWER   0x162 /* CH2 ADC Power */
#define	REG_CH2_RX_FILTER_POWER   0x163 /* CH2 Rx filter Power */
#define	REG_RX_QUAD_CAL_LEVEL   0x168 /* Rx Quad Cal Level */
#define	REG_CALIBRATION_CONFIG_1   0x169 /* Calibration Config 1 */
#define	REG_CALIBRATION_CONFIG_2   0x16A /* Calibration config2 */
#define	REG_CALIBRATION_CONFIG_3   0x16B /* Calibration config3 */
#define	REG_CALIB_COUNT   0x16C /* Calib count */
#define	REG_SETTLE_COUNT   0x16D /* Settle count */
#define	REG_RX_QUAD_GAIN1   0x16E /* Rx Quad gain1 */
#define	REG_RX_QUAD_GAIN2   0x16F /* Rx Quad gain2 */
#define	REG_RX1_INPUT_A_PHASE_CORR   0x170 /* Rx1 Input A Phase Corr */
#define	REG_RX1_INPUT_A_GAIN_CORR   0x171 /* Rx1 Input A Gain Corr */
#define	REG_RX2_INPUT_A_PHASE_CORR   0x172 /* Rx2 Input A Phase Corr */
#define	REG_RX2_INPUT_A_GAIN_CORR   0x173 /* Rx2 Input A Gain Corr */
#define	REG_RX1_INPUT_A_Q_OFFSET   0x174 /* Rx1 Input A Q" Offset */
#define	REG_RX1_INPUT_A_OFFSETS   0x175 /* Rx1 Input A Offsets */
#define	REG_INPUT_A_OFFSETS_1   0x176 /* Input A Offsets 1 */
#define	REG_RX2_INPUT_A_OFFSETS   0x177 /* Rx2 Input A Offsets */
#define	REG_RX2_INPUT_A_I_OFFSET   0x178 /* Rx2 Input A "I" Offset */
#define	REG_RX1_INPUT_BC_PHASE_CORR   0x179 /* Rx1 Input B&C Phase Corr */
#define	REG_RX1_INPUT_BC_GAIN_CORR   0x17A /* Rx1 Input B&C Gain Corr */
#define	REG_RX2_INPUT_BC_PHASE_CORR   0x17B /* Rx2 Input B&C Phase Corr */
#define	REG_RX2_INPUT_BC_GAIN_CORR   0x17C /* Rx2 Input B&C Gain Corr */
#define	REG_RX1_INPUT_BC_Q_OFFSET   0x17D /* Rx1 Input B&C "Q" Offset */
#define	REG_RX1_INPUT_BC_OFFSETS   0x17E /* Rx1 Input B&C Offsets */
#define	REG_INPUT_BC_OFFSETS_1   0x17F /* Input B&C Offsets 1 */
#define	REG_RX2_INPUT_BC_OFFSETS   0x180 /* Rx2 Input B&C Offsets */
#define	REG_RX2_INPUT_BC_I_OFFSET   0x181 /* Rx2 Input B&C "I" Offset */
#define	REG_FORCE_BITS   0x182 /* Force Bits */
#define	REG_WAIT_COUNT   0x185 /* Wait Count */
#define	REG_RF_DC_OFFSET_COUNT   0x186 /* RF DC Offset Count */
#define	REG_RF_DC_OFFSET_CONFIG_1   0x187 /* RF DC Offset Config1 */
#define	REG_RF_DC_OFFSET_ATTEN   0x188 /* RF DC Offset Attenuation */
#define	REG_INVERT_BITS   0x189 /* Invert Bits */
#define	REG_DC_OFFSET_CONFIG2   0x18B /* DC Offset Config2 */
#define	REG_RF_CAL_GAIN_INDEX   0x18C /* RF Cal Gain Index */
#define	REG_SOI_THRESH   0x18D /* SOI Threshold */
#define	REG_BB_DC_OFFSET_SHIFT   0x190 /* BB DC Offset Shift */
#define	REG_BB_DC_OFFSET_FAST_SETTLE_SHIFT   0x191 /* BB DC Offset Fast Settle Shift */
#define	REG_BB_FAST_SETTLE_DUR   0x192 /* BB Fast Settle Dur */
#define	REG_BB_DC_OFFSET_COUNT   0x193 /* BB DC Offset Count */
#define	REG_BB_DC_OFFSET_ATTEN   0x194 /* BB DC Offset Attenuation */
#define	REG_RX1_BB_DC_WORD_I_MSB   0x19A /* RX1 BB DC word I MSB */
#define	REG_RX1_BB_DC_WORD_I_LSB   0x19B /* RX1 BB DC word I LSB */
#define	REG_RX1_BB_DC_WORD_Q_MSB   0x19C /* RX1 BB DC word Q MSB */
#define	REG_RX1_BB_DC_WORD_Q_LSB   0x19D /* RX1 BB DC word Q LSB */
#define	REG_RX2_BB_DC_WORD_I_MSB   0x19E /* RX2 BB DC word I MSB */
#define	REG_RX2_BB_DC_WORD_I_LSB   0x19F /* RX2 BB DC word I LSB */
#define	REG_RX2_BB_DC_WORD_Q_MSB   0x1A0 /* RX2 BB DC word Q MSB */
#define	REG_RX2_BB_DC_WORD_Q_LSB   0x1A1 /* RX2 BB DC word Q LSB */
#define	REG_BB_TRACK_CORR_WORD_I_MSB   0x1A2 /* BB Track corr word I MSB */
#define	REG_BB_TRACK_CORR_WORD_I_LSB   0x1A3 /* BB Track corr word I LSB */
#define	REG_BB_TRACK_CORR_WORD_Q_MSB   0x1A4 /* BB Track corr word Q MSB */
#define	REG_BB_TRACK_CORR_WORD_Q_LSB   0x1A5 /* BB Track corr word Q LSB */
#define	REG_RX1_RSSI_SYMBOL   0x1A7 /* Rx1 RSSI Symbol */
#define	REG_RX1_RSSI_PREAMBLE   0x1A8 /* Rx1 RSSI preamble */
#define	REG_RX2_RSSI_SYMBOL   0x1A9 /* Rx2 RSSI symbol */
#define	REG_RX2_RSSI_PREAMBLE   0x1AA /* Rx2 RSSI preamble */
#define	REG_SYMBOL_LSB   0x1AB /* Symbol LSB */
#define	REG_PREAMBLE_LSB   0x1AC /* Preamble LSB */
#define	REG_RX_PATH_GAIN_MSB   0x1AD /* Rx Path Gain */
#define	REG_RX_PATH_GAIN_LSB   0x1AE /* Rx Path Gain */
#define	REG_RX_DIFF_LNA_FORCE   0x1B0 /* Rx Diff LNA Force */
#define	REG_RX_LNA_BIAS_COARSE   0x1B1 /* Rx LNA Bias Coarse */
#define	REG_RX_LNA_BIAS_FINE_0   0x1B2 /* Rx LNA Bias Fine 0 */
#define	REG_RX_LNA_BIAS_FINE_1   0x1B3 /* Rx LNA Bias Fine 1 */
#define	REG_RX_MIX_GM_CONFIG   0x1C0 /* Rx Mix Gm Config */
#define	REG_RX1_MIX_GM_FORCE   0x1C1 /* Rx1 Mix Gm Force */
#define	REG_RX1_MIX_GM_BIAS_FORCE   0x1C2 /* Rx1 Mix Gm Bias (Force) */
#define	REG_RX2_MIX_GM_FORCE   0x1C3 /* Rx2 Mix Gm Force */
#define	REG_RX2_MIX_GM_BIAS_FORCE   0x1C4 /* Rx2 Mix Gm Bias (Force) */
#define	REG_INPUT_A_MSBS   0x1C8 /* Input A MSBs */
#define	REG_INPUT_A_RX1_I   0x1C9 /* Input A RX1 I */
#define	REG_INPUT_A_RX1_Q   0x1CA /* Input A RX1 Q */
#define	REG_INPUT_A_RX2_I   0x1CB /* Input A RX2 I */
#define	REG_INPUT_A_RX2_Q   0x1CC /* Input A RX2 Q */
#define	REG_INPUTS_BC_RX1_I   0x1CD /* Inputs B&C RX1 I */
#define	REG_BAND1_RX1_Q   0x1CE /* Band1 RX1 Q */
#define	REG_INPUTS_BC_RX2_I   0x1CF /* Inputs B&C RX2 I */
#define	REG_INPUTS_BC_RX2_Q   0x1D0 /* Inputs B&C RX2 Q */
#define	REG_INPUTS_BC_MSBS   0x1D1 /* Inputs B&C MSBs */
#define	REG_FORCE_OS_DAC   0x1D2 /* Force OS DAC */
#define	REG_RX_MIX_LO_CM   0x1D5 /* Rx Mix LO CM */
#define	REG_RX_CGB_SEG_ENABLE   0x1D6 /* Rx CGB Seg Enable */
#define	REG_RX_MIX_INPUTBIAS   0x1D7 /* Rx Mix Input/Bias */
#define	REG_RX_TIA_CONFIG   0x1DB /* Rx TIA Config */
#define	REG_TIA1_C_LSB   0x1DC /* TIA1 C LSB */
#define	REG_TIA1_C_MSB   0x1DD /* TIA1 C MSB */
#define	REG_TIA2_C_LSB   0x1DE /* TIA2 C LSB */
#define	REG_TIA2_C_MSB   0x1DF /* TIA2 C MSB */
#define	REG_RX1_BBF_R1A   0x1E0 /* Rx1 BBF R1A */
#define	REG_RX2_BBF_R1A   0x1E1 /* Rx2 BBF R1A */
#define	REG_RX1_TUNE_CTRL   0x1E2 /* Rx1 Tune Control */
#define	REG_RX2_TUNE_CTRL   0x1E3 /* Rx2 Tune Control */
#define	REG_RX1_BBF_R5   0x1E4 /* Rx1 BBF R5 */
#define	REG_RX2_BBF_R5   0x1E5 /* Rx2 BBF R5 */
#define	REG_RX_BBF_R2346   0x1E6 /* Rx BBF R2346 */
#define	REG_RX_BBF_C1_MSB   0x1E7 /* Rx BBF C1 MSB */
#define	REG_RX_BBF_C1_LSB   0x1E8 /* Rx BBF C1 LSB */
#define	REG_RX_BBF_C2_MSB   0x1E9 /* Rx BBF C2 MSB */
#define	REG_RX_BBF_C2_LSB   0x1EA /* Rx BBF C2 LSB */
#define	REG_RX_BBF_C3_MSB   0x1EB /* Rx BBF C3 MSB */
#define	REG_RX_BBF_C3_LSB   0x1EC /* Rx BBF C3 LSB */
#define	REG_RX_BBF_CC1_CTR   0x1ED /* Rx BBF CC1 Ctr */
#define	REG_RX_BBF_POW_RZ_BYTE0   0x1EE /* Rx BBF Pow Rz Byte0 */
#define	REG_RX_BBF_CC2_CTR   0x1EF /* Rx BBF CC2 Ctr */
#define	REG_RX_BBF_POW_RZ_BYTE1   0x1F0 /* Rx BBF Pow Rz Byte1 */
#define	REG_RX_BBF_CC3_CTR   0x1F1 /* Rx BBF CC3 Ctr */
#define	REG_RX_BBF_R5_TUNE   0x1F2 /* Rx BBF R5 Tune */
#define	REG_RX_BBF_TUNE   0x1F3 /* Rx BBF Tune */
#define	REG_RX1_BBF_MAN_GAIN   0x1F4 /* Rx1 BBF Man Gain */
#define	REG_RX2_BBF_MAN_GAIN   0x1F5 /* Rx2 BBF Man Gain */
#define	REG_RX_BBF_TUNE_DIVIDE   0x1F8 /* RX BBF Tune Divide */
#define	REG_RX_BBF_TUNE_CONFIG   0x1F9 /* RX BBF Tune Config */
#define	REG_POLE_GAIN   0x1FA /* Pole gain */
#define	REG_RX_BBBW_MHZ   0x1FB /* Rx BBBW MHz */
#define	REG_RX_BBBW_KHZ   0x1FC /* Rx BBBW kHz */
#define	REG_FB_DAC_CLK_DELAY1   0x201 /* FB DAC Clk Delay1 */
#define	REG_FB_DAC_CLK_DELAY2   0x202 /* FB DAC Clk Delay2 */
#define	REG_FLASH_SAMPLE_CLK_DELAY_3P   0x203 /* Flash Sample Clk Delay 3p */
#define	REG_FLASH_SAMPLE_CLK_DELAY_3N   0x204 /* Flash Sample Clk Delay 3n */
#define	REG_TEST_MUX_2I   0x205 /* Test MUX 2i */
#define	REG_TEST_MUX_2Q   0x206 /* Test MUX 2q */
#define	REG_INTEGRATOR_1_RESISTANCE   0x207 /* Integrator 1 Resistance */
#define	REG_INTEGRATOR_1_CAPACITANCE   0x208 /* Integrator 1 Capacitance */
#define	REG_INTEGRATOR_23_RESISTANCE   0x209 /* Integrator 23 Resistance */
#define	REG_INTEGRATOR_2_RESISTANCE   0x20A /* Integrator 2 Resistance */
#define	REG_INTEGRATOR_2_CAPACITANCE   0x20B /* Integrator 2 Capacitance */
#define	REG_INTEGRATOR_3_RESISTANCE   0x20C /* Integrator 3 Resistance */
#define	REG_INTEGRATOR_3_CAPACITANCE   0x20D /* Integrator 3 Capacitance */
#define	REG_INTEGRATOR_AMP_CC   0x20E /* Integrator Amp Cc */
#define	REG_INT_1_FB_DAC_NMOS_CURRENT_SOURCE   0x20F /* Int 1 FB DAC NMOS Current Source */
#define	REG_INT_1_FB_DAC_NMOS_CASOADE_BIAS_CURRENT   0x210 /* Int 1 FB DAC NMOS Casoade Bias Current */
#define	REG_INT_1_FB_DAC_PMOS_CURRENT_SOURCE   0x211 /* Int 1 FB DAC PMOS Current Source */
#define	REG_INT_2_FB_DAC_NMOS_CURRENT_SOURCE   0x212 /* Int 2 FB DAC NMOS Current Source */
#define	REG_INT_2_FB_DAC_NMOS_CASCODE_BIAS_CURRENT   0x213 /* Int 2 FB DAC NMOS Cascode Bias Current */
#define	REG_INT_2_FB_DAC_PMOS_CURRENT_SOURCE   0x214 /* Int 2 FB DAC PMOS Current Source */
#define	REG_INT_3_FB_DAC_NMOS_CURRENT_SOURCE   0x215 /* Int 3 FB DAC NMOS Current Source */
#define	REG_INT_3_FB_DAC_NMOS_CASCODE_BIAS_CURRENT   0x216 /* Int 3 FB DAC NMOS Cascode Bias Current */
#define	REG_INT_3_FB_DAC_PMOS_CURRENT_SOURCE   0x217 /* Int 3 FB DAC PMOS Current Source */
#define	REG_FB_DAC_BIAS_CURRENT   0x218 /* FB DAC Bias Current */
#define	REG_INT_1_1ST_STAGE_CURRENT   0x219 /* Int 1 1st Stage Current */
#define	REG_INT_1_1ST_STAGE_CASCODE_CURRENT   0x21A /* Int 1 1st Stage Cascode Current */
#define	REG_INT_1_2ND_STAGE_CURRENT   0x21B /* Int 1 2nd Stage Current */
#define	REG_INTEGRATOR_2_1ST_STAGE_CURRENT   0x21C /* Integrator 2 1st Stage Current */
#define	REG_INT_2_1ST_STAGE_CASCODE_CURRENT   0x21D /* Int 2 1st Stage Cascode Current */
#define	REG_INT_2_2ND_STAGE_CURRENT   0x21E /* Int 2 2nd Stage Current */
#define	REG_INT_3_1ST_STAGE_CURRENT   0x21F /* Int 3 1st Stage Current */
#define	REG_INT_3_1ST_STAGE_CASCODE_CURRENT   0x220 /* Int 3 1st Stage Cascode Current */
#define	REG_INT_3_2ND_STAGE_CURRENT   0x221 /* Int 3 2nd Stage Current */
#define	REG_FLASH_BIAS_CURRENT   0x222 /* Flash Bias Current */
#define	REG_FLASH_LADDER_BIAS   0x223 /* Flash Ladder Bias */
#define	REG_FLASH_LADDER_CASCODE_CURRENT   0x224 /* Flash Ladder Cascode Current */
#define	REG_FLASH_LADDER_BIAS2   0x225 /* Flash Ladder Bias2 */
#define	REG_RESET   0x226 /* Reset */
#define	REG_RX_PFD_CONFIG   0x230 /* RX PFD Config */
#define	REG_RX_INTEGER_BYTE_0   0x231 /* RX Integer Byte 0 */
#define	REG_RX_INTEGER_BYTE_1   0x232 /* RX Integer Byte 1 */
#define	REG_RX_FRACT_BYTE_0   0x233 /* RX Fractional Byte 0 */
#define	REG_RX_FRACT_BYTE_1   0x234 /* RX Fractional Byte 1 */
#define	REG_RX_FRACT_BYTE_2   0x235 /* RX Fractional Byte 2 */
#define	REG_RX_FORCE_ALC   0x236 /* RX Force ALC */
#define	REG_RX_FORCE_VCO_TUNE_0   0x237 /* RX Force VCO Tune 0 */
#define	REG_RX_FORCE_VCO_TUNE_1   0x238 /* RX Force VCO Tune 1 */
#define	REG_RX_ALC_VARACTOR   0x239 /* RX ALC/Varactor */
#define	REG_RX_VCO_OUTPUT   0x23A /* RX VCO Output */
#define	REG_RX_CP_CURRENT   0x23B /* RX CP Current */
#define	REG_RX_CP_OFFSET   0x23C /* RX CP Offset */
#define	REG_RX_CP_CONFIG   0x23D /* RX CP Config */
#define	REG_RX_LOOP_FILTER_1   0x23E /* RX Loop Filter 1 */
#define	REG_RX_LOOP_FILTER_2   0x23F /* RX Loop Filter 2 */
#define	REG_RX_LOOP_FILTER_3   0x240 /* RX Loop Filter 3 */
#define	REG_RX_DITHERCP_CAL   0x241 /* RX Dither/CP Cal */
#define	REG_RX_VCO_BIAS_1   0x242 /* RX VCO Bias 1 */
#define	REG_RX_CAL_STATUS   0x244 /* RX Cal Status */
#define	REG_RX_VCO_CAL_REF   0x245 /* RX VCO Cal Ref */
#define	REG_RX_VCO_PD_OVERRIDES   0x246 /* RX VCO Pd Overrides */
#define	REG_RX_CP_OVERRANGE_VCO_LOCK   0x247 /* RX CP Over Range/VCO Lock */
#define	REG_RX_VCO_LDO   0x248 /* RX VCO LDO */
#define	REG_RX_VCO_CAL   0x249 /* RX VCO Cal */
#define	REG_RX_LOCK_DETECT_CONFIG   0x24A /* RX Lock Detect Config */
#define	REG_RX_CP_LEVEL_DETECT   0x24B /* RX CP Level Detect */
#define	REG_RX_DSM_SETUP_0   0x24C /* RX DSM Setup 0 */
#define	REG_RX_DSM_SETUP_1   0x24D /* RX DSM Setup 1 */
#define	REG_RX_CORRECTION_WORD0   0x24E /* RX Correction Word0 */
#define	REG_RX_CORRECTION_WORD1   0x24F /* RX Correction Word1 */
#define	REG_RX_VCO_VARACTOR_CTRL_0   0x250 /* RX VCO Varactor Control 0 */
#define	REG_RX_VCO_VARACTOR_CTRL_1   0x251 /* RX VCO Varactor Control 1 */
#define	REG_RX_FAST_LOCK_SETUP   0x25A /* Rx Fast Lock Setup */
#define	REG_RX_FAST_LOCK_SETUP_INIT_DELAY   0x25B /* Rx Fast Lock Setup Init Delay */
#define	REG_RX_FAST_LOCK_PROGRAM_ADDR   0x25C /* Rx Fast Lock Program Addr */
#define	REG_RX_FAST_LOCK_PROGRAM_DATA   0x25D /* Rx Fast Lock Program Data */
#define	REG_RX_FAST_LOCK_PROGRAM_READ   0x25E /* Rx Fast Lock Program Read */
#define	REG_RX_FAST_LOCK_PROGRAM_CTRL   0x25F /* Rx Fast Lock Program Control */
#define	REG_RX_LO_GEN_POWER_MODE   0x261 /* Rx LO Gen Power Mode */
#define	REG_TX_PFD_CONFIG   0x270 /* TX PFD Config */
#define	REG_TX_INTEGER_BYTE_0   0x271 /* TX Integer Byte 0 */
#define	REG_TX_INTEGER_BYTE_1   0x272 /* TX Integer Byte 1 */
#define	REG_TX_FRACT_BYTE_0   0x273 /* TX Fractional Byte 0 */
#define	REG_TX_FRACT_BYTE_1   0x274 /* TX Fractional Byte 1 */
#define	REG_TX_FRACT_BYTE_2   0x275 /* TX Fractional Byte 2 */
#define	REG_TX_FORCE_ALC   0x276 /* TX Force ALC */
#define	REG_TX_FORCE_VCO_TUNE_0   0x277 /* TX Force VCO Tune 0 */
#define	REG_TX_FORCE_VCO_TUNE_1   0x278 /* TX Force VCO Tune 1 */
#define	REG_TX_ALCVARACT_OR   0x279 /* TX ALC/Varact or */
#define	REG_TX_VCO_OUTPUT   0x27A /* TX VCO Output */
#define	REG_TX_CP_CURRENT   0x27B /* TX CP Current */
#define	REG_TX_CP_OFFSET   0x27C /* TX CP Offset */
#define	REG_TX_CP_CONFIG   0x27D /* TX CP Config */
#define	REG_TX_LOOP_FILTER_1   0x27E /* TX Loop Filter 1 */
#define	REG_TX_LOOP_FILTER_2   0x27F /* TX Loop Filter 2 */
#define	REG_TX_LOOP_FILTER_3   0x280 /* TX Loop Filter 3 */
#define	REG_TX_DITHERCP_CAL   0x281 /* TX Dither/CP Cal */
#define	REG_TX_VCO_BIAS_1   0x282 /* TX VCO Bias 1 */
#define	REG_TX_VCO_BIAS_2   0x283 /* TX VCO Bias 2 */
#define	REG_TX_CAL_STATUS   0x284 /* TX Cal Status */
#define	REG_TX_VCO_CAL_REF   0x285 /* TX VCO Cal Ref */
#define	REG_TX_VCO_PD_OVERRIDES   0x286 /* TX VCO Pd Overrides */
#define	REG_TX_CP_OVERRANGE_VCO_LOCK   0x287 /* TX CP Over Range/VCO Lock */
#define	REG_TX_VCO_LDO   0x288 /* TX VCO LDO */
#define	REG_TX_VCO_CAL   0x289 /* TX VCO Cal */
#define	REG_TX_LOCK_DETECT_CONFIG   0x28A /* TX Lock Detect Config */
#define	REG_TX_CP_LEVEL_DETECT   0x28B /* TX CP Level Detect */
#define	REG_TX_DSM_SETUP_0   0x28C /* TX DSM Setup 0 */
#define	REG_TX_DSM_SETUP_1   0x28D /* TX DSM Setup 1 */
#define	REG_TX_CORRECTION_WORD0   0x28E /* TX Correction Word0 */
#define	REG_TX_CORRECTION_WORD1   0x28F /* TX Correction Word1 */
#define	REG_TX_VCO_VARACTOR_CTRL_0   0x290 /* TX VCO Varactor Control 0 */
#define	REG_TX_VCO_VARACTOR_CTRL_1   0x291 /* TX VCO Varactor Control 1 */
#define	REG_DCXO_COARSE_TUNE   0x292 /* DCXO Coarse Tune */
#define	REG_DCXO_FINE_TUNE_HIGH   0x293 /* DCXO Fine Tune2 */
#define	REG_DCXO_FINE_TUNE_LOW   0x294 /* DCXO Fine Tune1 */
#define	REG_DCXO_CONFIG   0x295 /* DCXO Config */
#define	REG_DCXO_TEMPCO_WRITE   0x296 /* DCXO Tempco Write */
#define	REG_DCXO_TEMPCO_READ   0x297 /* DCXO Tempco Read */
#define	REG_DCXO_TEMPCO_ADDR   0x298 /* DCXO Tempco Addr */
#define	REG_DELTA_T_READ   0x299 /* Delta T Read */
#define	REG_TX_FAST_LOCK_SETUP   0x29A /* Tx Fast Lock Setup */
#define	REG_TX_FAST_LOCK_SETUP_INIT_DELAY   0x29B /* Tx Fast Lock Setup Init Delay */
#define	REG_TX_FAST_LOCK_PROGRAM_ADDR   0x29C /* Tx Fast Lock Program Addr */
#define	REG_TX_FAST_LOCK_PROGRAM_DATA   0x29D /* Tx Fast Lock Program Data */
#define	REG_TX_FAST_LOCK_PROGRAM_READ   0x29E /* Tx Fast Lock Program Read */
#define	REG_TX_FAST_LOCK_PROGRAM_CTRL   0x29F /* Tx Fast Lock Program Ctrl */
#define	REG_TX_LO_GEN_POWER_MODE   0x2A1 /* Tx LO Gen Power Mode */
#define	REG_BANDGAP_CONFIG0   0x2A6 /* Bandgap Config0 */
#define	REG_BANDGAP_CONFIG1   0x2A8 /* Bandgap Config1 */
#define	REG_REF_DIVIDE_CONFIG_1   0x2AB /* Ref Divide Config 1 */
#define	REG_REF_DIVIDE_CONFIG_2   0x2AC /* Ref Divide Config 2 */
#define	REG_GAIN_RX1   0x2B0 /* Gain Rx1 */
#define	REG_LPF_GAIN_RX1   0x2B1 /* LPF Gain Rx1 */
#define	REG_DIG_GAIN_RX1   0x2B2 /* Dig gain Rx1 */
#define	REG_FAST_ATTACK_STATE   0x2B3 /* Fast Attack State */
#define	REG_SLOW_LOOP_STATE   0x2B4 /* Slow Loop State */
#define	REG_GAIN_RX2   0x2B5 /* Gain Rx2 */
#define	REG_LPF_GAIN_RX2   0x2B6 /* LPF Gain Rx2 */
#define	REG_DIG_GAIN_RX2   0x2B7 /* Dig Gain Rx2 */
#define	REG_OVRG_SIGS_RX1   0x2B8 /* Ovrg Sigs Rx1 */
#define	REG_OVRG_SIGS_RX2   0x2B9 /* Ovrg Sigs Rx2 */
#define	REG_CTRL   0x3DF /* Control */
#define	REG_BIST_CONFIG   0x3F4 /* BIST Config */
#define	REG_OBSERVE_CONFIG   0x3F5 /* Observe Config */
#define	REG_BIST_AND_DATA_PORT_TEST_CONFIG   0x3F6 /* BIST and Data Port Test Config */
#define	REG_DAC_TEST_0   0x3FC /* DAC Test 0 */
#define	REG_DAC_TEST_1   0x3FD /* DAC Test 1 */
#define	REG_DAC_TEST_2   0x3FE /* DAC Test 2 */
#define	SOFT_RESET   (1 << 7) /* Soft Reset */
#define	WIRE3_SPI   (1 << 6) /* 3-Wire SPI */
#define	LSB_FIRST   (1 << 5) /* LSB First */
#define	_LSB_FIRST   (1 << 2) /* LSB First */
#define	_WIRE3_SPI   (1 << 1) /* 3-Wire SPI */
#define	_SOFT_RESET   (1 << 0) /* Soft reset */
#define	TX2_MONITOR_ENABLE   (1 << 6) /* Tx2 Monitor Enable */
#define	TX1_MONITOR_ENABLE   (1 << 5) /* Tx1 Monitor Enable */
#define	MCS_RF_ENABLE   (1 << 3) /* MCS RF Enable */
#define	MCS_BBPLL_ENABLE   (1 << 2) /* MCS BBPLL enable */
#define	MCS_DIGITAL_CLK_ENABLE   (1 << 1) /* MCS Digital CLK Enable */
#define	MCS_BB_ENABLE   (1 << 0) /* MCS BB Enable */
#define	THB2_EN   (1 << 3) /* THB2 Enable */
#define	THB1_EN   (1 << 2) /* THB1 Enable */
#define	TX_CHANNEL_ENABLE(x)
#define	THB3_ENABLE_INTERP(x)
#define	TX_FIR_ENABLE_INTERPOLATION(x)
#define	TX_1   1
#define	TX_2   2
#define	TX_ENABLE   1
#define	TX_DISABLE   0
#define	RHB2_EN   (1 << 3) /* RHB2 Enable */
#define	RHB1_EN   (1 << 2) /* RHB1 Enable */
#define	RX_CHANNEL_ENABLE(x)
#define	DEC3_ENABLE_DECIMATION(x)
#define	RX_FIR_ENABLE_DECIMATION(x)
#define	RX_1   1
#define	RX_2   2
#define	RX_ENABLE   1
#define	RX_DISABLE   0
#define	TX_OUTPUT   (1 << 6) /* TX Output */
#define	RX_INPUT(x)
#define	TX_VCO_DIVIDER(x)
#define	RX_VCO_DIVIDER(x)
#define	DATA_CLK_DELAY(x)
#define	RX_DATA_DELAY(x)
#define	FB_CLK_DELAY(x)
#define	TX_DATA_DELAY(x)
#define	XO_BYPASS   (1 << 4) /* XO Bypass */
#define	DIGITAL_POWER_UP   (1 << 2) /* Digital Power Up */
#define	CLOCK_ENABLE_DFLT   (1 << 1) /* Set to 1 */
#define	BBPLL_ENABLE   (1 << 0) /* BBPLL Enable */
#define	CLKOUT_ENABLE   (1 << 4) /* CLKOUT Enable */
#define	DAC_CLK_DIV2   (1 << 3) /* DAC Clk div2 */
#define	CLKOUT_SELECT(x)
#define	BBPLL_DIVIDER(x)
#define	START_TEMP_READING   (1 << 0) /* Start Temp Reading */
#define	TEMP_SENSE_PERIODIC_ENABLE   (1 << 0) /* Temp Sense Periodic Enable */
#define	MEASUREMENT_TIME_INTERVAL(x)
#define	TEMP_SENSOR_DECIMATION(x)
#define	PP_TX_SWAP_IQ   (1 << 7) /* PP Tx Swap IQ */
#define	PP_RX_SWAP_IQ   (1 << 6) /* PP Rx Swap IQ */
#define	TX_CHANNEL_SWAP   (1 << 5) /* Tx Channel swap */
#define	RX_CHANNEL_SWAP   (1 << 4) /* Rx Channel swap */
#define	RX_FRAME_PULSE_MODE   (1 << 3) /* Rx Frame Pulse Mode */
#define	R2T2_TIMING   (1 << 2) /* 2R2T Timing */
#define	INVERT_DATA_BUS   (1 << 1) /* Invert data bus */
#define	INVERT_DATA_CLK   (1 << 0) /* Invert DATA CLK */
#define	FDD_ALT_WORD_ORDER   (1 << 7) /* FDD Alt Word Order */
#define	INVERT_RX1   (1 << 6) /* Invert Rx1 */
#define	INVERT_RX2   (1 << 5) /* Invert Rx2 */
#define	INVERT_TX1   (1 << 4) /* Invert Tx1 */
#define	INVERT_TX2   (1 << 3) /* Invert Tx2 */
#define	INVERT_RX_FRAME   (1 << 2) /* Invert Rx Frame */
#define	DELAY_RX_DATA(x)
#define	FDD_RX_RATE_2TX_RATE   (1 << 7) /* FDD Rx Rate = 2*Tx Rate */
#define	SWAP_PORTS   (1 << 6) /* Swap Ports */
#define	SINGLE_DATA_RATE   (1 << 5) /* Single Data Rate */
#define	LVDS_MODE   (1 << 4) /* LVDS Mode */
#define	HALF_DUPLEX_MODE   (1 << 3) /* Half Duplex Mode */
#define	SINGLE_PORT_MODE   (1 << 2) /* Single Port Mode */
#define	FULL_PORT   (1 << 1) /* Full Port */
#define	FULL_DUPLEX_SWAP_BITS   (1 << 0) /* Full Duplex Swap Bits */
#define	FDD_MODE   (1 << 0) /* FDD Mode */
#define	ENABLE_RX_DATA_PORT_FOR_CAL   (1 << 7) /* Enable Rx Data Port for Cal */
#define	FORCE_RX_ON   (1 << 6) /* Force Rx On */
#define	FORCE_TX_ON   (1 << 5) /* Force Tx On */
#define	ENABLE_ENSM_PIN_CTRL   (1 << 4) /* Enable ENSM Pin Control */
#define	LEVEL_MODE   (1 << 3) /* Level Mode */
#define	FORCE_ALERT_STATE   (1 << 2) /* Force Alert State */
#define	AUTO_GAIN_LOCK   (1 << 1) /* Auto Gain Lock */
#define	TO_ALERT   (1 << 0) /* To Alert */
#define	FDD_EXTERNAL_CTRL_ENABLE   (1 << 7) /* FDD External Control Enable */
#define	POWER_DOWN_RX_SYNTH   (1 << 6) /* Power Down Rx Synth */
#define	POWER_DOWN_TX_SYNTH   (1 << 5) /* Power Down Tx Synth */
#define	TXNRX_SPI_CTRL   (1 << 4) /* TXNRX SPI Control */
#define	SYNTH_ENABLE_PIN_CTRL_MODE   (1 << 3) /* Synth Enable Pin Control Mode */
#define	DUAL_SYNTH_MODE   (1 << 2) /* Dual Synth Mode */
#define	RX_SYNTH_READY_MASK   (1 << 1) /* Rx Synth Ready Mask */
#define	TX_SYNTH_READY_MASK   (1 << 0) /* Tx Synth Ready Mask */
#define	RX_BB_TUNE_CAL   (1 << 7) /* Rx BB Tune */
#define	TX_BB_TUNE_CAL   (1 << 6) /* Tx BB Tune */
#define	RX_QUAD_CAL   (1 << 5) /* Rx Quad Cal */
#define	TX_QUAD_CAL   (1 << 4) /* Tx Quad Cal */
#define	RX_GAIN_STEP_CAL   (1 << 3) /* Rx Gain Step Cal */
#define	TXMON_CAL   (1 << 2)
#define	RFDC_CAL   (1 << 1) /* DC Cal RF Start */
#define	BBDC_CAL   (1 << 0) /* DC cal BB Start */
#define	CALIBRATION_SEQUENCE_STATE(x)
#define	ENSM_STATE(x)
#define	ENSM_STATE_SLEEP_WAIT   0x0
#define	ENSM_STATE_ALERT   0x5
#define	ENSM_STATE_TX   0x6
#define	ENSM_STATE_TX_FLUSH   0x7
#define	ENSM_STATE_RX   0x8
#define	ENSM_STATE_RX_FLUSH   0x9
#define	ENSM_STATE_FDD   0xA
#define	ENSM_STATE_FDD_FLUSH   0xB
#define	ENSM_STATE_INVALID   0xFF
#define	ENSM_STATE_SLEEP   0x80
#define	AUXDAC_2_WORD_MSB(x)
#define	AUXDAC_1_WORD(x)
#define	COMP_CTRL_1   (1 << 5) /* Comp Ctrl 1 */
#define	AUXDAC1_STP_FACTOR   (1 << 4) /* AuxDAC1 Step Factor */
#define	AUXDAC_1_VREF(x)
#define	AUXDAC_1_WORD_LSB(x)
#define	COMP_CTRL_2   (1 << 5) /* Comp Ctrl 2 */
#define	AUXDAC2_STP_FACTOR   (1 << 4) /* AuxDAC2 Step Factor */
#define	AUXDAC_2_VREF(x)
#define	AUXDAC_2_WORD_LSB(x)
#define	AUXADC_CLOCK_DIVIDER(x)
#define	AUXADC_POWER_DOWN   (1 << 0) /* AuxADC Power Down */
#define	AUX_ADC_DECIMATION(x)
#define	AUXADC_WORD_LSB(x)
#define	GPO_ENABLE_AUTO_RX(x)
#define	GPO_ENABLE_AUTO_TX(x)
#define	INVERT_BYPASSED_LNA_POLARITY   (1 << 6) /* Invert Bypassed LNA Polarity */
#define	AGC_ATTACK_DELAY(x)
#define	AUXDAC_MANUAL_BAR(x)
#define	AUXDAC_AUTO_TX_BAR(x)
#define	AUXDAC_AUTO_RX_BAR(x)
#define	AUXDAC_INIT_BAR(x)
#define	AUXDAC_MANUAL_SELECT   (1 << 7) /* AuxDAC Manual Select */
#define	EXTERNAL_LNA2_CTRL   (1 << 6) /* External LNA2 control */
#define	EXTERNAL_LNA1_CTRL   (1 << 5) /* External LNA1 control */
#define	GPO_MANUAL_SELECT   (1 << 4) /* GPO manual select */
#define	OPEN(x)
#define	GPO_MANUAL_CTRL(x)
#define	GPO_INIT_STATE(x)
#define	EN_CTRL7   (1 << 7) /* En ctrl7 */
#define	EN_CTRL6   (1 << 6) /* En ctrl6 */
#define	EN_CTRL5   (1 << 5) /* En ctrl5 */
#define	EN_CTRL4   (1 << 4) /* En ctrl4 */
#define	EN_CTRL3   (1 << 3) /* En ctrl3 */
#define	EN_CTRL2   (1 << 2) /* En ctrl2 */
#define	EN_CTRL1   (1 << 1) /* En ctrl1 */
#define	EN_CTRL0   (1 << 0) /* En ctrl0 */
#define	PRODUCT_ID_MASK   0xF8
#define	PRODUCT_ID_9361   0x08
#define	REV_MASK   0x07
#define	REFERENCE_CLOCK_CYCLES_PER_US(x)
#define	CLK_OUT_DRIVE   (1 << 7) /* CLK Out Drive */
#define	DATACLK_DRIVE   (1 << 6) /* DATACLK drive */
#define	DATA_PORT_DRIVE   (1 << 2) /* Data Port Drive */
#define	DATACLK_SLEW(x)
#define	DATA_PORT_SLEW(x)
#define	RX_ON_CHIP_TERM   (1 << 5) /* Rx On Chip Term */
#define	LVDS_BYPASS_BIAS_R   (1 << 4) /* Bypass Bias R */
#define	LVDS_TX_LO_VCM   (1 << 3) /* LVDS Tx LO VCM */
#define	CLK_OUT_SLEW(x)
#define	LVDS_BIAS(x)
#define	INIT_BB_FO_CAL   (1 << 2) /* Init BB FO CAL */
#define	BBPLL_RESET_BAR   (1 << 0) /* BBPLL Reset Bar */
#define	REF_FREQ_SCALER(x)
#define	CHARGE_PUMP_CURRENT(x)
#define	MCS_REFCLK_SCALE_EN   (1 << 7) /* MCS refclk Scale En */
#define	C1_WORD(x)
#define	R1_WORD(x)
#define	R2_WORD   (1 << 7) /* R2 Word<0> */
#define	C2_WORD(x)
#define	C1_WORD_LSB(x)
#define	BYPASS_C3   (1 << 7) /* Bypass C3 */
#define	BYPASS_R2   (1 << 6) /* Bypass R2 */
#define	C3_WORD(x)
#define	R2_WORD_LSB(x)
#define	FREQ_CAL_ENABLE   (1 << 7) /* Freq Cal Enable */
#define	FREQ_CAL_RESET   (1 << 4) /* Freq Cal Reset */
#define	FREQ_CAL_COUNT_LENGTH(x)
#define	CAL_CLOCK_DIV_4   (1 << 4) /* Cal Clock div 4 */
#define	RX_LO_POWER_DOWN   (1 << 4) /* Rx LO Power Down */
#define	RX_SYNTH_VCO_ALC_POWER_DOWN   (1 << 3) /* Rx Synth VCO ALC Power Down */
#define	RX_SYNTH_PTAT_POWER_DOWN   (1 << 2) /* Rx Synth PTAT Power Down */
#define	RX_SYNTH_VCO_POWER_DOWN   (1 << 1) /* Rx Synth VCO Power Down */
#define	RX_SYNTH_VCO_LDO_POWER_DOWN   (1 << 0) /* Rx Synth VCO LDO Power Down */
#define	TX_LO_POWER_DOWN   (1 << 4) /* Tx LO Power Down */
#define	TX_SYNTH_VCO_ALC_POWER_DOWN   (1 << 3) /* Tx Synth VCO ALC Power Down */
#define	TX_SYNTH_PTAT_POWER_DOWN   (1 << 2) /* Tx Synth PTAT Power Down */
#define	TX_SYNTH_VCO_POWER_DOWN   (1 << 1) /* Tx Synth VCO Power Down */
#define	TX_SYNTH_VCO_LDO_POWER_DOWN   (1 << 0) /* Tx Synth VCO LDO Power Down */
#define	RX_OFFSET_DAC_CGIN_POWER_DOWN(x)
#define	RX_LMT_OVERLOAD_POWER_DOWN(x)
#define	RX_MIXER_GM_POWER_DOWN(x)
#define	RX_CGB_POWER_DOWN(x)
#define	RX_BBF_POWER_DOWN(x)
#define	RX_TIA_POWER_DOWN(x)
#define	RX_MIXER_POWER_DOWN(x)
#define	RX_OFFSET_DAC_CGOUT_POWER_DOWN(x)
#define	TX_SECONDARY_FILTER_POWER_DOWN(x)
#define	TX_BBF_POWER_DOWN(x)
#define	TX_DAC_POWER_DOWN(x)
#define	TX_DAC_BIAS_POWER_DOWN(x)
#define	RX_EXT_VCO_BUFFER_POWER_DOWN   (1 << 5) /* Rx Ext VCO Buffer Power Down */
#define	TX_EXT_VCO_BUFFER_POWER_DOWN   (1 << 4) /* Tx Ext VCO Buffer Power Down */
#define	TX_MONITOR_POWER_DOWN(x)
#define	TX_UPCONVERTER_POWER_DOWN(x)
#define	RX_LNA_POWER_DOWN   (1 << 6) /* Rx LNA Power Down */
#define	DCXO_POWER_DOWN   (1 << 1) /* DCXO Power Down */
#define	MASTER_BIAS_POWER_DOWN   (1 << 0) /* Master Bias Power Down */
#define	RX_CALIBRATION_POWER_DOWN(x)
#define	BBPLL_LOCK   (1 << 7) /* BBPLL Lock */
#define	CH_1_INT3   (1 << 6) /* CH 1 INT3 */
#define	CH1_HB3   (1 << 5) /* CH1 HB3 */
#define	CH1_HB2   (1 << 4) /* CH1 HB2 */
#define	CH1_QEC   (1 << 3) /* CH1 QEC */
#define	CH1_HB1   (1 << 2) /* CH1 HB1 */
#define	CH1_TFIR   (1 << 1) /* CH1 TFIR */
#define	CH1_RFIR   (1 << 0) /* CH1 RFIR */
#define	CH2_INT3   (1 << 6) /* CH2 INT3 */
#define	CH2_HB3   (1 << 5) /* CH2 HB3 */
#define	CH2_HB2   (1 << 4) /* CH2 HB2 */
#define	CH2_QEC   (1 << 3) /* CH2 QEC */
#define	CH2_HB1   (1 << 2) /* CH2 HB1 */
#define	CH2_TFIR   (1 << 1) /* CH2 TFIR */
#define	CH2_RFIR   (1 << 0) /* CH2 RFIR */
#define	TX_FIR_GAIN_6DB   (1 << 0) /* Filter Gain */
#define	FIR_START_CLK   (1 << 1) /* Start Tx/Rx Clock */
#define	FIR_WRITE   (1 << 2) /* Write Tx/Rx */
#define	FIR_SELECT(x)
#define	FIR_NUM_TAPS(x)
#define	TX_MON_TRACK   (1 << 5) /* Tx Mon Track */
#define	TX_MON_LOW_GAIN(x)
#define	TX_MON_HIGH_GAIN(x)
#define	TX_LEVEL_THRESH(x)
#define	TX_MON_DELAY_COUNTER(x)
#define	TX_RSSI_2   (1 << 1) /* Tx RSSI 2<0> */
#define	TX_RSSI_1   (1 << 0) /* TX RSSI 1<0> */
#define	TX2_MON_ENABLE   (1 << 7) /* Tx2 Monitor Enable */
#define	TX1_MON_ENABLE   (1 << 5) /* Tx1 Monitor Enable */
#define	ONE_SHOT_MODE   (1 << 6) /* One Shot Mode */
#define	TX_MON_DURATION(x)
#define	TX_MON_1_LO_CM(x)
#define	TX_MON_1_GAIN(x)
#define	TX_MON_2_LO_CM(x)
#define	TX_MON_2_GAIN(x)
#define	TX_1_ATTEN   (1 << 0) /* Tx 1 Atten <8> */
#define	TX_2_ATTEN   (1 << 0) /* Tx 2 Atten <8> */
#define	MASK_CLR_ATTEN_UPDATE   (1 << 6) /* Mask Clr Atten Update */
#define	TX_ATTEN_OFFSET(x)
#define	SEL_TX1_TX2   (1 << 6) /* Sel Tx1 & Ttx2 */
#define	IMMEDIATELY_UPDATE_TPC_ATTEN   (1 << 6) /* Immediately Update TPC Atten */
#define	TX_1_SYMBOL_ATTEN(x)
#define	TX_2_SYMBOL_ATTEN(x)
#define	USE_TX1_PIN_SYMBOL_ATTEN   (1 << 3) /* Use Tx1 Pin & Symbol Atten */
#define	USE_CTRL_IN_FOR_SYMBOL_ATTEN   (1 << 1) /* Use CTRL IN for symbol Atten */
#define	ENABLE_SYMBOL_ATTEN   (1 << 0) /* Enable Symbol Atten */
#define	FORCE_OUT_2_TX2_OFFSET   (1 << 7) /* Force Out 2 Tx2 Offset */
#define	FORCE_OUT_2_TX1_OFFSET   (1 << 6) /* Force Out 2 Tx1 Offset */
#define	FORCE_OUT_2_TX2_PHASE_GAIN   (1 << 5) /* Force Out 2 Tx2 Phase & Gain */
#define	FORCE_OUT_2_TX1_PHASE_GAIN   (1 << 4) /* Force Out 2 Tx1 Phase & Gain */
#define	FORCE_OUT_1_TX2_OFFSET   (1 << 3) /* Force Out 1 Tx2 Offset */
#define	FORCE_OUT_1_TX1_OFFSET   (1 << 2) /* Force Out 1 Tx1 Offset */
#define	FORCE_OUT_1_TX2_PHASE_GAIN   (1 << 1) /* Force Out 1 Tx2 Phase & Gain */
#define	FORCE_OUT_1_TX1_PHASE_GAIN   (1 << 0) /* Force Out 1 Tx1 Phase & Gain */
#define	RX_NCO_FREQ(x)
#define	RX_NCO_PHASE_OFFSET(x)
#define	FREE_RUN_ENABLE   (1 << 7) /* Free Run Enable */
#define	SETTLE_MAIN_ENABLE   (1 << 6) /* Settle Main Enable */
#define	DC_OFFSET_ENABLE   (1 << 5) /* DC Offset Enable */
#define	GAIN_ENABLE   (1 << 4) /* Gain Enable */
#define	PHASE_ENABLE   (1 << 3) /* Phase Enable */
#define	QUAD_CAL_SOFT_RESET   (1 << 2) /* Quad Cal Soft Reset */
#define	M_DECIM(x)
#define	KEXP_TX(x)
#define	KEXP_TX_COMP(x)
#define	KEXP_DC_I(x)
#define	KEXP_DC_Q(x)
#define	INVERT_I_DATA   (1 << 5) /* Invert I data */
#define	INVERT_Q_DATA   (1 << 4) /* Invert Q data */
#define	TX_NCO_FREQ(x)
#define	KEXP_PHASE(x)
#define	KEXP_AMP(x)
#define	TX1_LO_CONV   (1 << 1) /* Tx1 LO Conv */
#define	TX1_SSB_CONV   (1 << 0) /* Tx1 SSB Conv */
#define	TX1_CONVERGENCE_COUNT(x)
#define	TX2_LO_CONV   (1 << 1) /* Tx2 LO Conv */
#define	TX2_SSB_CONV   (1 << 0) /* Tx2 SSB Conv */
#define	TX2_CONVERGENCE_COUNT(x)
#define	RX_FULL_TABLELMT_TABLE_GAIN(x)
#define	GM_STAGE_TIME_CON_OVERRIDE   (1 << 5) /* Gm Stage Time Con Override */
#define	GM_STAGE_MV_HP_POLE   (1 << 4) /* Gm Stage MV HP Pole */
#define	GM_STAGE_LOWER_CM   (1 << 3) /* Gm Stage Lower CM */
#define	BYPASS_BIAS_R   (1 << 0) /* Bypass Bias R */
#define	VBIAS_CTRL(x)
#define	THRESH_ACCUMULATOR(x)
#define	RX_LPF_GAIN(x)
#define	TXDAC_VDS_I(x)
#define	TXDAC_VDS_Q(x)
#define	TXDAC_GN_I(x)
#define	TXDAC_GN_Q(x)
#define	OPAMPA_OUTPUT_BIAS(x)
#define	OPAMPA_RZ(x)
#define	OPAMP_A_CC(x)
#define	OPAMPB_OUTPUT_BIAS(x)
#define	OPAMPB_RZ(x)
#define	OPAMP_B_CC(x)
#define	OVERRIDE_ENABLE   (1 << 7) /* Override enable */
#define	R1(x)
#define	R2(x)
#define	R3(x)
#define	R4(x)
#define	RP(x)
#define	C1(x)
#define	C2(x)
#define	CP(x)
#define	PD_TUNE   (1 << 2) /* PD Tune */
#define	TUNER_RESAMPLE   (1 << 1) /* Tuner Resample */
#define	TUNER_RESAMPLE_PHASE   (1 << 0) /* Tuner Resample Phase */
#define	TUNE_CTRL(x)
#define	TX_BBF_BYPASS_BIAS_R   (1 << 7) /* Bypass Bias R */
#define	R2B_OVR   (1 << 5) /* R2b Ovr */
#define	R2B(x)
#define	BBF1_COMP_I   (1 << 3) /* BBF1 Comp I */
#define	BBF1_COMP_Q   (1 << 2) /* BBF1 Comp Q */
#define	BBF2_COMP_I   (1 << 1) /* BBF2 Comp I */
#define	BBF2_COMP_Q   (1 << 0) /* BBF2 Comp Q */
#define	BIAS(x)
#define	RGM(x)
#define	CC(x)
#define	AMPBIAS(x)
#define	RESISTOR(x)
#define	CAPACITOR(x)
#define	LO_COMMON_MODE(x)
#define	EVALTIME   (1 << 4) /* EvalTime */
#define	TX_BBF_TUNE_DIVIDER   (1 << 0) /* TX BBF Tune Divider<8> */
#define	TUNE_COMP_MASK(x)
#define	TUNER_MODE(x)
#define	WRITE_RX   (1 << 2) /* Write Rx */
#define	START_RX_CLOCK   (1 << 1) /* Start Rx Clock */
#define	NUMBER_OF_TAPS(x)
#define	SELECT_RX_CH(x)
#define	FILTER_GAIN(x)
#define	DEC_PWR_FOR_LOW_PWR   (1 << 7) /* Dec Pwr for Low Pwr */
#define	DEC_PWR_FOR_LOCK_LEVEL   (1 << 6) /* Dec Pwr for Lock Level */
#define	DEC_PWR_FOR_GAIN_LOCK_EXIT   (1 << 5) /* Dec Pwr for Gain Lock Exit */
#define	SLOW_ATTACK_HYBRID_MODE   (1 << 4) /* Slow Attack Hybrid Mode */
#define	RX2_GAIN_CTRL_SETUP(x)
#define	RX1_GAIN_CTRL_SETUP(x)
#define	RX_GAIN_CTL_MASK   0x03
#define	RX2_GAIN_CTRL_SHIFT   2
#define	RX1_GAIN_CTRL_SHIFT   0
#define	RX_GAIN_CTL_MGC   0x00
#define	RX_GAIN_CTL_AGC_FAST_ATK   0x01
#define	RX_GAIN_CTL_AGC_SLOW_ATK   0x02
#define	RX_GAIN_CTL_AGC_SLOW_ATK_HYBD   0x03
#define	AGC_SOFT_RESET   (1 << 7) /* Soft Reset */
#define	AGC_GAIN_UNLOCK_CTRL   (1 << 6) /* Gain Unlock Control */
#define	AGC_USE_FULL_GAIN_TABLE   (1 << 3) /* Use Full Gain Table */
#define	DIG_GAIN_EN   (1 << 2) /* Enable Digital Gain */
#define	MAN_GAIN_CTRL_RX2   (1 << 1) /* Manual Gain Control Rx 2 */
#define	MAN_GAIN_CTRL_RX1   (1 << 0) /* Manual Gain Control Rx 1 */
#define	INCDEC_LMT_GAIN   (1 << 4) /* Inc/Dec LMT Gain */
#define	USE_AGC_FOR_LMTLPF_GAIN   (1 << 3) /* Use AGC for LMT/LPF Gain */
#define	MANUAL_INCR_STEP_SIZE(x)
#define	ADC_OVERRANGE_SAMPLE_SIZE(x)
#define	MAXIMUM_FULL_TABLELMT_TABLE_INDEX(x)
#define	MANUAL_CTRL_IN_DECR_GAIN_STP_SIZE(x)
#define	PEAK_OVERLOAD_WAIT_TIME(x)
#define	DIG_GAIN_STP_SIZE(x)
#define	MAXIMUM_DIGITAL_GAIN(x)
#define	ENABLE_DIG_SAT_OVRG   (1 << 7) /* Enable Dig Sat Ovrg */
#define	AGC_LOCK_LEVEL_FAST_AGC_INNER_HIGH_THRESH_SLOW(x)
#define	LMT_DETECTOR_SETTLING_TIME(x)
#define	DEC_STP_SIZE_FOR_LARGE_LMT_OVERLOAD(x)
#define	ADC_NOISE_CORRECTION_FACTOR(x)
#define	DECREMENT_STP_SIZE_FOR_SMALL_LPF_GAIN_CHANGE(x)
#define	LARGE_LPF_GAIN_STEP(x)
#define	FORCE_PD_RESET_RX2   (1 << 7) /* Force PD Reset Rx2 */
#define	FORCE_PD_RESET_RX1   (1 << 6) /* Force PD Reset Rx1 */
#define	SMALL_LMT_OVERLOAD_THRESH(x)
#define	LARGE_LMT_OVERLOAD_THRESH(x)
#define	POWER_MEAS_IN_STATE_5_MSB   (1 << 7) /* Power Meas in State 5 <3> */
#define	RX1_MANUAL_FULL_TABLE_LMT_TABLE_GAIN_INDEX(x)
#define	RX_FULL_TBL_IDX_MASK   RX1_MANUAL_FULL_TABLE_LMT_TABLE_GAIN_INDEX(~0)
#define	POWER_MEAS_IN_STATE_5(x)
#define	RX1_MANUAL_LPF_GAIN(x)
#define	RX_LPF_IDX_MASK   RX1_MANUAL_LPF_GAIN(~0)
#define	FORCE_RX1_DIGITAL_GAIN   (1 << 5) /* Force Rx1 Digital Gain */
#define	RX1_MANUALFORCED_DIGITAL_GAIN(x)
#define	RX_DIGITAL_IDX_MASK   RX1_MANUALFORCED_DIGITAL_GAIN(~0)
#define	RX2_MANUAL_FULL_TABLE_LMT_TABLE_GAIN_INDEX(x)
#define	RX2_MANUAL_LPF_GAIN(x)
#define	FORCE_RX2_DIGITAL_GAIN   (1 << 5) /* Force Rx2 Digital Gain */
#define	RX2_MANUALFORCED_DIGITAL_GAIN(x)
#define	ENABLE_GAIN_INC_AFTER_GAIN_LOCK   (1 << 7) /* Enable Gain Inc after Gain Lock */
#define	GOTO_OPT_GAIN_IF_ENERGY_LOST_OR_EN_AGC_HIGH   (1 << 6) /* Goto Opt Gain if Energy Lost or EN_AGC High */
#define	GOTO_SET_GAIN_IF_EN_AGC_HIGH   (1 << 5) /* Goto Set Gain if EN_AGC High */
#define	GOTO_SET_GAIN_IF_EXIT_RX_STATE   (1 << 4) /* Goto Set Gain if Exit Rx State */
#define	DONT_UNLOCK_GAIN_IF_ENERGY_LOST   (1 << 3) /* Don't Unlock Gain if Energy Lost */
#define	GOTO_OPTIMIZED_GAIN_IF_EXIT_RX_STATE   (1 << 2) /* Goto Optimized Gain if Exit Rx State */
#define	DONT_UNLOCK_GAIN_IF_LG_ADC_OR_LMT_OVRG   (1 << 1) /* Don't Unlock Gain If Lg ADC or LMT Ovrg */
#define	ENABLE_INCR_GAIN   (1 << 0) /* Enable Incr Gain */
#define	USE_LAST_LOCK_LEVEL_FOR_SET_GAIN   (1 << 7) /* Use Last Lock Level for Set Gain */
#define	ENABLE_LMT_GAIN_INC_FOR_LOCK_LEVEL   (1 << 6) /* Enable LMT Gain Inc for Lock Level */
#define	GOTO_MAX_GAIN_OR_OPT_GAIN_IF_EN_AGC_HIGH   (1 << 5) /* Goto Max Gain or Opt Gain if EN_AGC High */
#define	SETTLING_DELAY(x)
#define	POST_LOCK_LEVEL_STP_SIZE_FOR_LPF_TABLE_FULL_TABLE(x)
#define	ENERGY_LOST_THRESH(x)
#define	POST_LOCK_LEVEL_STP_FOR_LMT_TABLE(x)
#define	STRONGER_SIGNAL_THRESH(x)
#define	DONT_UNLOCK_GAIN_IF_ADC_OVRG   (1 << 7) /* Don't unlock gain if ADC Ovrg */
#define	LOW_POWER_THRESH(x)
#define	DONT_UNLOCK_GAIN_IF_STRONGER_SIGNAL   (1 << 7) /* Don't unlock gain if Stronger Signal */
#define	FINAL_OVER_RANGE_COUNT(x)
#define	OPTIMIZE_GAIN_OFFSET(x)
#define	INCREMENT_GAIN_STP_LPFLMT(x)
#define	ENERGY_DETECT_COUNT(x)
#define	AGCLL_MAX_INCREASE(x)
#define	GAIN_LOCK_EXIT_COUNT(x)
#define	INITIAL_LMT_GAIN_LIMIT(x)
#define	PREVENT_GAIN_INC   (1 << 7) /* Prevent Gain Inc */
#define	AGC_INNER_LOW_THRESH(x)
#define	LARGE_LMT_OVERLOAD_EXED_COUNTER(x)
#define	SMALL_LMT_OVERLOAD_EXED_COUNTER(x)
#define	LARGE_ADC_OVERLOAD_EXED_COUNTER(x)
#define	SMALL_ADC_OVERLOAD_EXED_COUNTER(x)
#define	IMMED_GAIN_CHANGE_IF_LG_LMT_OVERLOAD   (1 << 7) /* Immed. Gain Change if Lg LMT Overload */
#define	IMMED_GAIN_CHANGE_IF_LG_ADC_OVERLOAD   (1 << 3) /* Immed. Gain Change if Lg ADC Overload */
#define	AGC_INNER_HIGH_THRESH_EXED_STP_SIZE(x)
#define	AGC_INNER_LOW_THRESH_EXED_STP_SIZE(x)
#define	DOUBLE_GAIN_COUNTER   (1 << 5) /* Double Gain Counter */
#define	ENABLE_SYNC_FOR_GAIN_COUNTER   (1 << 4) /* Enable Sync for Gain Counter */
#define	DIG_SATURATION_EXED_COUNTER(x)
#define	AGC_OUTER_HIGH_THRESH(x)
#define	AGC_OUTER_LOW_THRESH(x)
#define	AGC_OUTER_HIGH_THRESH_EXED_STP_SIZE(x)
#define	AGC_OUTER_LOW_THRESH_EXED_STP_SIZE(x)
#define	EXT_LNA_HIGH_GAIN(x)
#define	EXT_LNA_LOW_GAIN(x)
#define	GAIN_TABLE_ADDRESS(x)
#define	EXT_LNA_CTRL   (1 << 7) /* Ext LNA Ctrl */
#define	LNA_GAIN(x)
#define	MIXER_GM_GAIN(x)
#define	TIA_GAIN   (1 << 5) /* TIA Gain */
#define	LPF_GAIN(x)
#define	RF_DC_CAL   (1 << 5) /* RF DC Cal */
#define	DIGITAL_GAIN(x)
#define	TO_LNA_GAIN(x)
#define	TO_MIXER_GM_GAIN(x)
#define	TO_LPF_GAIN(x)
#define	TO_DIGITAL_GAIN(x)
#define	WRITE_GAIN_TABLE   (1 << 2) /* Write Gain Table */
#define	START_GAIN_TABLE_CLOCK   (1 << 1) /* Start Gain Table Clock */
#define	RECEIVER_SELECT(x)
#define	GT_RX1   1
#define	GT_RX2   2
#define	GM_SUB_TABLE_GAIN_WRITE(x)
#define	GM_SUB_TABLE_BIAS_WRITE(x)
#define	GM_SUB_TABLE_CTRL_WRITE(x)
#define	GM_SUB_TABLE_GAIN_READ(x)
#define	GM_SUB_TABLE_BIAS_READ(x)
#define	GM_SUB_TABLE_CTRL_READ(x)
#define	WRITE_GM_SUB_TABLE   (1 << 2) /* Write Gm Sub Table */
#define	START_GM_SUB_TABLE_CLOCK   (1 << 1) /* Start Gm Sub Table Clock */
#define	CALIB_TABLE_GAIN_DIFFERROR_WORD(x)
#define	CALIB_TABLE_GAIN_ERROR(x)
#define	READ_SELECT   (1 << 4) /* Read Select */
#define	WRITE_MIXER_ERROR_TABLE   (1 << 3) /* Write Mixer Error Table */
#define	WRITE_LNA_ERROR_TABLE   (1 << 2) /* Write LNA Error Table */
#define	WRITE_LNA_GAIN_DIFF   (1 << 1) /* Write LNA Gain Diff */
#define	START_CALIB_TABLE_CLOCK   (1 << 0) /* Start Calib Table Clock */
#define	CALIB_TABLE_SELECT(x)
#define	LNA_CALIB_TABLE_GAIN_DIFFERENCE_WORD(x)
#define	MAX_MIXER_CALIBRATION_GAIN_INDEX(x)
#define	ENABLE_DIG_GAIN_CORR   (1 << 7) /* Enable Dig Gain Corr */
#define	FORCE_TEMP_SENSOR_FOR_CAL   (1 << 6) /* Force Temp Sensor for Cal */
#define	SETTLE_TIME(x)
#define	GAIN_CAL_MEAS_DURATION(x)
#define	MEASUREMENT_DURATION_1(x)
#define	MEASUREMENT_DURATION_0(x)
#define	MEASUREMENT_DURATION_3(x)
#define	MEASUREMENT_DURATION_2(x)
#define	START_RSSI_MEAS   (1 << 5) /* Start RSSI Meas (Mode 4) */
#define	ENABLE_ADC_POWER_MEAS   (1 << 1) /* Enable ADC Power Meas. */
#define	DEFAULT_RSSI_MEAS_MODE   (1 << 0) /* Default RSSI Meas Mode */
#define	RFIR_FOR_RSSI_MEASUREMENT(x)
#define	RSSI_MODE_SELECT(x)
#define	ADC_POWER_MEASUREMENT_DURATION_1(x)
#define	ADC_POWER_MEASUREMENT_DURATION_0(x)
#define	USE_HB3_OUT_FOR_ADC_PWR_MEAS   (1 << 7) /* Use HB3 Out for ADC Pwr Meas */
#define	USE_HB1_OUT_FOR_DEC_PWR_MEAS   (1 << 6) /* Use HB1 Out for Dec pwr Meas */
#define	ENABLE_DEC_PWR_MEAS   (1 << 5) /* Enable Dec Pwr Meas */
#define	DEFAULT_MODE_ADC_POWER   (1 << 4) /* Default Mode ADC Power */
#define	DEC_POWER_MEASUREMENT_DURATION(x)
#define	DB_GAIN_READBACK_CHANNEL   (1 << 0) /* dB Gain Read-back Channel */
#define	MAX_LNA_GAIN(x)
#define	RX_QUAD_CAL_LEVEL(x)
#define	ENABLE_PHASE_CORR   (1 << 7) /* Enable Phase Corr */
#define	ENABLE_GAIN_CORR   (1 << 6) /* Enable Gain Corr */
#define	USE_SETTLE_COUNT_FOR_DC_CAL_WAIT   (1 << 5) /* Use Settle Count for DC Cal Wait */
#define	FIXED_DC_CAL_WAIT_TIME   (1 << 4) /* Fixed DC Cal Wait Time */
#define	FREE_RUN_MODE   (1 << 3) /* Free Run Mode */
#define	ENABLE_CORR_WORD_DECIMATION   (1 << 2) /* Enable Corr Word Decimation */
#define	ENABLE_TRACKING_MODE_CH2   (1 << 1) /* Enable Tracking Mode CH2 */
#define	ENABLE_TRACKING_MODE_CH1   (1 << 0) /* Enable Tracking Mode CH1 */
#define	SOFT_RESET   (1 << 7) /* Soft Reset */
#define	CALIBRATION_CONFIG2_DFLT   (0x3 << 5) /* Must be 2'b11 */
#define	K_EXP_PHASE(x)
#define	PREVENT_POS_LOOP_GAIN   (1 << 7) /* Prevent Pos Loop Gain */
#define	K_EXP_AMPLITUDE(x)
#define	RX_FULL_TABLELMT_TABLE_GAIN(x)
#define	CORRECTION_WORD_DECIMATION_M(x)
#define	RX_LPF_GAIN(x)
#define	RX1_INPUT_A_I_DC_OFFSET_LSB(x)
#define	RX1_INPUT_A_Q_DC_OFFSET(x)
#define	RX2_INPUT_A_Q_DC_OFFSET_LSB(x)
#define	RX1_INPUT_A_I_DC_OFFSET_MSB(x)
#define	RX2_INPUT_A_I_DC_OFFSET(x)
#define	RX2_INPUT_A_Q_DC_OFFSET_MSB(x)
#define	RX1_INPUT_BC_I_DC_OFFSET_LSB(x)
#define	RX1_INPUT_BC_Q_DC_OFFSET(x)
#define	RX2_INPUT_BC_Q_DC_OFFSET_LSB(x)
#define	RX1_INPUT_BC_I_DC_OFFSET_MSB(x)
#define	RX2_INPUT_BC_I_DC_OFFSET(x)
#define	RX2_INPUT_BC_Q_DC_OFFSET_MSB(x)
#define	RX2_INPUT_BC_FORCE_OFFSET   (1 << 7) /* Rx2 Input B&C Force offset */
#define	RX1_INPUT_BC_FORCE_OFFSET   (1 << 6) /* Rx1 Input B&C Force offset */
#define	RX2_INPUT_BC_FORCE_PHGAIN   (1 << 5) /* Rx2 Input B&C Force Ph/Gain */
#define	RX1_INPUT_BC_FORCE_PHGAIN   (1 << 4) /* Rx1 Input B&C Force Ph/Gain */
#define	RX2_INPUT_A_FORCE_OFFSET   (1 << 3) /* Rx2 Input A Force offset */
#define	RX1_INPUT_A_FORCE_OFFSET   (1 << 2) /* Rx1 Input A Force offset */
#define	RX2_INPUT_A_FORCE_PHGAIN   (1 << 1) /* Rx2 Input A Force Ph/Gain */
#define	RX1_INPUT_A_FORCE_PHGAIN   (1 << 0) /* Rx1 Input A Force Ph/Gain */
#define	DAC_FS(x)
#define	RF_DC_CALIBRATION_COUNT(x)
#define	RF_DC_OFFSET_TABLE_UPDATE_COUNT(x)
#define	RF_DC_OFFSET_ATTEN(x)
#define	INVERT_RX2_RF_DC_CGIN_WORD   (1 << 7) /* Invert Rx2 RF DC CGin Word */
#define	INVERT_RX1_RF_DC_CGIN_WORD   (1 << 6) /* Invert Rx1 RF DC CGin Word */
#define	INVERT_RX2_RF_DC_CGOUT_WORD   (1 << 5) /* Invert Rx2 RF DC CGout Word */
#define	INVERT_RX1_RF_DC_CGOUT_WORD   (1 << 4) /* Invert Rx1 RF DC CGout Word */
#define	USE_WAIT_COUNTER_FOR_RF_DC_INIT_CAL   (1 << 7) /* Use Wait Counter for RF DC Init Cal */
#define	ENABLE_FAST_SETTLE_MODE   (1 << 6) /* Enable Fast Settle Mode */
#define	ENABLE_BB_DC_OFFSET_TRACKING   (1 << 5) /* Enable BB DC Offset Tracking */
#define	RESET_ACC_ON_GAIN_CHANGE   (1 << 4) /* Reset Acc on Gain Change */
#define	ENABLE_RF_OFFSET_TRACKING   (1 << 3) /* Enable RF Offset Tracking */
#define	DC_OFFSET_UPDATE(x)
#define	RF_MINIMUM_CALIBRATION_GAIN_INDEX(x)
#define	RF_SOI_THRESH(x)
#define	INCREASE_COUNT_DURATION   (1 << 7) /* Increase Count Duration */
#define	BB_TRACKING_DECIMATE(x)
#define	BB_DC_M_SHIFT(x)
#define	READ_BACK_CH_SEL   (1 << 7) /* Read Back CH Sel */
#define	UPDATE_TRACKING_WORD   (1 << 6) /* Update Tracking Word */
#define	FORCE_RX_NULL   (1 << 5) /* Force Rx Null */
#define	BB_DC_TRACKING_FAST_SETTLE_M_SHIFT(x)
#define	BB_DC_OFFSET_ATTEN(x)
#define	RX1_BB_DC_OFFSET_CORRECTION_WORD_I(x)
#define	RX1_BB_DC_OFFSET_CORRECTION_WORD_Q(x)
#define	RX2_BB_DC_OFFSET_CORRECTION_WORD_I(x)
#define	RX2_BB_DC_OFFSET_CORRECTION_WORD_Q(x)
#define	RX1RX2_BB_DC_OFFSET_TRACKING_CORRECTION_WORD_I(x)
#define	RX1RX2_BB_DC_OFFSET_TRACKING_CORRECTION_WORD_Q(x)
#define	RX2_RSSI_SYMBOL   (1 << 1) /* Rx2 RSSI symbol <0> */
#define	RX1_RSSI_SYMBOL   (1 << 0) /* Rx1 RSSI symbol <0> */
#define	RX2_RSSI_PREAMBLE   (1 << 1) /* Rx2 RSSI preamble <0> */
#define	RX1_RSSI_PREAMBLE   (1 << 0) /* Rx1 RSSI preamble <0> */
#define	RSSI_LSB_SHIFT   1
#define	RSSI_LSB_MASK1   0x01
#define	RSSI_LSB_MASK2   0x02
#define	RX_PATH_GAIN   (1 << 0) /* Rx Path Gain<0> */
#define	FORCE_RX2_LNA_GAIN   (1 << 7) /* Force Rx2 LNA Gain */
#define	RX2_LNA_BYPASS   (1 << 6) /* Rx2 LNA Bypass */
#define	FORCE_RX1_LNA_GAIN   (1 << 3) /* Force Rx1 LNA Gain */
#define	RX1_LNA_BYPASS   (1 << 2) /* Rx1 LNA Bypass */
#define	RX2_LNA_GAIN(x)
#define	RX1_LNA_GAIN(x)
#define	RX_LNA_BIAS_COARSE(x)
#define	RX_LNA_PCASCODE_BIAS(x)
#define	RX_LNA_BIAS(x)
#define	RX_LNA_P_CASCODE_BIAS_FINE(x)
#define	RX_MIX_GM_CM_OUT(x)
#define	RX_MIX_GM_PLOAD(x)
#define	FORCE_RX1_MIX_GM   (1 << 6) /* Force Rx1 Mix Gm */
#define	RX1_MIX_GM_GAIN(x)
#define	RX1_MIX_GM_BIAS(x)
#define	FORCE_RX2_MIX_GM   (1 << 6) /* Force Rx2 Mix Gm */
#define	RX2_MIX_GM_GAIN(x)
#define	RX2_MIX_GM_BIAS(x)
#define	INPUT_A_RX1_Q(x)
#define	INPUT_A_RX1_I(x)
#define	INPUT_A_RX2_I(x)
#define	INPUT_A_RX2_Q(x)
#define	INPUTS_BC_RX1_Q(x)
#define	INPUTS_BC_RX1_I(x)
#define	INPUTS_BC_RX2_I(x)
#define	INPUTS_BC_RX2_Q(x)
#define	FORCE_CGIN_DAC   (1 << 2) /* Force CGin DAC */
#define	RX_MIX_LO_CM(x)
#define	RX_CGB_SEG_ENABLE(x)
#define	RX_CGB_INPUT_CM_SEL(x)
#define	RX_CGB_BIAS(x)
#define	TIA2_OVERRIDE_C   (1 << 3) /* TIA2 Override C */
#define	TIA2_OVERRIDE_R   (1 << 2) /* TIA2 Override R */
#define	TIA1_OVERRIDE_C   (1 << 1) /* TIA1 Override C */
#define	TIA1_OVERRIDE_R   (1 << 0) /* TIA1 Override R */
#define	TIA_SEL_CC(x)
#define	TIA1_RF(x)
#define	TIA1_C_LSB(x)
#define	TIA1_C_MSB(x)
#define	TIA2_RF(x)
#define	TIA2_C_LSB(x)
#define	TIA2_C_MSB(x)
#define	FORCE_RX1_RESISTORS   (1 << 7) /* Force Rx1 Resistors */
#define	RX1_BBF_R1A(x)
#define	FORCE_RX2_RESISTORS   (1 << 7) /* Force Rx2 Resistors */
#define	RX2_BBF_R1A(x)
#define	RX1_TUNE_RESAMPLE_PHASE   (1 << 2) /* Rx1 Tune Resample Phase */
#define	RX1_TUNE_RESAMPLE   (1 << 1) /* Rx1 Tune Resample */
#define	RX1_PD_TUNE   (1 << 0) /* Rx1 PD Tune */
#define	RX2_TUNE_RESAMPLE_PHASE   (1 << 2) /* Rx2 Tune Resam ple Phase */
#define	RX2_TUNE_RESAMPLE   (1 << 1) /* Rx2 Tune Resample */
#define	RX2_PD_TUNE   (1 << 0) /* Rx2 PD Tune */
#define	TUNE_OVERRIDE   (1 << 7) /* Tune Override */
#define	RX_BBF_R2346(x)
#define	RX_BBF_C1_MSB(x)
#define	RX_BBF_C1_LSB(x)
#define	RX_BBF_C2_MSB(x)
#define	RX_BBF_C2_LSB(x)
#define	RX_BBF_C3_MSB(x)
#define	RX_BBF_C3_LSB(x)
#define	RX_BBF_CC1_CTR(x)
#define	MUST_BE_ZERO   (1 << 7) /* Must be zero */
#define	RX1_BBF_POW_CTR(x)
#define	RX_BBF_RZ1_CTR(x)
#define	RX_BBF_CC2_CTR(x)
#define	RX_BBF_POW3_CTR(x)
#define	RX_BBF_RZ3_CTR(x)
#define	RX_BBF_POW2_CTR(x)
#define	RX_BBF_RZ2_CTR(x)
#define	RX_BBF_CC3_CTR(x)
#define	RXBBF_BYPASS_BIAS_R   (1 << 7) /* RxBBF Bypass Bias R */
#define	RX_BBF_R5_TUNE   (1 << 4) /* Rx BBF R5 Tune */
#define	RX1_BBF_TUNE_COMP_I   (1 << 3) /* Rx1 BBF Tune Comp I */
#define	RX1_BBF_TUNE_COMP_Q   (1 << 2) /* Rx1 BBF Tune Comp Q */
#define	RX2_BBF_TUNE_COMP_I   (1 << 1) /* Rx2 BBF Tune Comp I */
#define	RX2_BBF_TUNE_COMP_Q   (1 << 0) /* Rx2 BBF Tune Comp Q */
#define	RX_BBF_TUNE_CTR(x)
#define	RX1_BBF_FORCE_GAIN   (1 << 5) /* Rx1 BBF Force Gain */
#define	RX1_BBF_BQ_GAIN(x)
#define	RX1_BBF_POLE_GAIN(x)
#define	RX2_BBF_FORCE_GAIN   (1 << 5) /* Rx2 BBF Force Gain */
#define	RX2_BBF_BQ_GAIN(x)
#define	RX2_BBF_POLE_GAIN(x)
#define	RX_TUNE_EVALTIME   (1 << 4) /* Rx Tune Evaltime */
#define	RX_BBF_TUNE_DIVIDE   (1 << 0) /* RX BBF Tune Divide<8> */
#define	TUNE_COMP_MASK(x)
#define	RX_TUNE_MODE(x)
#define	POLE_GAIN_TUNE(x)
#define	RX_TUNE_BBBW_MHZ(x)
#define	RX_TUNE_BBBW_KHZ(x)
#define	BYPASS_LD_SYNTH   (1 << 0) /* Bypass Ld Synth */
#define	SYNTH_INTEGER_WORD(x)
#define	SYNTH_FRACT_WORD(x)
#define	VCO_CAL_OFFSET(x)
#define	INIT_ALC_VALUE(x)
#define	VCO_VARACTOR(x)
#define	PORB_VCO_LOGIC   (1 << 6) /* PORb VCO Logic */
#define	VCO_OUTPUT_LEVEL(x)
#define	CHARGE_PUMP_CURRENT(x)
#define	SYNTH_RECAL   (1 << 7) /* Synth Re-Cal */
#define	HALF_VCO_CAL_CLK   (1 << 7) /* Half Vco Cal Clk */
#define	CP_OFFSET_OFF   (1 << 4) /* CP Offset Off */
#define	F_CPCAL   (1 << 3) /* F Cpcal */
#define	CP_CAL_ENABLE   (1 << 2) /* Cp Cal Enable */
#define	LOOP_FILTER_C2(x)
#define	LOOP_FILTER_C1(x)
#define	LOOP_FILTER_R1(x)
#define	LOOP_FILTER_C3(x)
#define	LOOP_FILTER_BYPASS_R3   (1 << 7) /* Loop Filter Bypass R3 */
#define	LOOP_FILTER_BYPASS_R1   (1 << 6) /* Loop Filter Bypass R1 */
#define	LOOP_FILTER_BYPASS_C2   (1 << 5) /* Loop Filter Bypass C2 */
#define	LOOP_FILTER_BYPASS_C1   (1 << 4) /* Loop Filter Bypass C1 */
#define	LOOP_FILTER_R3(x)
#define	FORCED_CP_CAL_WORD(x)
#define	VCO_BIAS_TCF(x)
#define	VCO_BIAS_REF(x)
#define	CP_CAL_VALID   (1 << 7) /* CP Cal Valid */
#define	CP_CAL_DONE   (1 << 5) /* CP Cal Done */
#define	VCO_CAL_BUSY   (1 << 4) /* VCO Cal Busy */
#define	CP_CAL_WORD(x)
#define	VCO_CAL_REF_TCF(x)
#define	POWER_DOWN_VARACTOR_REF   (1 << 3) /* Power Down Varactor Ref */
#define	PWR_DOWN_VARACT_REF_TCF   (1 << 2) /* Pwr Down Varact Ref Tcf */
#define	POWER_DOWN_CAL_TCF   (1 << 1) /* Power Down Cal Tcf */
#define	POWER_DOWN_VCO_BUFFFER   (1 << 0) /* Power Down VCO Bufffer */
#define	CP_OVRG_HIGH   (1 << 7) /* CP Ovrg High */
#define	CP_OVRG_LOW   (1 << 6) /* CP Ovrg Low */
#define	VCO_LOCK   (1 << 1) /* Lock */
#define	VCO_LDO_BYPASS   (1 << 7) /* VCO LDO Bypass */
#define	VCO_LDO_INRUSH(x)
#define	VCO_LDO_SEL(x)
#define	VCO_LDO_VDROP_SEL(x)
#define	VCO_CAL_EN   (1 << 7) /* VCO Cal En */
#define	VCO_CAL_ALC_WAIT(x)
#define	VCO_CAL_COUNT(x)
#define	LOCK_DETECT_COUNT(x)
#define	LOCK_DETECT_MODE(x)
#define	CP_LEVEL_DETECT_POWER_DOWN   (1 << 6) /* CP Level Detect Power Down */
#define	CP_LEVEL_THRESH_LOW(x)
#define	CP_LEVEL_THRESH_HIGH(x)
#define	DSM_PROG(x)
#define	SIF_CLOCK   (1 << 6) /* SIF clock */
#define	SIF_RESET_BAR   (1 << 5) /* SIF Reset Bar */
#define	SIF_ADDR(x)
#define	UPDATE_FREQ_WORD   (1 << 7) /* Update Freq Word */
#define	READ_EFFECTIVE_TUNING_WORD   (1 << 5) /* Read Effective Tuning Word */
#define	FREQ_CORRECTION_WORD_MSB(x)
#define	UPDATE_FREQ_WORD   (1 << 7) /* Update Freq Word */
#define	FREQ_CORRECTION_WORD_LSB(x)
#define	VCO_VARACTOR_REFERENCE_TCF(x)
#define	VCO_VARACTOR_OFFSET(x)
#define	VCO_VARACTOR_REFERENCE(x)
#define	RX_FAST_LOCK_LOAD_SYNTH   (1 << 3) /* Rx Fast Lock Load Synth */
#define	RX_FAST_LOCK_PROFILE_INIT   (1 << 2) /* Rx Fast Lock Profile Init */
#define	RX_FAST_LOCK_PROFILE_PIN_SELECT   (1 << 1) /* Rx Fast Lock Profile Pin Select */
#define	RX_FAST_LOCK_MODE_ENABLE   (1 << 0) /* Rx Fast Lock Mode Enable */
#define	RX_FAST_LOCK_PROFILE(x)
#define	RX_FAST_LOCK_PROFILE_ADDR(x)
#define	RX_FAST_LOCK_PROFILE_WORD(x)
#define	RX_FAST_LOCK_PROGRAM_WRITE   (1 << 1) /* Rx Fast Lock Program Write */
#define	RX_FAST_LOCK_PROGRAM_CLOCK_ENABLE   (1 << 0) /* Rx Fast Lock Program Clock Enable */
#define	RX_FAST_LOCK_CONFIG_WORD_NUM   16
#define	RX_LO_GEN_POWER_MODE(x)
#define	DIV_TEST_EN   (1 << 5) /* Div Test En */
#define	PFD_CLK_EDGE   (1 << 1) /* PFD Clk Edge */
#define	BYPASS_LD_SYNTH   (1 << 0) /* Bypass Ld Synth */
#define	PFD_WIDTH(x)
#define	SDM_BYPASS   (1 << 7) /* SDM Bypass */
#define	SDM_POWER_DOWN   (1 << 6) /* SDM Power Down */
#define	SYNTH_INTEGER_WORD(x)
#define	SYNTH_FRACT_WORD(x)
#define	FORCE_ALC_ENABLE   (1 << 7) /* Force ALC Enable */
#define	FORCE_ALC_WORD(x)
#define	BYPASS_LOAD_DELAY   (1 << 7) /* Bypass Load Delay */
#define	FORCE_VCO_TUNE_ENABLE   (1 << 1) /* Force VCO Tune Enable */
#define	FORCE_VCO_TUNE   (1 << 0) /* Force VCO Tune */
#define	VCO_CAL_OFFSET(x)
#define	INIT_ALC_VALUE(x)
#define	VCO_VARACTOR(x)
#define	PORB_VCO_LOGIC   (1 << 6) /* PORb VCO Logic */
#define	VCO_OUTPUT_LEVEL(x)
#define	TX_CP_CURRENT_DFLT   (1 << 7) /* Set to 1 */
#define	VTUNE_FORCE   (1 << 6) /* Vtune Force */
#define	CHARGE_PUMP_CURRENT(x)
#define	SYNTH_RECAL   (1 << 7) /* Synth Re-Cal */
#define	CHARGE_PUMP_OFFSET(x)
#define	HALF_VCO_CAL_CLK   (1 << 7) /* Half Vco Cal Clk */
#define	DITHER_MODE   (1 << 6) /* Dither Mode */
#define	CP_OFFSET_OFF   (1 << 4) /* Cp Offset Off */
#define	F_CPCAL   (1 << 3) /* F Cpcal */
#define	CP_CAL_ENABLE   (1 << 2) /* Cp Cal Enable */
#define	CP_TEST(x)
#define	LOOP_FILTER_C2(x)
#define	LOOP_FILTER_C1(x)
#define	LOOP_FILTER_R1(x)
#define	LOOP_FILTER_C3(x)
#define	LOOP_FILTER_BYPASS_R3   (1 << 7) /* Loop Filter Bypass R3 */
#define	LOOP_FILTER_BYPASS_R1   (1 << 6) /* Loop Filter Bypass R1 */
#define	LOOP_FILTER_BYPASS_C2   (1 << 5) /* Loop Filter Bypass C2 */
#define	LOOP_FILTER_BYPASS_C1   (1 << 4) /* Loop Filter Bypass C1 */
#define	LOOP_FILTER_R3(x)
#define	NUMBER_SDM_DITHER_BITS(x)
#define	FORCED_CP_CAL_WORD(x)
#define	MUST_BE_ZEROS(x)
#define	VCO_BIAS_TCF(x)
#define	VCO_BIAS_REF(x)
#define	VCO_BYPASS_BIAS_DAC_R   (1 << 7) /* VCO Bypass Bias DAC R */
#define	VCO_COMP_BYPASS_BIAS_R   (1 << 4) /* VCO Comp Bypass Bias R */
#define	BYPASS_PRESCALE_R   (1 << 3) /* Bypass Prescale R */
#define	LAST_ALC_ENABLE   (1 << 2) /* Last ALC Enable */
#define	PRESCALE_BIAS(x)
#define	CP_CAL_VALID   (1 << 7) /* CP Cal Valid */
#define	COMP_OUT   (1 << 6) /* Comp Out */
#define	CP_CAL_DONE   (1 << 5) /* CP Cal Done */
#define	VCO_CAL_BUSY   (1 << 4) /* VCO Cal Busy */
#define	CP_CAL_WORD(x)
#define	VCO_CAL_REF_MONITOR   (1 << 3) /* VCO Cal Ref Monitor */
#define	VCO_CAL_REF_TCF(x)
#define	POWER_DOWN_VARACTOR_REF   (1 << 3) /* Power Down Varactor Ref */
#define	POWER_DOWN_VARACT_REF_TCF   (1 << 2) /* Power Down Varact Ref Tcf */
#define	POWER_DOWN_CAL_TCF   (1 << 1) /* Power Down Cal Tcf */
#define	POWER_DOWN_VCO_BUFFFER   (1 << 0) /* Power Down VCO Bufffer */
#define	CP_OVRG_HIGH   (1 << 7) /* CP Ovrg High */
#define	CP_OVRG_LOW   (1 << 6) /* CP Ovrg Low */
#define	VCO_LOCK   (1 << 1) /* Lock */
#define	VCO_LDO_BYPASS   (1 << 7) /* VCO LDO Bypass */
#define	VCO_LDO_INRUSH(x)
#define	VCO_LDO_VOUT_SEL(x)
#define	VCO_LDO_VDROP_SEL(x)
#define	VCO_CAL_EN   (1 << 7) /* VCO Cal En */
#define	VCO_CAL_ALC_WAIT(x)
#define	VCO_CAL_COUNT(x)
#define	FB_CLOCK_ADV(x)
#define	LOCK_DETECT_COUNT(x)
#define	LOCK_DETECT_MODE(x)
#define	CP_LEVEL_DETECT_POWER_DOWN   (1 << 6) /* CP Level Detect Power Down */
#define	CP_LEVEL_DETECT_THRESH_LOW(x)
#define	CP_LEVEL_DETECT_THRESH_HIGH(x)
#define	DSM_PROG(x)
#define	SIF_CLOCK   (1 << 6) /* SIF clock */
#define	SIF_RESET_BAR   (1 << 5) /* SIF Reset Bar */
#define	SIF_ADDR(x)
#define	UPDATE_FREQ_WORD   (1 << 7) /* Update Freq Word */
#define	READ_EFFECTIVE_TUNING_WORD   (1 << 5) /* Read Effective Tuning Word */
#define	FREQ_CORRECTION_WORD_MSB(x)
#define	UPDATE_FREQ_WORD   (1 << 7) /* Update Freq Word */
#define	FREQ_CORRECTION_WORD_LSB(x)
#define	VCO_VARACTOR_REFERENCE_TCF(x)
#define	VCO_VARACTOR_OFFSET(x)
#define	VCO_VARACTOR_REFERENCE(x)
#define	DCXO_TUNE_COARSE(x)
#define	DCXO_TUNE_FINE_LOW(x)
#define	DCXO_TUNE_FINE_HIGH(x)
#define	MUST_BE_ZERO   (1 << 7) /* Must be zero */
#define	DCXO_RTAIL(x)
#define	DCXO_RD(x)
#define	DCXO_TEMPCO_EN   (1 << 7) /* DCXO Tempco En */
#define	DCXO_TEMPCO_CLK   (1 << 6) /* DCXO Tempco Clk */
#define	DCXO_TEMPERATURE_COEF_ADDRESS(x)
#define	TX_FAST_LOCK_LOAD_SYNTH   (1 << 3) /* Tx Fast Lock Load Synth */
#define	TX_FAST_LOCK_PROFILE_INIT   (1 << 2) /* Tx Fast Lock Profile Init */
#define	TX_FAST_LOCK_PROFILE_PIN_SELECT   (1 << 1) /* Tx Fast Lock Profile Pin Select */
#define	TX_FAST_LOCK_MODE_ENABLE   (1 << 0) /* Tx Fast Lock Mode Enable */
#define	TX_FAST_LOCK_PROFILE(x)
#define	TX_FAST_LOCK_PROGRAM_WRITE   (1 << 1) /* Tx Fast Lock Program Write */
#define	TX_FAST_LOCK_PROGRAM_CLOCK_ENABLE   (1 << 0) /* Tx Fast Lock Program Clock Enable */
#define	TX_LO_GEN_POWER_MODE(x)
#define	POWER_DOWN_BANDGAP_REF   (1 << 7) /* Power Down Bandgap Ref */
#define	MASTER_BIAS_FILTER_BYPASS   (1 << 6) /* Master Bias Filter Bypass */
#define	MASTER_BIAS_REF_SEL   (1 << 5) /* Master Bias Ref Sel */
#define	MASTER_BIAS_TRIM(x)
#define	VCO_LDO_FILTER_BYPASS   (1 << 7) /* VCO LDO Filter Bypass */
#define	VCO_LDO_REF_SEL   (1 << 6) /* VCO LDO Ref Sel */
#define	BANDGAP_REF_RESET   (1 << 5) /* Bandgap Ref Reset */
#define	BANDGAP_TEMP_TRIM(x)
#define	REF_DIVIDE_CONFIG_1_DFLT   (1 << 2) /* Set to 1 */
#define	RX_REF_RESET_BAR   (1 << 1) /* Rx Ref Reset Bar */
#define	RX_REF_DIVIDER_MSB   (1 << 0) /* Rx Ref Divider<1> */
#define	RX_REF_DIVIDER_LSB   (1 << 7) /* Rx Ref Divider< 0> */
#define	TX_REF_RESET_BAR   (1 << 4) /* Tx Ref Reset Bar */
#define	RX_REF_DOUBLER_FB_DELAY(x)
#define	TX_REF_DIVIDER(x)
#define	TX_REF_DOUBLER_FB_DELAY(x)
#define	FULL_TABLE_GAIN_INDEX(x)
#define	LPF_GAIN_RX(x)
#define	DIGITAL_GAIN_RX(x)
#define	FAST_ATTACK_STATE_RX2(x)
#define	FAST_ATTACK_STATE_RX1(x)
#define	FAST_ATK_MASK   0x7
#define	RX1_FAST_ATK_SHIFT   0
#define	RX2_FAST_ATK_SHIFT   4
#define	FAST_ATK_RESET   0
#define	FAST_ATK_PEAK_DETECT   1
#define	FAST_ATK_PWR_MEASURE   2
#define	FAST_ATK_FINAL_SETTELING   3
#define	FAST_ATK_FINAL_OVER   4
#define	FAST_ATK_GAIN_LOCKED   5
#define	SLOW_LOOP_STATE_RX2(x)
#define	SLOW_LOOP_STATE_RX1(x)
#define	GAIN_LOCK_1   (1 << 6) /* Gain Lock 1 */
#define	LOW_POWER_1   (1 << 5) /* Low Power 1 */
#define	LARGE_LMT_OL   (1 << 4) /* Large LMT OL */
#define	SMALL_LMT_OL   (1 << 3) /* Small LMT OL */
#define	LARGE_ADC_OL   (1 << 2) /* Large ADC OL */
#define	SMALL_ADC_OL   (1 << 1) /* Small ADC OL */
#define	DIG_SAT   (1 << 0) /* Dig Sat */
#define	CTRL_ENABLE   (1 << 0) /* Set to 1 */
#define	TONE_PRBS   (1 << 1) /* Tone/ PRBS */
#define	BIST_ENABLE   (1 << 0) /* BIST Enable */
#define	TONE_FREQ(x)
#define	TONE_LEVEL(x)
#define	BIST_CTRL_POINT(x)
#define	DATA_PORT_SP_HD_LOOP_TEST_OE   (1 << 7) /* Data Port SP, HD Loop Test OE */
#define	RX_MASK   (1 << 6) /* Rx Mask */
#define	CHANNEL   (1 << 5) /* Channel */
#define	DATA_PORT_LOOP_TEST_ENABLE   (1 << 0) /* Data Port Loop Test Enable */
#define	OBSERVATION_POINT(x)
#define	BIST_MASK_CHANNEL_2_Q_DATA   (1 << 5) /* BIST Mask Channel 2 Q data */
#define	BIST_MASK_CHANNEL_2_I_DATA   (1 << 4) /* BIST Mask Channel 2 I data */
#define	BIST_MASK_CHANNEL_1_Q_DATA   (1 << 3) /* BIST Mask Channel 1 Q data */
#define	BIST_MASK_CHANNEL_1_I_DATA   (1 << 2) /* BIST Mask Channel 1 I data */
#define	DATA_PORT_HILOW   (1 << 1) /* Data Port Hi/Low */
#define	USE_DATA_PORT   (1 << 0) /* Use Data Port */
#define	TEMP_SENSE_VBE_TEST(x)
#define	DAC_TEST_ENABLE   (1 << 7) /* DAC Test Enable */
#define	DAC_TEST_WORD(x)
#define	AD_READ   (0 << 15)
#define	AD_WRITE   (1 << 15)
#define	AD_CNT(x)
#define	AD_ADDR(x)
#define	RSSI_MULTIPLIER   100
#define	RSSI_RESOLUTION   ((int) (0.25 * RSSI_MULTIPLIER))
#define	RSSI_MAX_WEIGHT   255
#define	MAX_LMT_INDEX   40
#define	MAX_LPF_GAIN   24
#define	MAX_DIG_GAIN   31
#define	MAX_BBPLL_FREF   70007000UL /* 70 MHz + 100ppm */
#define	MIN_BBPLL_FREQ   714928500UL /* 715 MHz - 100ppm */
#define	MAX_BBPLL_FREQ   1430143000UL /* 1430 MHz + 100ppm */
#define	MAX_BBPLL_DIV   64
#define	MIN_BBPLL_DIV   2
#define	MIN_ADC_CLK   25000000U /* 25 MHz */
#define	MAX_ADC_CLK   640000000U /* 640 MHz */
#define	MAX_DAC_CLK   (MAX_ADC_CLK / 2)
#define	MAX_RX_HB1   245760000UL
#define	MAX_RX_HB2   320000000UL
#define	MAX_RX_HB3   640000000UL
#define	MAX_TX_HB1   160000000UL
#define	MAX_TX_HB2   320000000UL
#define	MAX_TX_HB3   320000000UL
#define	MAX_BASEBAND_RATE   61440000UL
#define	MAX_MBYTE_SPI   8
#define	RFPLL_MODULUS   8388593UL
#define	BBPLL_MODULUS   2088960UL
#define	MAX_SYNTH_FREF   80008000UL /* 80 MHz + 100ppm */
#define	MIN_SYNTH_FREF   9999000UL /* 10 MHz - 100ppm */
#define	MIN_VCO_FREQ_HZ   6000000000ULL
#define	MAX_CARRIER_FREQ_HZ   6000000000ULL
#define	MIN_RX_CARRIER_FREQ_HZ   70000000ULL
#define	MIN_TX_CARRIER_FREQ_HZ   46875001ULL
#define	AD9363A_MAX_CARRIER_FREQ_HZ   3800000000ULL
#define	AD9363A_MIN_CARRIER_FREQ_HZ   325000000ULL
#define	MAX_TX_ATTENUATION_DB   89750
#define	FASTLOOK_INIT   1

Enumerations
enum	rx_gain_table_type {   RXGAIN_FULL_TBL ,   RXGAIN_SPLIT_TBL }
enum	rx_gain_table_name {   TBL_200_1300_MHZ ,   TBL_1300_4000_MHZ ,   TBL_4000_6000_MHZ ,   RXGAIN_TBLS_END }
enum	fir_dest {   FIR_TX1 = 0x01 ,   FIR_TX2 = 0x02 ,   FIR_TX1_TX2 = 0x03 ,   FIR_RX1 = 0x81 ,   FIR_RX2 = 0x82 ,   FIR_RX1_RX2 = 0x83 ,   FIR_IS_RX = 0x80 }
enum	rf_gain_ctrl_mode {   RF_GAIN_MGC ,   RF_GAIN_FASTATTACK_AGC ,   RF_GAIN_SLOWATTACK_AGC ,   RF_GAIN_HYBRID_AGC }
enum	f_agc_target_gain_index_type {   MAX_GAIN ,   SET_GAIN ,   OPTIMIZED_GAIN ,   NO_GAIN_CHANGE }
enum	rssi_restart_mode {   AGC_IN_FAST_ATTACK_MODE_LOCKS_THE_GAIN ,   EN_AGC_PIN_IS_PULLED_HIGH ,   ENTERS_RX_MODE ,   GAIN_CHANGE_OCCURS ,   SPI_WRITE_TO_REGISTER ,   GAIN_CHANGE_OCCURS_OR_EN_AGC_PIN_PULLED_HIGH }
enum	ad9361_pdata_rx_freq {   BBPLL_FREQ ,   ADC_FREQ ,   R2_FREQ ,   R1_FREQ ,   CLKRF_FREQ ,   RX_SAMPL_FREQ ,   NUM_RX_CLOCKS }
enum	ad9361_pdata_tx_freq {   IGNORE ,   DAC_FREQ ,   T2_FREQ ,   T1_FREQ ,   CLKTF_FREQ ,   TX_SAMPL_FREQ ,   NUM_TX_CLOCKS }
enum	ad9361_clkout {   CLKOUT_DISABLE ,   BUFFERED_XTALN_DCXO ,   ADC_CLK_DIV_2 ,   ADC_CLK_DIV_3 ,   ADC_CLK_DIV_4 ,   ADC_CLK_DIV_8 ,   ADC_CLK_DIV_16 }
enum	{   LUT_FTDD_40 ,   LUT_FTDD_60 ,   LUT_FTDD_80 ,   LUT_FTDD_ENT }
enum	ad9361_clocks {   BB_REFCLK ,   RX_REFCLK ,   TX_REFCLK ,   BBPLL_CLK ,   ADC_CLK ,   R2_CLK ,   R1_CLK ,   CLKRF_CLK ,   RX_SAMPL_CLK ,   DAC_CLK ,   T2_CLK ,   T1_CLK ,   CLKTF_CLK ,   TX_SAMPL_CLK ,   RX_RFPLL_INT ,   TX_RFPLL_INT ,   RX_RFPLL_DUMMY ,   TX_RFPLL_DUMMY ,   RX_RFPLL ,   TX_RFPLL ,   NUM_AD9361_CLKS ,   EXT_REF_CLK }
enum	dig_tune_flags {   BE_VERBOSE = 1 ,   BE_MOREVERBOSE = 2 ,   DO_IDELAY = 4 ,   DO_ODELAY = 8 ,   SKIP_STORE_RESULT = 16 ,   RESTORE_DEFAULT = 32 }
enum	ad9361_bist_mode {   BIST_DISABLE ,   BIST_INJ_TX ,   BIST_INJ_RX }
enum	synth_pd_ctrl {   LO_DONTCARE ,   LO_OFF ,   LO_ON }
enum	dev_id {   ID_AD9361 ,   ID_AD9364 ,   ID_AD9363A }
enum	debugfs_cmd {   DBGFS_NONE ,   DBGFS_INIT ,   DBGFS_LOOPBACK ,   DBGFS_BIST_PRBS ,   DBGFS_BIST_TONE ,   DBGFS_BIST_DT_ANALYSIS ,   DBGFS_RXGAIN_1 ,   DBGFS_RXGAIN_2 }

Functions
int32_t	ad9361_spi_readm (struct no_os_spi_desc *spi, uint32_t reg, uint8_t *rbuf, uint32_t num)
int32_t	ad9361_spi_read (struct no_os_spi_desc *spi, uint32_t reg)
int32_t	ad9361_reg_read (struct ad9361_rf_phy *phy, uint32_t reg, uint32_t *val)
int32_t	ad9361_spi_write (struct no_os_spi_desc *spi, uint32_t reg, uint32_t val)
int32_t	ad9361_reg_write (struct ad9361_rf_phy *phy, uint32_t reg, uint32_t val)
int32_t	ad9361_reset (struct ad9361_rf_phy *phy)
int32_t	ad9361_register_clocks (struct ad9361_rf_phy *phy)
int32_t	ad9361_unregister_clocks (struct ad9361_rf_phy *phy)
uint32_t	ad9361_gt (struct ad9361_rf_phy *phy)
int32_t	ad9361_init_gain_tables (struct ad9361_rf_phy *phy)
int32_t	ad9361_setup (struct ad9361_rf_phy *phy)
int32_t	ad9361_post_setup (struct ad9361_rf_phy *phy)
int32_t	ad9361_set_ensm_mode (struct ad9361_rf_phy *phy, bool fdd, bool pinctrl)
int32_t	ad9361_ensm_set_state (struct ad9361_rf_phy *phy, uint8_t ensm_state, bool pinctrl)
int32_t	ad9361_set_rx_gain (struct ad9361_rf_phy *phy, uint32_t rx_id, struct rf_rx_gain *rx_gain)
int32_t	ad9361_get_rx_gain (struct ad9361_rf_phy *phy, uint32_t rx_id, struct rf_rx_gain *rx_gain)
int32_t	ad9361_update_rf_bandwidth (struct ad9361_rf_phy *phy, uint32_t rf_rx_bw, uint32_t rf_tx_bw)
int32_t	ad9361_calculate_rf_clock_chain (struct ad9361_rf_phy *phy, uint32_t tx_sample_rate, uint32_t rate_gov, uint32_t *rx_path_clks, uint32_t *tx_path_clks)
int32_t	ad9361_set_trx_clock_chain (struct ad9361_rf_phy *phy, uint32_t *rx_path_clks, uint32_t *tx_path_clks)
int32_t	ad9361_get_trx_clock_chain (struct ad9361_rf_phy *phy, uint32_t *rx_path_clks, uint32_t *tx_path_clks)
uint32_t	ad9361_to_clk (uint64_t freq)
uint64_t	ad9361_from_clk (uint32_t freq)
int32_t	ad9361_read_rssi (struct ad9361_rf_phy *phy, struct rf_rssi *rssi)
int32_t	ad9361_set_gain_ctrl_mode (struct ad9361_rf_phy *phy, struct rf_gain_ctrl *gain_ctrl)
int32_t	ad9361_load_fir_filter_coef (struct ad9361_rf_phy *phy, enum fir_dest dest, int32_t gain_dB, uint32_t ntaps, short *coef)
int32_t	ad9361_validate_enable_fir (struct ad9361_rf_phy *phy)
int32_t	ad9361_set_tx_atten (struct ad9361_rf_phy *phy, uint32_t atten_mdb, bool tx1, bool tx2, bool immed)
int32_t	ad9361_get_tx_atten (struct ad9361_rf_phy *phy, uint32_t tx_num)
uint32_t	ad9361_clk_factor_recalc_rate (struct refclk_scale *clk_priv, uint32_t parent_rate)
int32_t	ad9361_clk_factor_round_rate (struct refclk_scale *clk_priv, uint32_t rate, uint32_t *prate)
int32_t	ad9361_clk_factor_set_rate (struct refclk_scale *clk_priv, uint32_t rate, uint32_t parent_rate)
uint32_t	ad9361_bbpll_recalc_rate (struct refclk_scale *clk_priv, uint32_t parent_rate)
int32_t	ad9361_bbpll_round_rate (struct refclk_scale *clk_priv, uint32_t rate, uint32_t *prate)
int32_t	ad9361_bbpll_set_rate (struct refclk_scale *clk_priv, uint32_t rate, uint32_t parent_rate)
uint32_t	ad9361_rfpll_int_recalc_rate (struct refclk_scale *clk_priv, uint32_t parent_rate)
int32_t	ad9361_rfpll_int_round_rate (struct refclk_scale *clk_priv, uint32_t rate, uint32_t *prate)
int32_t	ad9361_rfpll_int_set_rate (struct refclk_scale *clk_priv, uint32_t rate, uint32_t parent_rate)
uint32_t	ad9361_rfpll_dummy_recalc_rate (struct refclk_scale *clk_priv)
int32_t	ad9361_rfpll_dummy_set_rate (struct refclk_scale *clk_priv, uint32_t rate)
uint32_t	ad9361_rfpll_recalc_rate (struct refclk_scale *clk_priv)
int32_t	ad9361_rfpll_round_rate (struct refclk_scale *clk_priv, uint32_t rate)
int32_t	ad9361_rfpll_set_rate (struct refclk_scale *clk_priv, uint32_t rate)
int32_t	ad9361_clk_mux_set_parent (struct refclk_scale *clk_priv, uint8_t index)
int32_t	ad9361_tracking_control (struct ad9361_rf_phy *phy, bool bbdc_track, bool rfdc_track, bool rxquad_track)
int32_t	ad9361_bist_loopback (struct ad9361_rf_phy *phy, int32_t mode)
void	ad9361_get_bist_loopback (struct ad9361_rf_phy *phy, int32_t *mode)
int32_t	ad9361_bist_prbs (struct ad9361_rf_phy *phy, enum ad9361_bist_mode mode)
void	ad9361_get_bist_prbs (struct ad9361_rf_phy *phy, enum ad9361_bist_mode *mode)
int32_t	ad9361_bist_tone (struct ad9361_rf_phy *phy, enum ad9361_bist_mode mode, uint32_t freq_Hz, uint32_t level_dB, uint32_t mask)
void	ad9361_get_bist_tone (struct ad9361_rf_phy *phy, enum ad9361_bist_mode *mode, uint32_t *freq_Hz, uint32_t *level_dB, uint32_t *mask)
int32_t	ad9361_rf_port_setup (struct ad9361_rf_phy *phy, bool is_out, uint32_t rx_inputs, uint32_t txb)
int32_t	ad9361_mcs (struct ad9361_rf_phy *phy, int32_t step)
int32_t	ad9361_do_calib_run (struct ad9361_rf_phy *phy, uint32_t cal, int32_t arg)
int32_t	ad9361_fastlock_store (struct ad9361_rf_phy *phy, bool tx, uint32_t profile)
int32_t	ad9361_fastlock_recall (struct ad9361_rf_phy *phy, bool tx, uint32_t profile)
int32_t	ad9361_fastlock_load (struct ad9361_rf_phy *phy, bool tx, uint32_t profile, uint8_t *values)
int32_t	ad9361_fastlock_save (struct ad9361_rf_phy *phy, bool tx, uint32_t profile, uint8_t *values)
void	ad9361_ensm_force_state (struct ad9361_rf_phy *phy, uint8_t ensm_state)
uint8_t	ad9361_ensm_get_state (struct ad9361_rf_phy *phy)
void	ad9361_ensm_restore_state (struct ad9361_rf_phy *phy, uint8_t ensm_state)
void	ad9361_ensm_restore_prev_state (struct ad9361_rf_phy *phy)
int32_t	ad9361_set_trx_clock_chain_freq (struct ad9361_rf_phy *phy, uint32_t freq)
int32_t	ad9361_find_opt (uint8_t *field, uint32_t size, uint32_t *ret_start)
int32_t	ad9361_hdl_loopback (struct ad9361_rf_phy *phy, bool enable)
int32_t	ad9361_dig_interface_timing_analysis (struct ad9361_rf_phy *phy, char *buf, int32_t buflen)
int32_t	ad9361_dig_tune (struct ad9361_rf_phy *phy, uint32_t max_freq, enum dig_tune_flags flags)
int32_t	ad9361_en_dis_tx (struct ad9361_rf_phy *phy, uint32_t tx_if, uint32_t enable)
int32_t	ad9361_en_dis_rx (struct ad9361_rf_phy *phy, uint32_t rx_if, uint32_t enable)
int32_t	ad9361_1rx1tx_channel_map (struct ad9361_rf_phy *phy, bool tx, int32_t channel)
int32_t	ad9361_rssi_gain_step_calib (struct ad9361_rf_phy *phy)
int32_t	ad9361_set_dcxo_tune (struct ad9361_rf_phy *phy, uint32_t coarse, uint32_t fine)
int32_t	ad9361_tx_mute (struct ad9361_rf_phy *phy, uint32_t state)
uint32_t	ad9361_validate_rf_bw (struct ad9361_rf_phy *phy, uint32_t bw)
int32_t	ad9361_get_temp (struct ad9361_rf_phy *phy)
int	ad9361_synth_lo_powerdown (struct ad9361_rf_phy *phy, enum synth_pd_ctrl rx, enum synth_pd_ctrl tx)
void	ad9361_clear_state (struct ad9361_rf_phy *phy)
int32_t	ad9361_get_dig_tune_data (struct ad9361_rf_phy *phy, struct ad9361_dig_tune_data *data)
int32_t	ad9361_write_clock_data_delays (struct ad9361_rf_phy *phy)
int32_t	ad9361_read_clock_data_delays (struct ad9361_rf_phy *phy)
int32_t	ad9361_write_bist_reg (struct ad9361_rf_phy *phy, uint32_t val)
int32_t	ad9361_ensm_mode_disable_pinctrl (struct ad9361_rf_phy *phy)
int32_t	ad9361_ensm_mode_restore_pinctrl (struct ad9361_rf_phy *phy)
int32_t	ad9361_rssi_program_lna_gain (struct ad9361_rf_phy *phy)
int32_t	ad9361_rssi_write_err_tbl (struct ad9361_rf_phy *phy)
int32_t	ad9361_set_cal_sw (struct ad9361_rf_phy *phy, uint32_t val)

Detailed Description

Header file of AD9361 Driver.

Copyright 2014(c) Analog Devices, Inc.

SPDX-License-Identifier: BSD-3-Clause

Macro Definition Documentation

_LSB_FIRST

#define _LSB_FIRST   (1 << 2) /* LSB First */

_SOFT_RESET

#define _SOFT_RESET   (1 << 0) /* Soft reset */

_WIRE3_SPI

#define _WIRE3_SPI   (1 << 1) /* 3-Wire SPI */

AD9363A_MAX_CARRIER_FREQ_HZ

#define AD9363A_MAX_CARRIER_FREQ_HZ   3800000000ULL

AD9363A_MIN_CARRIER_FREQ_HZ

#define AD9363A_MIN_CARRIER_FREQ_HZ   325000000ULL

AD_ADDR

#define AD_ADDR

(

x

)

Value:

((x) & 0x3FF)

AD_CNT

#define AD_CNT

(

x

)

Value:

((((x) - 1) & 0x7) << 12)

AD_READ

#define AD_READ   (0 << 15)

AD_WRITE

#define AD_WRITE   (1 << 15)

ADC_NOISE_CORRECTION_FACTOR

#define ADC_NOISE_CORRECTION_FACTOR

(

x

)

Value:

(((x) & 0x3) << 0) /* ADC Noise Correction Factor<1:0> */

ADC_OVERRANGE_SAMPLE_SIZE

#define ADC_OVERRANGE_SAMPLE_SIZE

(

x

)

Value:

(((x) & 0x7) << 0) /* ADC Overrange Sample Size<2:0> */

ADC_POWER_MEASUREMENT_DURATION_0

#define ADC_POWER_MEASUREMENT_DURATION_0

(

x

)

Value:

(((x) & 0xF) << 0) /* ADC Power Measurement Duration 0 <3:0> */

ADC_POWER_MEASUREMENT_DURATION_1

#define ADC_POWER_MEASUREMENT_DURATION_1

(

x

)

Value:

(((x) & 0xF) << 4) /* ADC Power Measurement Duration 1<3:0> */

AGC_ATTACK_DELAY

#define AGC_ATTACK_DELAY

(

x

)

Value:

(((x) & 0x3F) << 0) /* AGC Attack Delay<5:0> */

AGC_GAIN_UNLOCK_CTRL

#define AGC_GAIN_UNLOCK_CTRL   (1 << 6) /* Gain Unlock Control */

AGC_INNER_HIGH_THRESH_EXED_STP_SIZE

#define AGC_INNER_HIGH_THRESH_EXED_STP_SIZE

(

x

)

Value:

(((x) & 0x7) << 4) /* AGC Inner High Threshold Exceeded Step Size<2:0> */

AGC_INNER_LOW_THRESH

#define AGC_INNER_LOW_THRESH

(

x

)

Value:

(((x) & 0x7F) << 0) /* AGC Inner Low Threshold<6:0> */

AGC_INNER_LOW_THRESH_EXED_STP_SIZE

#define AGC_INNER_LOW_THRESH_EXED_STP_SIZE

(

x

)

Value:

(((x) & 0x7) << 0) /* AGC Inner Low Threshold Exceeded Step Size<2:0> */

AGC_LOCK_LEVEL_FAST_AGC_INNER_HIGH_THRESH_SLOW

#define AGC_LOCK_LEVEL_FAST_AGC_INNER_HIGH_THRESH_SLOW

(

x

)

Value:

(((x) & 0x7F) << 0) /* AGC Lock Level (Fast)/ AGC Inner High Threshold (Slow) <6:0> */

AGC_OUTER_HIGH_THRESH

#define AGC_OUTER_HIGH_THRESH

(

x

)

Value:

(((x) & 0xF) << 4) /* AGC Outer High Threshold<3:0> */

AGC_OUTER_HIGH_THRESH_EXED_STP_SIZE

#define AGC_OUTER_HIGH_THRESH_EXED_STP_SIZE

(

x

)

Value:

(((x) & 0xF) << 4) /* AGC outer High Threshold Exceeded Step Size<3:0> */

AGC_OUTER_LOW_THRESH

#define AGC_OUTER_LOW_THRESH

(

x

)

Value:

(((x) & 0xF) << 0) /* AGC Outer Low Threshold<3:0> */

AGC_OUTER_LOW_THRESH_EXED_STP_SIZE

#define AGC_OUTER_LOW_THRESH_EXED_STP_SIZE

(

x

)

Value:

(((x) & 0xF) << 0) /* AGC Outer Low Threshold Exceeded Step Size<3:0> */

AGC_SOFT_RESET

#define AGC_SOFT_RESET   (1 << 7) /* Soft Reset */

AGC_USE_FULL_GAIN_TABLE

#define AGC_USE_FULL_GAIN_TABLE   (1 << 3) /* Use Full Gain Table */

AGCLL_MAX_INCREASE

#define AGCLL_MAX_INCREASE

(

x

)

Value:

(((x) & 0x3F) << 0) /* AGCLL Max Increase<5:0> */

AMPBIAS

#define AMPBIAS

(

x

)

Value:

(((x) & 0x3) << 0) /* AmpBias<1:0> */

AUTO_GAIN_LOCK

#define AUTO_GAIN_LOCK   (1 << 1) /* Auto Gain Lock */

AUX_ADC_DECIMATION

#define AUX_ADC_DECIMATION

(

x

)

Value:

(((x) & 0x7) << 1) /* Aux ADC Decimation<2:0> */

AUXADC_CLOCK_DIVIDER

#define AUXADC_CLOCK_DIVIDER

(

x

)

Value:

(((x) & 0x3F) << 0) /* AuxADC Clock Divider<5:0> */

AUXADC_POWER_DOWN

#define AUXADC_POWER_DOWN   (1 << 0) /* AuxADC Power Down */

AUXADC_WORD_LSB

#define AUXADC_WORD_LSB

(

x

)

Value:

(((x) & 0xF) << 0) /* AuxADC Word LSB<3:0> */

AUXDAC1_STP_FACTOR

#define AUXDAC1_STP_FACTOR   (1 << 4) /* AuxDAC1 Step Factor */

AUXDAC2_STP_FACTOR

#define AUXDAC2_STP_FACTOR   (1 << 4) /* AuxDAC2 Step Factor */

AUXDAC_1_VREF

#define AUXDAC_1_VREF

(

x

)

Value:

(((x) & 0x3) << 2) /* AuxDAC 1 Vref<1:0> */

AUXDAC_1_WORD

#define AUXDAC_1_WORD

(

x

)

Value:

(((x) & 0x3) << 0) /* AuxDAC 1 Word <1:0> */

AUXDAC_1_WORD_LSB

#define AUXDAC_1_WORD_LSB

(

x

)

Value:

(((x) & 0x3) << 0) /* AuxDAC 2 Word <1:0> */

AUXDAC_2_VREF

#define AUXDAC_2_VREF

(

x

)

Value:

(((x) & 0xF) << 2) /* AuxDAC 2 Vref<1:0> */

AUXDAC_2_WORD_LSB

#define AUXDAC_2_WORD_LSB

(

x

)

Value:

(((x) & 0x3) << 0) /* AuxDAC 2 Word <1:0> */

AUXDAC_2_WORD_MSB

#define AUXDAC_2_WORD_MSB

(

x

)

Value:

(((x) & 0x3F) << 2) /* AuxDAC 2 Word<9:2> */

AUXDAC_AUTO_RX_BAR

#define AUXDAC_AUTO_RX_BAR

(

x

)

Value:

(((x) & 0x3) << 2) /* AuxDAC Auto Rx Bar<1:0> */

AUXDAC_AUTO_TX_BAR

#define AUXDAC_AUTO_TX_BAR

(

x

)

Value:

(((x) & 0x3) << 4) /* AuxDAC Auto Tx Bar<1:0> */

AUXDAC_INIT_BAR

#define AUXDAC_INIT_BAR

(

x

)

Value:

(((x) & 0x3) << 0) /* AuxDAC Init Bar<1:0> */

AUXDAC_MANUAL_BAR

#define AUXDAC_MANUAL_BAR

(

x

)

Value:

(((x) & 0x3) << 6) /* AuxDac Manual Bar<1:0> */

AUXDAC_MANUAL_SELECT

#define AUXDAC_MANUAL_SELECT   (1 << 7) /* AuxDAC Manual Select */

BANDGAP_REF_RESET

#define BANDGAP_REF_RESET   (1 << 5) /* Bandgap Ref Reset */

BANDGAP_TEMP_TRIM

#define BANDGAP_TEMP_TRIM

(

x

)

Value:

(((x) & 0x1F) << 0) /* Bandgap Temp Trim<4:0> */

BB_DC_M_SHIFT

#define BB_DC_M_SHIFT

(

x

)

Value:

(((x) & 0x1F) << 0) /* BB  DC M Shift<4:0> */

BB_DC_OFFSET_ATTEN

#define BB_DC_OFFSET_ATTEN

(

x

)

Value:

(((x) & 0xF) << 0) /* BB DC Offset Atten<3:0> */

BB_DC_TRACKING_FAST_SETTLE_M_SHIFT

#define BB_DC_TRACKING_FAST_SETTLE_M_SHIFT

(

x

)

Value:

(((x) & 0x1F) << 0) /* BB DC Tracking Fast Settle M Shift<4:0> */

BB_TRACKING_DECIMATE

#define BB_TRACKING_DECIMATE

(

x

)

Value:

(((x) & 0x3) << 5) /* BB Tracking Decimate<1:0> */

BBDC_CAL

#define BBDC_CAL   (1 << 0) /* DC cal BB Start */

BBF1_COMP_I

#define BBF1_COMP_I   (1 << 3) /* BBF1 Comp I */

BBF1_COMP_Q

#define BBF1_COMP_Q   (1 << 2) /* BBF1 Comp Q */

BBF2_COMP_I

#define BBF2_COMP_I   (1 << 1) /* BBF2 Comp I */

BBF2_COMP_Q

#define BBF2_COMP_Q   (1 << 0) /* BBF2 Comp Q */

BBPLL_DIVIDER

#define BBPLL_DIVIDER

(

x

)

Value:

(((x) & 0x7) << 0) /* BBPLL Divider <2:0> */

BBPLL_ENABLE

#define BBPLL_ENABLE   (1 << 0) /* BBPLL Enable */

BBPLL_LOCK

#define BBPLL_LOCK   (1 << 7) /* BBPLL Lock */

BBPLL_MODULUS

#define BBPLL_MODULUS   2088960UL

BBPLL_RESET_BAR

#define BBPLL_RESET_BAR   (1 << 0) /* BBPLL Reset Bar */

BIAS

#define BIAS

(

x

)

Value:

(((x) & 0x3) << 6) /* Bias<1:0> */

BIST_CTRL_POINT

#define BIST_CTRL_POINT

(

x

)

Value:

(((x) & 0x3) << 2) /* BIST Control Point <1:0> */

BIST_ENABLE

#define BIST_ENABLE   (1 << 0) /* BIST Enable */

BIST_MASK_CHANNEL_1_I_DATA

#define BIST_MASK_CHANNEL_1_I_DATA   (1 << 2) /* BIST Mask Channel 1 I data */

BIST_MASK_CHANNEL_1_Q_DATA

#define BIST_MASK_CHANNEL_1_Q_DATA   (1 << 3) /* BIST Mask Channel 1 Q data */

BIST_MASK_CHANNEL_2_I_DATA

#define BIST_MASK_CHANNEL_2_I_DATA   (1 << 4) /* BIST Mask Channel 2 I data */

BIST_MASK_CHANNEL_2_Q_DATA

#define BIST_MASK_CHANNEL_2_Q_DATA   (1 << 5) /* BIST Mask Channel 2 Q data */

BYPASS_BIAS_R

#define BYPASS_BIAS_R   (1 << 0) /* Bypass Bias R */

BYPASS_C3

#define BYPASS_C3   (1 << 7) /* Bypass C3 */

BYPASS_LD_SYNTH [1/2]

#define BYPASS_LD_SYNTH   (1 << 0) /* Bypass Ld Synth */

BYPASS_LD_SYNTH [2/2]

#define BYPASS_LD_SYNTH   (1 << 0) /* Bypass Ld Synth */

BYPASS_LOAD_DELAY

#define BYPASS_LOAD_DELAY   (1 << 7) /* Bypass Load Delay */

BYPASS_PRESCALE_R

#define BYPASS_PRESCALE_R   (1 << 3) /* Bypass Prescale R */

BYPASS_R2

#define BYPASS_R2   (1 << 6) /* Bypass R2 */

C1

#define C1

(

x

)

Value:

(((x) & 0x3F) << 0) /* C1<5:0> */

C1_WORD

#define C1_WORD

(

x

)

Value:

(((x) & 0x7) << 5) /* C1 Word<2:0> */

C1_WORD_LSB

#define C1_WORD_LSB

(

x

)

Value:

(((x) & 0x3) << 0) /* C1 Word<4:3> */

C2

#define C2

(

x

)

Value:

(((x) & 0x3F) << 0) /* C2<5:0> */

C2_WORD

#define C2_WORD

(

x

)

Value:

(((x) & 0x1F) << 2) /* C2 Word<4:0> */

C3_WORD

#define C3_WORD

(

x

)

Value:

(((x) & 0xF) << 2) /* C3 Word<3:0> */

CAL_CLOCK_DIV_4

#define CAL_CLOCK_DIV_4   (1 << 4) /* Cal Clock div 4 */

CALIB_TABLE_GAIN_DIFFERROR_WORD

#define CALIB_TABLE_GAIN_DIFFERROR_WORD

(

x

)

Value:

(((x) & 0x3F) << 0) /* Calib Table Gain Diff/Error Word<5:0> */

CALIB_TABLE_GAIN_ERROR

#define CALIB_TABLE_GAIN_ERROR

(

x

)

Value:

(((x) & 0x1F) << 0) /* Calib Table Gain Error<4:0> */

CALIB_TABLE_SELECT

#define CALIB_TABLE_SELECT

(

x

)

Value:

(((x) & 0x3) << 5) /* Calib Table Select<1:0> */

CALIBRATION_CONFIG2_DFLT

#define CALIBRATION_CONFIG2_DFLT   (0x3 << 5) /* Must be 2'b11 */

CALIBRATION_SEQUENCE_STATE

#define CALIBRATION_SEQUENCE_STATE

(

x

)

Value:

(((x) & 0xF) << 4) /* Calibration Sequence State<3:0> */

CAPACITOR

#define CAPACITOR

(

x

)

Value:

(((x) & 0x3F) << 0) /* Capacitor<5:0> */

CC

#define CC

(

x

)

Value:

(((x) & 0x3) << 2) /* Cc<1:0> */

CH1_HB1

#define CH1_HB1   (1 << 2) /* CH1 HB1 */

CH1_HB2

#define CH1_HB2   (1 << 4) /* CH1 HB2 */

CH1_HB3

#define CH1_HB3   (1 << 5) /* CH1 HB3 */

CH1_QEC

#define CH1_QEC   (1 << 3) /* CH1 QEC */

CH1_RFIR

#define CH1_RFIR   (1 << 0) /* CH1 RFIR */

CH1_TFIR

#define CH1_TFIR   (1 << 1) /* CH1 TFIR */

CH2_HB1

#define CH2_HB1   (1 << 2) /* CH2 HB1 */

CH2_HB2

#define CH2_HB2   (1 << 4) /* CH2 HB2 */

CH2_HB3

#define CH2_HB3   (1 << 5) /* CH2 HB3 */

CH2_INT3

#define CH2_INT3   (1 << 6) /* CH2 INT3 */

CH2_QEC

#define CH2_QEC   (1 << 3) /* CH2 QEC */

CH2_RFIR

#define CH2_RFIR   (1 << 0) /* CH2 RFIR */

CH2_TFIR

#define CH2_TFIR   (1 << 1) /* CH2 TFIR */

CH_1_INT3

#define CH_1_INT3   (1 << 6) /* CH 1 INT3 */

CHANNEL

#define CHANNEL   (1 << 5) /* Channel */

CHARGE_PUMP_CURRENT [1/3]

#define CHARGE_PUMP_CURRENT

(

x

)

Value:

(((x) & 0x3F) << 0) /* Charge Pump Current<5:0> */

CHARGE_PUMP_CURRENT [2/3]

#define CHARGE_PUMP_CURRENT

(

x

)

Value:

(((x) & 0x3F) << 0) /* Charge Pump Current<5:0> */

CHARGE_PUMP_CURRENT [3/3]

#define CHARGE_PUMP_CURRENT

(

x

)

Value:

(((x) & 0x3F) << 0) /* Charge Pump Current<5:0> */

CHARGE_PUMP_OFFSET

#define CHARGE_PUMP_OFFSET

(

x

)

Value:

(((x) & 0x3F) << 0) /* Charge Pump Offset<5:0> */

CLK_OUT_DRIVE

#define CLK_OUT_DRIVE   (1 << 7) /* CLK Out Drive */

CLK_OUT_SLEW

#define CLK_OUT_SLEW

(

x

)

Value:

(((x) & 0x3) << 6) /* CLK Out Slew<1:0> */

CLKOUT_ENABLE

#define CLKOUT_ENABLE   (1 << 4) /* CLKOUT Enable */

CLKOUT_SELECT

#define CLKOUT_SELECT

(

x

)

Value:

(((x) & 0x7) << 5) /* CLKOUT  Select<2:0> */

CLOCK_ENABLE_DFLT

#define CLOCK_ENABLE_DFLT   (1 << 1) /* Set to 1 */

COMP_CTRL_1

#define COMP_CTRL_1   (1 << 5) /* Comp Ctrl 1 */

COMP_CTRL_2

#define COMP_CTRL_2   (1 << 5) /* Comp Ctrl 2 */

COMP_OUT

#define COMP_OUT   (1 << 6) /* Comp Out */

CORRECTION_WORD_DECIMATION_M

#define CORRECTION_WORD_DECIMATION_M

(

x

)

Value:

(((x) & 0x7) << 5) /* Correction Word Decimation M<2:0> */

CP

#define CP

(

x

)

Value:

(((x) & 0x3F) << 0) /* Cp<5:0> */

CP_CAL_DONE [1/2]

#define CP_CAL_DONE   (1 << 5) /* CP Cal Done */

CP_CAL_DONE [2/2]

#define CP_CAL_DONE   (1 << 5) /* CP Cal Done */

CP_CAL_ENABLE [1/2]

#define CP_CAL_ENABLE   (1 << 2) /* Cp Cal Enable */

CP_CAL_ENABLE [2/2]

#define CP_CAL_ENABLE   (1 << 2) /* Cp Cal Enable */

CP_CAL_VALID [1/2]

#define CP_CAL_VALID   (1 << 7) /* CP Cal Valid */

CP_CAL_VALID [2/2]

#define CP_CAL_VALID   (1 << 7) /* CP Cal Valid */

CP_CAL_WORD [1/2]

#define CP_CAL_WORD

(

x

)

Value:

(((x) & 0xF) << 0) /* CP Cal Word<3:0> */

CP_CAL_WORD [2/2]

#define CP_CAL_WORD

(

x

)

Value:

(((x) & 0xF) << 0) /* CP Cal Word<3:0> */

CP_LEVEL_DETECT_POWER_DOWN [1/2]

#define CP_LEVEL_DETECT_POWER_DOWN   (1 << 6) /* CP Level Detect Power Down */

CP_LEVEL_DETECT_POWER_DOWN [2/2]

#define CP_LEVEL_DETECT_POWER_DOWN   (1 << 6) /* CP Level Detect Power Down */

CP_LEVEL_DETECT_THRESH_HIGH

#define CP_LEVEL_DETECT_THRESH_HIGH

(

x

)

Value:

(((x) & 0x7) << 0) /* CP Level Detect Threshold High<2:0> */

CP_LEVEL_DETECT_THRESH_LOW

#define CP_LEVEL_DETECT_THRESH_LOW

(

x

)

Value:

(((x) & 0x7) << 3) /* CP Level Detect Threshold Low<2:0> */

CP_LEVEL_THRESH_HIGH

#define CP_LEVEL_THRESH_HIGH

(

x

)

Value:

(((x) & 0x7) << 0) /* CP Level Threshold High<2:0> */

CP_LEVEL_THRESH_LOW

#define CP_LEVEL_THRESH_LOW

(

x

)

Value:

(((x) & 0x7) << 3) /* CP Level Threshold Low<2:0> */

CP_OFFSET_OFF [1/2]

#define CP_OFFSET_OFF   (1 << 4) /* CP Offset Off */

CP_OFFSET_OFF [2/2]

#define CP_OFFSET_OFF   (1 << 4) /* Cp Offset Off */

CP_OVRG_HIGH [1/2]

#define CP_OVRG_HIGH   (1 << 7) /* CP Ovrg High */

CP_OVRG_HIGH [2/2]

#define CP_OVRG_HIGH   (1 << 7) /* CP Ovrg High */

CP_OVRG_LOW [1/2]

#define CP_OVRG_LOW   (1 << 6) /* CP Ovrg Low */

CP_OVRG_LOW [2/2]

#define CP_OVRG_LOW   (1 << 6) /* CP Ovrg Low */

CP_TEST

#define CP_TEST

(

x

)

Value:

(((x) & 0x3) << 0) /* Cp Test <1:0> */

CTRL_ENABLE

#define CTRL_ENABLE   (1 << 0) /* Set to 1 */

DAC_CLK_DIV2

#define DAC_CLK_DIV2   (1 << 3) /* DAC Clk div2 */

DAC_FS

#define DAC_FS

(

x

)

Value:

(((x) & 0x3) << 4) /* DAC FS<1:0> */

DAC_TEST_ENABLE

#define DAC_TEST_ENABLE   (1 << 7) /* DAC Test Enable */

DAC_TEST_WORD

#define DAC_TEST_WORD

(

x

)

Value:

(((x) & 0x7F) << 0) /* DAC test Word <22:16> */

DATA_CLK_DELAY

#define DATA_CLK_DELAY

(

x

)

Value:

(((x) & 0xF) << 4) /* DATA_CLK Delay<3:0> */

DATA_PORT_DRIVE

#define DATA_PORT_DRIVE   (1 << 2) /* Data Port Drive */

DATA_PORT_HILOW

#define DATA_PORT_HILOW   (1 << 1) /* Data Port Hi/Low */

DATA_PORT_LOOP_TEST_ENABLE

#define DATA_PORT_LOOP_TEST_ENABLE   (1 << 0) /* Data Port Loop Test Enable */

DATA_PORT_SLEW

#define DATA_PORT_SLEW

(

x

)

Value:

(((x) & 0x3) << 0) /* Data Port Slew<1:0> */

DATA_PORT_SP_HD_LOOP_TEST_OE

#define DATA_PORT_SP_HD_LOOP_TEST_OE   (1 << 7) /* Data Port SP, HD Loop Test OE */

DATACLK_DRIVE

#define DATACLK_DRIVE   (1 << 6) /* DATACLK drive */

DATACLK_SLEW

#define DATACLK_SLEW

(

x

)

Value:

(((x) & 0x3) << 4) /* DATACLK slew <1:0> */

DB_GAIN_READBACK_CHANNEL

#define DB_GAIN_READBACK_CHANNEL   (1 << 0) /* dB Gain Read-back Channel */

DC_OFFSET_ENABLE

#define DC_OFFSET_ENABLE   (1 << 5) /* DC Offset Enable */

DC_OFFSET_UPDATE

#define DC_OFFSET_UPDATE

(

x

)

Value:

(((x) & 0x7) << 0) /* DC Offset Update<2:0> */

DCXO_POWER_DOWN

#define DCXO_POWER_DOWN   (1 << 1) /* DCXO Power Down */

DCXO_RD

#define DCXO_RD

(

x

)

Value:

(((x) & 0x3) << 2) /* DCXO Rd<1:0> */

DCXO_RTAIL

#define DCXO_RTAIL

(

x

)

Value:

(((x) & 0x7) << 4) /* DCXO Rtail<2:0> */

DCXO_TEMPCO_CLK

#define DCXO_TEMPCO_CLK   (1 << 6) /* DCXO Tempco Clk */

DCXO_TEMPCO_EN

#define DCXO_TEMPCO_EN   (1 << 7) /* DCXO Tempco En */

DCXO_TEMPERATURE_COEF_ADDRESS

#define DCXO_TEMPERATURE_COEF_ADDRESS

(

x

)

Value:

(((x) & 0x3F) << 0) /* DCXO Temperature Coefficient Address<5:0> */

DCXO_TUNE_COARSE

#define DCXO_TUNE_COARSE

(

x

)

Value:

(((x) & 0x3F) << 0) /* DCXO Tune Coarse<5:0> */

DCXO_TUNE_FINE_HIGH

#define DCXO_TUNE_FINE_HIGH

(

x

)

Value:

((x) >> 5) /* DCXO Tune Fine<12:5> */

DCXO_TUNE_FINE_LOW

#define DCXO_TUNE_FINE_LOW

(

x

)

Value:

(((x) & 0x1F) << 3) /* DCXO Tune Fine<4:0> */

DEC3_ENABLE_DECIMATION

#define DEC3_ENABLE_DECIMATION

(

x

)

Value:

(((x) & 0x3) << 4) /* DEC3 Enable & Decimation<1:0> */

DEC_POWER_MEASUREMENT_DURATION

#define DEC_POWER_MEASUREMENT_DURATION

(

x

)

Value:

(((x) & 0xF) << 0) /* Dec Power Measurement Duration <3:0> */

DEC_PWR_FOR_GAIN_LOCK_EXIT

#define DEC_PWR_FOR_GAIN_LOCK_EXIT   (1 << 5) /* Dec Pwr for Gain Lock Exit */

DEC_PWR_FOR_LOCK_LEVEL

#define DEC_PWR_FOR_LOCK_LEVEL   (1 << 6) /* Dec Pwr for Lock Level */

DEC_PWR_FOR_LOW_PWR

#define DEC_PWR_FOR_LOW_PWR   (1 << 7) /* Dec Pwr for Low Pwr */

DEC_STP_SIZE_FOR_LARGE_LMT_OVERLOAD

#define DEC_STP_SIZE_FOR_LARGE_LMT_OVERLOAD

(

x

)

Value:

(((x) & 0x7) << 2) /* Dec Step Size for: Large LMT Overload/ Full Table Case #3 <2:0> */

DECREMENT_STP_SIZE_FOR_SMALL_LPF_GAIN_CHANGE

#define DECREMENT_STP_SIZE_FOR_SMALL_LPF_GAIN_CHANGE

(

x

)

Value:

(((x) & 0x7) << 4) /* Fast Attack Only. Decrement Step Size for: Small LPF Gain Change / Full Table Case #2 <2:0> */

DEFAULT_MODE_ADC_POWER

#define DEFAULT_MODE_ADC_POWER   (1 << 4) /* Default Mode ADC Power */

DEFAULT_RSSI_MEAS_MODE

#define DEFAULT_RSSI_MEAS_MODE   (1 << 0) /* Default RSSI Meas Mode */

DELAY_RX_DATA

#define DELAY_RX_DATA

(

x

)

Value:

(((x) & 0x3) << 0) /* Delay Rx Data<1:0> */

DIG_GAIN_EN

#define DIG_GAIN_EN   (1 << 2) /* Enable Digital Gain */

DIG_GAIN_STP_SIZE

#define DIG_GAIN_STP_SIZE

(

x

)

Value:

(((x) & 0x7) << 5) /* Dig Gain Step Size<2:0> */

DIG_SAT

#define DIG_SAT   (1 << 0) /* Dig Sat */

DIG_SATURATION_EXED_COUNTER

#define DIG_SATURATION_EXED_COUNTER

(

x

)

Value:

(((x) & 0xF) << 0) /* Dig Saturation Exceeded Counter<3:0> */

DIGITAL_GAIN

#define DIGITAL_GAIN

(

x

)

Value:

(((x) & 0x1F) << 0) /* Digital Gain <4:0> */

DIGITAL_GAIN_RX

#define DIGITAL_GAIN_RX

(

x

)

Value:

(((x) & 0x1F) << 0) /* Digital gain Rx1<4:0> */

DIGITAL_POWER_UP

#define DIGITAL_POWER_UP   (1 << 2) /* Digital Power Up */

DITHER_MODE

#define DITHER_MODE   (1 << 6) /* Dither Mode */

DIV_TEST_EN

#define DIV_TEST_EN   (1 << 5) /* Div Test En */

DONT_UNLOCK_GAIN_IF_ADC_OVRG

#define DONT_UNLOCK_GAIN_IF_ADC_OVRG   (1 << 7) /* Don't unlock gain if ADC Ovrg */

DONT_UNLOCK_GAIN_IF_ENERGY_LOST

#define DONT_UNLOCK_GAIN_IF_ENERGY_LOST   (1 << 3) /* Don't Unlock Gain if Energy Lost */

DONT_UNLOCK_GAIN_IF_LG_ADC_OR_LMT_OVRG

#define DONT_UNLOCK_GAIN_IF_LG_ADC_OR_LMT_OVRG   (1 << 1) /* Don't Unlock Gain If Lg ADC or LMT Ovrg */

DONT_UNLOCK_GAIN_IF_STRONGER_SIGNAL

#define DONT_UNLOCK_GAIN_IF_STRONGER_SIGNAL   (1 << 7) /* Don't unlock gain if Stronger Signal */

DOUBLE_GAIN_COUNTER

#define DOUBLE_GAIN_COUNTER   (1 << 5) /* Double Gain Counter */

DSM_PROG [1/2]

#define DSM_PROG

(

x

)

Value:

(((x) & 0xF) << 0) /* DSM Prog<3:0> */

DSM_PROG [2/2]

#define DSM_PROG

(

x

)

Value:

(((x) & 0xF) << 0) /* DSM Prog<3:0> */

DUAL_SYNTH_MODE

#define DUAL_SYNTH_MODE   (1 << 2) /* Dual Synth Mode */

EN_CTRL0

#define EN_CTRL0   (1 << 0) /* En ctrl0 */

EN_CTRL1

#define EN_CTRL1   (1 << 1) /* En ctrl1 */

EN_CTRL2

#define EN_CTRL2   (1 << 2) /* En ctrl2 */

EN_CTRL3

#define EN_CTRL3   (1 << 3) /* En ctrl3 */

EN_CTRL4

#define EN_CTRL4   (1 << 4) /* En ctrl4 */

EN_CTRL5

#define EN_CTRL5   (1 << 5) /* En ctrl5 */

EN_CTRL6

#define EN_CTRL6   (1 << 6) /* En ctrl6 */

EN_CTRL7

#define EN_CTRL7   (1 << 7) /* En ctrl7 */

ENABLE_ADC_POWER_MEAS

#define ENABLE_ADC_POWER_MEAS   (1 << 1) /* Enable ADC Power Meas. */

ENABLE_BB_DC_OFFSET_TRACKING

#define ENABLE_BB_DC_OFFSET_TRACKING   (1 << 5) /* Enable BB DC Offset Tracking */

ENABLE_CORR_WORD_DECIMATION

#define ENABLE_CORR_WORD_DECIMATION   (1 << 2) /* Enable Corr Word Decimation */

ENABLE_DEC_PWR_MEAS

#define ENABLE_DEC_PWR_MEAS   (1 << 5) /* Enable Dec Pwr Meas */

ENABLE_DIG_GAIN_CORR

#define ENABLE_DIG_GAIN_CORR   (1 << 7) /* Enable Dig Gain Corr */

ENABLE_DIG_SAT_OVRG

#define ENABLE_DIG_SAT_OVRG   (1 << 7) /* Enable Dig Sat Ovrg */

ENABLE_ENSM_PIN_CTRL

#define ENABLE_ENSM_PIN_CTRL   (1 << 4) /* Enable ENSM Pin Control */

ENABLE_FAST_SETTLE_MODE

#define ENABLE_FAST_SETTLE_MODE   (1 << 6) /* Enable Fast Settle Mode */

ENABLE_GAIN_CORR

#define ENABLE_GAIN_CORR   (1 << 6) /* Enable Gain Corr */

ENABLE_GAIN_INC_AFTER_GAIN_LOCK

#define ENABLE_GAIN_INC_AFTER_GAIN_LOCK   (1 << 7) /* Enable Gain Inc after Gain Lock */

ENABLE_INCR_GAIN

#define ENABLE_INCR_GAIN   (1 << 0) /* Enable Incr Gain */

ENABLE_LMT_GAIN_INC_FOR_LOCK_LEVEL

#define ENABLE_LMT_GAIN_INC_FOR_LOCK_LEVEL   (1 << 6) /* Enable LMT Gain Inc for Lock Level */

ENABLE_PHASE_CORR

#define ENABLE_PHASE_CORR   (1 << 7) /* Enable Phase Corr */

ENABLE_RF_OFFSET_TRACKING

#define ENABLE_RF_OFFSET_TRACKING   (1 << 3) /* Enable RF Offset Tracking */

ENABLE_RX_DATA_PORT_FOR_CAL

#define ENABLE_RX_DATA_PORT_FOR_CAL   (1 << 7) /* Enable Rx Data Port for Cal */

ENABLE_SYMBOL_ATTEN

#define ENABLE_SYMBOL_ATTEN   (1 << 0) /* Enable Symbol Atten */

ENABLE_SYNC_FOR_GAIN_COUNTER

#define ENABLE_SYNC_FOR_GAIN_COUNTER   (1 << 4) /* Enable Sync for Gain Counter */

ENABLE_TRACKING_MODE_CH1

#define ENABLE_TRACKING_MODE_CH1   (1 << 0) /* Enable Tracking Mode CH1 */

ENABLE_TRACKING_MODE_CH2

#define ENABLE_TRACKING_MODE_CH2   (1 << 1) /* Enable Tracking Mode CH2 */

ENERGY_DETECT_COUNT

#define ENERGY_DETECT_COUNT

(

x

)

Value:

(((x) & 0x1F) << 0) /* Energy Detect count<4:0> */

ENERGY_LOST_THRESH

#define ENERGY_LOST_THRESH

(

x

)

Value:

(((x) & 0x3F) << 0) /* Energy lost threshold<5:0> */

ENSM_STATE

#define ENSM_STATE

(

x

)

Value:

(((x) & 0xF) << 0) /* ENSM State<3:0> */

ENSM_STATE_ALERT

#define ENSM_STATE_ALERT   0x5

ENSM_STATE_FDD

#define ENSM_STATE_FDD   0xA

ENSM_STATE_FDD_FLUSH

#define ENSM_STATE_FDD_FLUSH   0xB

ENSM_STATE_INVALID

#define ENSM_STATE_INVALID   0xFF

ENSM_STATE_RX

#define ENSM_STATE_RX   0x8

ENSM_STATE_RX_FLUSH

#define ENSM_STATE_RX_FLUSH   0x9

ENSM_STATE_SLEEP

#define ENSM_STATE_SLEEP   0x80

ENSM_STATE_SLEEP_WAIT

#define ENSM_STATE_SLEEP_WAIT   0x0

ENSM_STATE_TX

#define ENSM_STATE_TX   0x6

ENSM_STATE_TX_FLUSH

#define ENSM_STATE_TX_FLUSH   0x7

EVALTIME

#define EVALTIME   (1 << 4) /* EvalTime */

EXT_LNA_CTRL

#define EXT_LNA_CTRL   (1 << 7) /* Ext LNA Ctrl */

EXT_LNA_HIGH_GAIN

#define EXT_LNA_HIGH_GAIN

(

x

)

Value:

(((x) & 0x3F) << 0) /* Ext LNA High Gain<5:0> */

EXT_LNA_LOW_GAIN

#define EXT_LNA_LOW_GAIN

(

x

)

Value:

(((x) & 0x3F) << 0) /* Ext LNA Low Gain<5:0> */

EXTERNAL_LNA1_CTRL

#define EXTERNAL_LNA1_CTRL   (1 << 5) /* External LNA1 control */

EXTERNAL_LNA2_CTRL

#define EXTERNAL_LNA2_CTRL   (1 << 6) /* External LNA2 control */

F_CPCAL [1/2]

#define F_CPCAL   (1 << 3) /* F Cpcal */

F_CPCAL [2/2]

#define F_CPCAL   (1 << 3) /* F Cpcal */

FAST_ATK_FINAL_OVER

#define FAST_ATK_FINAL_OVER   4

FAST_ATK_FINAL_SETTELING

#define FAST_ATK_FINAL_SETTELING   3

FAST_ATK_GAIN_LOCKED

#define FAST_ATK_GAIN_LOCKED   5

FAST_ATK_MASK

#define FAST_ATK_MASK   0x7

FAST_ATK_PEAK_DETECT

#define FAST_ATK_PEAK_DETECT   1

FAST_ATK_PWR_MEASURE

#define FAST_ATK_PWR_MEASURE   2

FAST_ATK_RESET

#define FAST_ATK_RESET   0

FAST_ATTACK_STATE_RX1

#define FAST_ATTACK_STATE_RX1

(

x

)

Value:

(((x) & 0x7) << 0) /* Fast Attack State Rx1<2:0> */

FAST_ATTACK_STATE_RX2

#define FAST_ATTACK_STATE_RX2

(

x

)

Value:

(((x) & 0x7) << 4) /* Fast Attack State Rx2<2:0> */

FASTLOOK_INIT

#define FASTLOOK_INIT   1

FB_CLK_DELAY

#define FB_CLK_DELAY

(

x

)

Value:

(((x) & 0xF) << 4) /* FB_CLK Delay<3:0> */

FB_CLOCK_ADV

#define FB_CLOCK_ADV

(

x

)

Value:

(((x) & 0x3) << 0) /* FB Clock Adv<1:0> */

FDD_ALT_WORD_ORDER

#define FDD_ALT_WORD_ORDER   (1 << 7) /* FDD Alt Word Order */

FDD_EXTERNAL_CTRL_ENABLE

#define FDD_EXTERNAL_CTRL_ENABLE   (1 << 7) /* FDD External Control Enable */

FDD_MODE

#define FDD_MODE   (1 << 0) /* FDD Mode */

FDD_RX_RATE_2TX_RATE

#define FDD_RX_RATE_2TX_RATE   (1 << 7) /* FDD Rx Rate = 2*Tx Rate */

FILTER_GAIN

#define FILTER_GAIN

(

x

)

Value:

(((x) & 0x3) << 0) /* Filter gain<1:0> */

FINAL_OVER_RANGE_COUNT

#define FINAL_OVER_RANGE_COUNT

(

x

)

Value:

(((x) & 0x7) << 5) /* Final Over Range Count<2:0> */

FIR_NUM_TAPS

#define FIR_NUM_TAPS

(

x

)

Value:

(((x) & 0x7) << 5) /* Number of Taps<2:0> */

FIR_SELECT

#define FIR_SELECT

(

x

)

Value:

(((x) & 0x3) << 3) /* Select Tx/Rx CH<1:0> */

FIR_START_CLK

#define FIR_START_CLK   (1 << 1) /* Start Tx/Rx Clock */

FIR_WRITE

#define FIR_WRITE   (1 << 2) /* Write Tx/Rx */

FIXED_DC_CAL_WAIT_TIME

#define FIXED_DC_CAL_WAIT_TIME   (1 << 4) /* Fixed DC Cal Wait Time */

FORCE_ALC_ENABLE

#define FORCE_ALC_ENABLE   (1 << 7) /* Force ALC Enable */

FORCE_ALC_WORD

#define FORCE_ALC_WORD

(

x

)

Value:

(((x) & 0x7F) << 0) /* Force ALC Word<6:0> */

FORCE_ALERT_STATE

#define FORCE_ALERT_STATE   (1 << 2) /* Force Alert State */

FORCE_CGIN_DAC

#define FORCE_CGIN_DAC   (1 << 2) /* Force CGin DAC */

FORCE_OUT_1_TX1_OFFSET

#define FORCE_OUT_1_TX1_OFFSET   (1 << 2) /* Force Out 1 Tx1 Offset */

FORCE_OUT_1_TX1_PHASE_GAIN

#define FORCE_OUT_1_TX1_PHASE_GAIN   (1 << 0) /* Force Out 1 Tx1 Phase & Gain */

FORCE_OUT_1_TX2_OFFSET

#define FORCE_OUT_1_TX2_OFFSET   (1 << 3) /* Force Out 1 Tx2 Offset */

FORCE_OUT_1_TX2_PHASE_GAIN

#define FORCE_OUT_1_TX2_PHASE_GAIN   (1 << 1) /* Force Out 1 Tx2 Phase & Gain */

FORCE_OUT_2_TX1_OFFSET

#define FORCE_OUT_2_TX1_OFFSET   (1 << 6) /* Force Out 2 Tx1 Offset */

FORCE_OUT_2_TX1_PHASE_GAIN

#define FORCE_OUT_2_TX1_PHASE_GAIN   (1 << 4) /* Force Out 2 Tx1 Phase & Gain */

FORCE_OUT_2_TX2_OFFSET

#define FORCE_OUT_2_TX2_OFFSET   (1 << 7) /* Force Out 2 Tx2 Offset */

FORCE_OUT_2_TX2_PHASE_GAIN

#define FORCE_OUT_2_TX2_PHASE_GAIN   (1 << 5) /* Force Out 2 Tx2 Phase & Gain */

FORCE_PD_RESET_RX1

#define FORCE_PD_RESET_RX1   (1 << 6) /* Force PD Reset Rx1 */

FORCE_PD_RESET_RX2

#define FORCE_PD_RESET_RX2   (1 << 7) /* Force PD Reset Rx2 */

FORCE_RX1_DIGITAL_GAIN

#define FORCE_RX1_DIGITAL_GAIN   (1 << 5) /* Force Rx1 Digital Gain */

FORCE_RX1_LNA_GAIN

#define FORCE_RX1_LNA_GAIN   (1 << 3) /* Force Rx1 LNA Gain */

FORCE_RX1_MIX_GM

#define FORCE_RX1_MIX_GM   (1 << 6) /* Force Rx1 Mix Gm */

FORCE_RX1_RESISTORS

#define FORCE_RX1_RESISTORS   (1 << 7) /* Force Rx1 Resistors */

FORCE_RX2_DIGITAL_GAIN

#define FORCE_RX2_DIGITAL_GAIN   (1 << 5) /* Force Rx2 Digital Gain */

FORCE_RX2_LNA_GAIN

#define FORCE_RX2_LNA_GAIN   (1 << 7) /* Force Rx2 LNA Gain */

FORCE_RX2_MIX_GM

#define FORCE_RX2_MIX_GM   (1 << 6) /* Force Rx2 Mix Gm */

FORCE_RX2_RESISTORS

#define FORCE_RX2_RESISTORS   (1 << 7) /* Force Rx2 Resistors */

FORCE_RX_NULL

#define FORCE_RX_NULL   (1 << 5) /* Force Rx Null */

FORCE_RX_ON

#define FORCE_RX_ON   (1 << 6) /* Force Rx On */

FORCE_TEMP_SENSOR_FOR_CAL

#define FORCE_TEMP_SENSOR_FOR_CAL   (1 << 6) /* Force Temp Sensor for Cal */

FORCE_TX_ON

#define FORCE_TX_ON   (1 << 5) /* Force Tx On */

FORCE_VCO_TUNE

#define FORCE_VCO_TUNE   (1 << 0) /* Force VCO Tune */

FORCE_VCO_TUNE_ENABLE

#define FORCE_VCO_TUNE_ENABLE   (1 << 1) /* Force VCO Tune Enable */

FORCED_CP_CAL_WORD [1/2]

#define FORCED_CP_CAL_WORD

(

x

)

Value:

(((x) & 0xF) << 0) /* Forced CP Cal Word<3:0> */

FORCED_CP_CAL_WORD [2/2]

#define FORCED_CP_CAL_WORD

(

x

)

Value:

(((x) & 0xF) << 0) /* Forced CP Cal Word<3:0> */

FREE_RUN_ENABLE

#define FREE_RUN_ENABLE   (1 << 7) /* Free Run Enable */

FREE_RUN_MODE

#define FREE_RUN_MODE   (1 << 3) /* Free Run Mode */

FREQ_CAL_COUNT_LENGTH

#define FREQ_CAL_COUNT_LENGTH

(

x

)

Value:

(((x) & 0x3) << 5) /* Freq Cal Count Length<1:0> */

FREQ_CAL_ENABLE

#define FREQ_CAL_ENABLE   (1 << 7) /* Freq Cal Enable */

FREQ_CAL_RESET

#define FREQ_CAL_RESET   (1 << 4) /* Freq Cal Reset */

FREQ_CORRECTION_WORD_LSB [1/2]

#define FREQ_CORRECTION_WORD_LSB

(

x

)

Value:

(((x) & 0x7F) << 0) /* Frequency Correction Word<6:0> */

FREQ_CORRECTION_WORD_LSB [2/2]

#define FREQ_CORRECTION_WORD_LSB

(

x

)

Value:

(((x) & 0x7F) << 0) /* Frequency Correction Word<6:0> */

FREQ_CORRECTION_WORD_MSB [1/2]

#define FREQ_CORRECTION_WORD_MSB

(

x

)

Value:

(((x) & 0x1F) << 0) /* Frequency Correction Word<11:7> */

FREQ_CORRECTION_WORD_MSB [2/2]

#define FREQ_CORRECTION_WORD_MSB

(

x

)

Value:

(((x) & 0x1F) << 0) /* Frequency Correction Word<11:7> */

FULL_DUPLEX_SWAP_BITS

#define FULL_DUPLEX_SWAP_BITS   (1 << 0) /* Full Duplex Swap Bits */

FULL_PORT

#define FULL_PORT   (1 << 1) /* Full Port */

FULL_TABLE_GAIN_INDEX

#define FULL_TABLE_GAIN_INDEX

(

x

)

Value:

(((x) & 0x7F) << 0) /* Full Table Gain Index Rx1/LMT Gain Rx1<6:0> */

GAIN_CAL_MEAS_DURATION

#define GAIN_CAL_MEAS_DURATION

(

x

)

Value:

(((x) & 0xF) << 0) /* Gain Cal Meas Duration<3:0> */

GAIN_ENABLE

#define GAIN_ENABLE   (1 << 4) /* Gain Enable */

GAIN_LOCK_1

#define GAIN_LOCK_1   (1 << 6) /* Gain Lock 1 */

GAIN_LOCK_EXIT_COUNT

#define GAIN_LOCK_EXIT_COUNT

(

x

)

Value:

(((x) & 0x3F) << 0) /* Gain Lock Exit Count<5:0> */

GAIN_TABLE_ADDRESS

#define GAIN_TABLE_ADDRESS

(

x

)

Value:

(((x) & 0x7F) << 0) /* Gain Table Address<6:0> */

GM_STAGE_LOWER_CM

#define GM_STAGE_LOWER_CM   (1 << 3) /* Gm Stage Lower CM */

GM_STAGE_MV_HP_POLE

#define GM_STAGE_MV_HP_POLE   (1 << 4) /* Gm Stage MV HP Pole */

GM_STAGE_TIME_CON_OVERRIDE

#define GM_STAGE_TIME_CON_OVERRIDE   (1 << 5) /* Gm Stage Time Con Override */

GM_SUB_TABLE_BIAS_READ

#define GM_SUB_TABLE_BIAS_READ

(

x

)

Value:

(((x) & 0x1F) << 0) /* Gm Sub Table Bias Word Read<4:0> */

GM_SUB_TABLE_BIAS_WRITE

#define GM_SUB_TABLE_BIAS_WRITE

(

x

)

Value:

(((x) & 0x1F) << 0) /* Gm Sub Table Bias Word Write<4:0> */

GM_SUB_TABLE_CTRL_READ

#define GM_SUB_TABLE_CTRL_READ

(

x

)

Value:

(((x) & 0x3F) << 0) /* Gm Sub Table Control Word Read<5:0> */

GM_SUB_TABLE_CTRL_WRITE

#define GM_SUB_TABLE_CTRL_WRITE

(

x

)

Value:

(((x) & 0x3F) << 0) /* Gm Sub Table Control Word Write<5:0> */

GM_SUB_TABLE_GAIN_READ

#define GM_SUB_TABLE_GAIN_READ

(

x

)

Value:

(((x) & 0x7F) << 0) /* Gm Sub Table Gain Word Read<6:0> */

GM_SUB_TABLE_GAIN_WRITE

#define GM_SUB_TABLE_GAIN_WRITE

(

x

)

Value:

(((x) & 0x7F) << 0) /* Gm Sub Table Gain Word Write<6:0> */

GOTO_MAX_GAIN_OR_OPT_GAIN_IF_EN_AGC_HIGH

#define GOTO_MAX_GAIN_OR_OPT_GAIN_IF_EN_AGC_HIGH   (1 << 5) /* Goto Max Gain or Opt Gain if EN_AGC High */

GOTO_OPT_GAIN_IF_ENERGY_LOST_OR_EN_AGC_HIGH

#define GOTO_OPT_GAIN_IF_ENERGY_LOST_OR_EN_AGC_HIGH   (1 << 6) /* Goto Opt Gain if Energy Lost or EN_AGC High */

GOTO_OPTIMIZED_GAIN_IF_EXIT_RX_STATE

#define GOTO_OPTIMIZED_GAIN_IF_EXIT_RX_STATE   (1 << 2) /* Goto Optimized Gain if Exit Rx State */

GOTO_SET_GAIN_IF_EN_AGC_HIGH

#define GOTO_SET_GAIN_IF_EN_AGC_HIGH   (1 << 5) /* Goto Set Gain if EN_AGC High */

GOTO_SET_GAIN_IF_EXIT_RX_STATE

#define GOTO_SET_GAIN_IF_EXIT_RX_STATE   (1 << 4) /* Goto Set Gain if Exit Rx State */

GPO_ENABLE_AUTO_RX

#define GPO_ENABLE_AUTO_RX

(

x

)

Value:

(((x) & 0xF) << 4) /* GPO Enable Auto Rx<3:0> */

GPO_ENABLE_AUTO_TX

#define GPO_ENABLE_AUTO_TX

(

x

)

Value:

(((x) & 0xF) << 0) /* GPO Enable Auto Tx<3:0> */

GPO_INIT_STATE

#define GPO_INIT_STATE

(

x

)

Value:

(((x) & 0xF) << 0) /* GPO Init State<3:0> */

GPO_MANUAL_CTRL

#define GPO_MANUAL_CTRL

(

x

)

Value:

(((x) & 0xF) << 4) /* GPO Manual Control<3:0> */

GPO_MANUAL_SELECT

#define GPO_MANUAL_SELECT   (1 << 4) /* GPO manual select */

GT_RX1

#define GT_RX1   1

GT_RX2

#define GT_RX2   2

HALF_DUPLEX_MODE

#define HALF_DUPLEX_MODE   (1 << 3) /* Half Duplex Mode */

HALF_VCO_CAL_CLK [1/2]

#define HALF_VCO_CAL_CLK   (1 << 7) /* Half Vco Cal Clk */

HALF_VCO_CAL_CLK [2/2]

#define HALF_VCO_CAL_CLK   (1 << 7) /* Half Vco Cal Clk */

IMMED_GAIN_CHANGE_IF_LG_ADC_OVERLOAD

#define IMMED_GAIN_CHANGE_IF_LG_ADC_OVERLOAD   (1 << 3) /* Immed. Gain Change if Lg ADC Overload */

IMMED_GAIN_CHANGE_IF_LG_LMT_OVERLOAD

#define IMMED_GAIN_CHANGE_IF_LG_LMT_OVERLOAD   (1 << 7) /* Immed. Gain Change if Lg LMT Overload */

IMMEDIATELY_UPDATE_TPC_ATTEN

#define IMMEDIATELY_UPDATE_TPC_ATTEN   (1 << 6) /* Immediately Update TPC Atten */

INCDEC_LMT_GAIN

#define INCDEC_LMT_GAIN   (1 << 4) /* Inc/Dec LMT Gain */

INCREASE_COUNT_DURATION

#define INCREASE_COUNT_DURATION   (1 << 7) /* Increase Count Duration */

INCREMENT_GAIN_STP_LPFLMT

#define INCREMENT_GAIN_STP_LPFLMT

(

x

)

Value:

(((x) & 0x7) << 5) /* Increment Gain Step (LPF/LMT)<2:0> */

INIT_ALC_VALUE [1/2]

#define INIT_ALC_VALUE

(

x

)

Value:

(((x) & 0xF) << 4) /* Init ALC Value<3:0> */

INIT_ALC_VALUE [2/2]

#define INIT_ALC_VALUE

(

x

)

Value:

(((x) & 0xF) << 4) /* Init ALC Value<3:0> */

INIT_BB_FO_CAL

#define INIT_BB_FO_CAL   (1 << 2) /* Init BB FO CAL */

INITIAL_LMT_GAIN_LIMIT

#define INITIAL_LMT_GAIN_LIMIT

(

x

)

Value:

(((x) & 0x7F) << 0) /* Initial LMT Gain Limit<6:0> */

INPUT_A_RX1_I

#define INPUT_A_RX1_I

(

x

)

Value:

(((x) & 0x3) << 4) /* Input A RX1 I<9:8> */

INPUT_A_RX1_Q

#define INPUT_A_RX1_Q

(

x

)

Value:

(((x) & 0x3) << 6) /* Input A RX1 Q<9:8> */

INPUT_A_RX2_I

#define INPUT_A_RX2_I

(

x

)

Value:

(((x) & 0x3) << 2) /* Input A RX2 I<9:8> */

INPUT_A_RX2_Q

#define INPUT_A_RX2_Q

(

x

)

Value:

(((x) & 0x3) << 0) /* Input A RX2 Q<9:8> */

INPUTS_BC_RX1_I

#define INPUTS_BC_RX1_I

(

x

)

Value:

(((x) & 0x3) << 4) /* Inputs B&C RX1 I<9:8> */

INPUTS_BC_RX1_Q

#define INPUTS_BC_RX1_Q

(

x

)

Value:

(((x) & 0x3) << 6) /* Inputs B&C RX1 Q<9:8> */

INPUTS_BC_RX2_I

#define INPUTS_BC_RX2_I

(

x

)

Value:

(((x) & 0x3) << 2) /* Inputs B&C RX2 I<9:8> */

INPUTS_BC_RX2_Q

#define INPUTS_BC_RX2_Q

(

x

)

Value:

(((x) & 0x3) << 0) /* Inputs B&C RX2 Q<9:8> */

INVERT_BYPASSED_LNA_POLARITY

#define INVERT_BYPASSED_LNA_POLARITY   (1 << 6) /* Invert Bypassed LNA Polarity */

INVERT_DATA_BUS

#define INVERT_DATA_BUS   (1 << 1) /* Invert data bus */

INVERT_DATA_CLK

#define INVERT_DATA_CLK   (1 << 0) /* Invert DATA CLK */

INVERT_I_DATA

#define INVERT_I_DATA   (1 << 5) /* Invert I data */

INVERT_Q_DATA

#define INVERT_Q_DATA   (1 << 4) /* Invert Q data */

INVERT_RX1

#define INVERT_RX1   (1 << 6) /* Invert Rx1 */

INVERT_RX1_RF_DC_CGIN_WORD

#define INVERT_RX1_RF_DC_CGIN_WORD   (1 << 6) /* Invert Rx1 RF DC CGin Word */

INVERT_RX1_RF_DC_CGOUT_WORD

#define INVERT_RX1_RF_DC_CGOUT_WORD   (1 << 4) /* Invert Rx1 RF DC CGout Word */

INVERT_RX2

#define INVERT_RX2   (1 << 5) /* Invert Rx2 */

INVERT_RX2_RF_DC_CGIN_WORD

#define INVERT_RX2_RF_DC_CGIN_WORD   (1 << 7) /* Invert Rx2 RF DC CGin Word */

INVERT_RX2_RF_DC_CGOUT_WORD

#define INVERT_RX2_RF_DC_CGOUT_WORD   (1 << 5) /* Invert Rx2 RF DC CGout Word */

INVERT_RX_FRAME

#define INVERT_RX_FRAME   (1 << 2) /* Invert Rx Frame */

INVERT_TX1

#define INVERT_TX1   (1 << 4) /* Invert Tx1 */

INVERT_TX2

#define INVERT_TX2   (1 << 3) /* Invert Tx2 */

K_EXP_AMPLITUDE

#define K_EXP_AMPLITUDE

(

x

)

Value:

(((x) & 0x1F) << 0) /* K exp Amplitude<4:0> */

K_EXP_PHASE

#define K_EXP_PHASE

(

x

)

Value:

(((x) & 0x1F) << 0) /* K exp Phase<4:0> */

KEXP_AMP

#define KEXP_AMP

(

x

)

Value:

(((x) & 0x3) << 0) /* Kexp Amp <1:0> */

KEXP_DC_I

#define KEXP_DC_I

(

x

)

Value:

(((x) & 0x3) << 2) /* Kexp DC I <1:0> */

KEXP_DC_Q

#define KEXP_DC_Q

(

x

)

Value:

(((x) & 0x3) << 0) /* Kexp DC Q <1:0> */

KEXP_PHASE

#define KEXP_PHASE

(

x

)

Value:

(((x) & 0x3) << 2) /* Kexp Phase <1:0> */

KEXP_TX

#define KEXP_TX

(

x

)

Value:

(((x) & 0x3) << 6) /* Kexp Tx<1:0> */

KEXP_TX_COMP

#define KEXP_TX_COMP

(

x

)

Value:

(((x) & 0x3) << 4) /* Kexp Tx_comp <1:0> */

LARGE_ADC_OL

#define LARGE_ADC_OL   (1 << 2) /* Large ADC OL */

LARGE_ADC_OVERLOAD_EXED_COUNTER

#define LARGE_ADC_OVERLOAD_EXED_COUNTER

(

x

)

Value:

(((x) & 0xF) << 4) /* Large ADC Overload Exceeded Counter<3:0> */

LARGE_LMT_OL

#define LARGE_LMT_OL   (1 << 4) /* Large LMT OL */

LARGE_LMT_OVERLOAD_EXED_COUNTER

#define LARGE_LMT_OVERLOAD_EXED_COUNTER

(

x

)

Value:

(((x) & 0xF) << 4) /* Large LMT Overload Exceeded Counter<3:0> */

LARGE_LMT_OVERLOAD_THRESH

#define LARGE_LMT_OVERLOAD_THRESH

(

x

)

Value:

(((x) & 0x3F) << 0) /* Large LMT Overload Threshold<5:0> */

LARGE_LPF_GAIN_STEP

#define LARGE_LPF_GAIN_STEP

(

x

)

Value:

(((x) & 0xF) << 0) /* Decrement Step Size for: Large LPF Gain Change / Full Table Case #1<3:0> */

LAST_ALC_ENABLE

#define LAST_ALC_ENABLE   (1 << 2) /* Last ALC Enable */

LEVEL_MODE

#define LEVEL_MODE   (1 << 3) /* Level Mode */

LMT_DETECTOR_SETTLING_TIME

#define LMT_DETECTOR_SETTLING_TIME

(

x

)

Value:

(((x) & 0x7) << 5) /* LMT Detector Settling Time<2:0> */

LNA_CALIB_TABLE_GAIN_DIFFERENCE_WORD

#define LNA_CALIB_TABLE_GAIN_DIFFERENCE_WORD

(

x

)

Value:

(((x) & 0x3F) << 0) /* LNA Calib Table Gain Difference Word<5:0> */

LNA_GAIN

#define LNA_GAIN

(

x

)

Value:

(((x) & 0x3) << 5) /* LNA Gain <1:0> */

LO_COMMON_MODE

#define LO_COMMON_MODE

(

x

)

Value:

(((x) & 0x3) << 5) /* LO Common Mode<1:0> */

LOCK_DETECT_COUNT [1/2]

#define LOCK_DETECT_COUNT

(

x

)

Value:

(((x) & 0x3) << 2) /* Lock Detect Count<1:0> */

LOCK_DETECT_COUNT [2/2]

#define LOCK_DETECT_COUNT

(

x

)

Value:

(((x) & 0x3) << 2) /* Lock Detect Count<1:0> */

LOCK_DETECT_MODE [1/2]

#define LOCK_DETECT_MODE

(

x

)

Value:

(((x) & 0x3) << 0) /* Lock Detect Mode<1:0> */

LOCK_DETECT_MODE [2/2]

#define LOCK_DETECT_MODE

(

x

)

Value:

(((x) & 0x3) << 0) /* Lock Detect Mode<1:0> */

LOOP_FILTER_BYPASS_C1 [1/2]

#define LOOP_FILTER_BYPASS_C1   (1 << 4) /* Loop Filter Bypass C1 */

LOOP_FILTER_BYPASS_C1 [2/2]

#define LOOP_FILTER_BYPASS_C1   (1 << 4) /* Loop Filter Bypass C1 */

LOOP_FILTER_BYPASS_C2 [1/2]

#define LOOP_FILTER_BYPASS_C2   (1 << 5) /* Loop Filter Bypass C2 */

LOOP_FILTER_BYPASS_C2 [2/2]

#define LOOP_FILTER_BYPASS_C2   (1 << 5) /* Loop Filter Bypass C2 */

LOOP_FILTER_BYPASS_R1 [1/2]

#define LOOP_FILTER_BYPASS_R1   (1 << 6) /* Loop Filter Bypass R1 */

LOOP_FILTER_BYPASS_R1 [2/2]

#define LOOP_FILTER_BYPASS_R1   (1 << 6) /* Loop Filter Bypass R1 */

LOOP_FILTER_BYPASS_R3 [1/2]

#define LOOP_FILTER_BYPASS_R3   (1 << 7) /* Loop Filter Bypass R3 */

LOOP_FILTER_BYPASS_R3 [2/2]

#define LOOP_FILTER_BYPASS_R3   (1 << 7) /* Loop Filter Bypass R3 */

LOOP_FILTER_C1 [1/2]

#define LOOP_FILTER_C1

(

x

)

Value:

(((x) & 0xF) << 0) /* Loop Filter C1<3:0> */

LOOP_FILTER_C1 [2/2]

#define LOOP_FILTER_C1

(

x

)

Value:

(((x) & 0xF) << 0) /* Loop Filter C1<3:0> */

LOOP_FILTER_C2 [1/2]

#define LOOP_FILTER_C2

(

x

)

Value:

(((x) & 0xF) << 4) /* Loop Filter C2<3:0> */

LOOP_FILTER_C2 [2/2]

#define LOOP_FILTER_C2

(

x

)

Value:

(((x) & 0xF) << 4) /* Loop Filter C2<3:0> */

LOOP_FILTER_C3 [1/2]

#define LOOP_FILTER_C3

(

x

)

Value:

(((x) & 0xF) << 0) /* Loop Filter C3<3:0> */

LOOP_FILTER_C3 [2/2]

#define LOOP_FILTER_C3

(

x

)

Value:

(((x) & 0xF) << 0) /* Loop Filter C3<3:0> */

LOOP_FILTER_R1 [1/2]

#define LOOP_FILTER_R1

(

x

)

Value:

(((x) & 0xF) << 4) /* Loop Filter R1<3:0> */

LOOP_FILTER_R1 [2/2]

#define LOOP_FILTER_R1

(

x

)

Value:

(((x) & 0xF) << 4) /* Loop Filter R1<3:0> */

LOOP_FILTER_R3 [1/2]

#define LOOP_FILTER_R3

(

x

)

Value:

(((x) & 0xF) << 0) /* Loop Filter R3<3:0> */

LOOP_FILTER_R3 [2/2]

#define LOOP_FILTER_R3

(

x

)

Value:

(((x) & 0xF) << 0) /* Loop Filter R3<3:0> */

LOW_POWER_1

#define LOW_POWER_1   (1 << 5) /* Low Power 1 */

LOW_POWER_THRESH

#define LOW_POWER_THRESH

(

x

)

Value:

(((x) & 0x7F) << 0) /* Low Power Threshold<6:0> */

LPF_GAIN

#define LPF_GAIN

(

x

)

Value:

(((x) & 0x1F) << 0) /* LPF Gain <4:0> */

LPF_GAIN_RX

#define LPF_GAIN_RX

(

x

)

Value:

(((x) & 0x1F) << 0) /* LPF gain Rx1<4:0> */

LSB_FIRST

#define LSB_FIRST   (1 << 5) /* LSB First */

LVDS_BIAS

#define LVDS_BIAS

(

x

)

Value:

(((x) & 0x7) << 0) /* LVDS Bias <2:0> */

LVDS_BYPASS_BIAS_R

#define LVDS_BYPASS_BIAS_R   (1 << 4) /* Bypass Bias R */

LVDS_MODE

#define LVDS_MODE   (1 << 4) /* LVDS Mode */

LVDS_TX_LO_VCM

#define LVDS_TX_LO_VCM   (1 << 3) /* LVDS Tx LO VCM */

M_DECIM

#define M_DECIM

(

x

)

Value:

(((x) & 0x3) << 0) /* M<1:0> */

MAN_GAIN_CTRL_RX1

#define MAN_GAIN_CTRL_RX1   (1 << 0) /* Manual Gain Control Rx 1 */

MAN_GAIN_CTRL_RX2

#define MAN_GAIN_CTRL_RX2   (1 << 1) /* Manual Gain Control Rx 2 */

MANUAL_CTRL_IN_DECR_GAIN_STP_SIZE

#define MANUAL_CTRL_IN_DECR_GAIN_STP_SIZE

(

x

)

Value:

(((x) & 0x7) << 5) /* Manual (CTRL_IN) Decr Gain Step Size<2:0> */

MANUAL_INCR_STEP_SIZE

#define MANUAL_INCR_STEP_SIZE

(

x

)

Value:

(((x) & 0x7) << 5) /* Manual (CTRL_IN) Incr Gain Step Size<2:0> */

MASK_CLR_ATTEN_UPDATE

#define MASK_CLR_ATTEN_UPDATE   (1 << 6) /* Mask Clr Atten Update */

MASTER_BIAS_FILTER_BYPASS

#define MASTER_BIAS_FILTER_BYPASS   (1 << 6) /* Master Bias Filter Bypass */

MASTER_BIAS_POWER_DOWN

#define MASTER_BIAS_POWER_DOWN   (1 << 0) /* Master Bias Power Down */

MASTER_BIAS_REF_SEL

#define MASTER_BIAS_REF_SEL   (1 << 5) /* Master Bias Ref Sel */

MASTER_BIAS_TRIM

#define MASTER_BIAS_TRIM

(

x

)

Value:

(((x) & 0x1F) << 0) /* Master Bias Trim<4:0> */

MAX_ADC_CLK

#define MAX_ADC_CLK   640000000U /* 640 MHz */

MAX_BASEBAND_RATE

#define MAX_BASEBAND_RATE   61440000UL

MAX_BBPLL_DIV

#define MAX_BBPLL_DIV   64

MAX_BBPLL_FREF

#define MAX_BBPLL_FREF   70007000UL /* 70 MHz + 100ppm */

MAX_BBPLL_FREQ

#define MAX_BBPLL_FREQ   1430143000UL /* 1430 MHz + 100ppm */

MAX_CARRIER_FREQ_HZ

#define MAX_CARRIER_FREQ_HZ   6000000000ULL

MAX_DAC_CLK

#define MAX_DAC_CLK   (MAX_ADC_CLK / 2)

MAX_DIG_GAIN

#define MAX_DIG_GAIN   31

MAX_LMT_INDEX

#define MAX_LMT_INDEX   40

MAX_LNA_GAIN

#define MAX_LNA_GAIN

(

x

)

Value:

(((x) & 0x7F) << 1) /* Max LNA Gain<6:0> */

MAX_LPF_GAIN

#define MAX_LPF_GAIN   24

MAX_MBYTE_SPI

#define MAX_MBYTE_SPI   8

MAX_MIXER_CALIBRATION_GAIN_INDEX

#define MAX_MIXER_CALIBRATION_GAIN_INDEX

(

x

)

Value:

(((x) & 0x1F) << 0) /* Max Mixer Calibration Gain Index<4:0> */

MAX_RX_HB1

#define MAX_RX_HB1   245760000UL

MAX_RX_HB2

#define MAX_RX_HB2   320000000UL

MAX_RX_HB3

#define MAX_RX_HB3   640000000UL

MAX_SYNTH_FREF

#define MAX_SYNTH_FREF   80008000UL /* 80 MHz + 100ppm */

MAX_TX_ATTENUATION_DB

#define MAX_TX_ATTENUATION_DB   89750

MAX_TX_HB1

#define MAX_TX_HB1   160000000UL

MAX_TX_HB2

#define MAX_TX_HB2   320000000UL

MAX_TX_HB3

#define MAX_TX_HB3   320000000UL

MAXIMUM_DIGITAL_GAIN

#define MAXIMUM_DIGITAL_GAIN

(

x

)

Value:

(((x) & 0x1F) << 0) /* Maximum Digital Gain<4:0> */

MAXIMUM_FULL_TABLELMT_TABLE_INDEX

#define MAXIMUM_FULL_TABLELMT_TABLE_INDEX

(

x

)

Value:

(((x) & 0x7F) << 0) /* Maximum Full Table/LMT Table Index<6:0> */

MCS_BB_ENABLE

#define MCS_BB_ENABLE   (1 << 0) /* MCS BB Enable */

MCS_BBPLL_ENABLE

#define MCS_BBPLL_ENABLE   (1 << 2) /* MCS BBPLL enable */

MCS_DIGITAL_CLK_ENABLE

#define MCS_DIGITAL_CLK_ENABLE   (1 << 1) /* MCS Digital CLK Enable */

MCS_REFCLK_SCALE_EN

#define MCS_REFCLK_SCALE_EN   (1 << 7) /* MCS refclk Scale En */

MCS_RF_ENABLE

#define MCS_RF_ENABLE   (1 << 3) /* MCS RF Enable */

MEASUREMENT_DURATION_0

#define MEASUREMENT_DURATION_0

(

x

)

Value:

(((x) & 0xF) << 0) /* Measurement duration 0 <3:0> */

MEASUREMENT_DURATION_1

#define MEASUREMENT_DURATION_1

(

x

)

Value:

(((x) & 0xF) << 4) /* Measurement duration 1 <3:0> */

MEASUREMENT_DURATION_2

#define MEASUREMENT_DURATION_2

(

x

)

Value:

(((x) & 0xF) << 0) /* Measurement duration 2 <3:0> */

MEASUREMENT_DURATION_3

#define MEASUREMENT_DURATION_3

(

x

)

Value:

(((x) & 0xF) << 4) /* Measurement duration 3 <3:0> */

MEASUREMENT_TIME_INTERVAL

#define MEASUREMENT_TIME_INTERVAL

(

x

)

Value:

(((x) & 0x7F) << 1) /* Measurement Time Interval<6:0> */

MIN_ADC_CLK

#define MIN_ADC_CLK   25000000U /* 25 MHz */

MIN_BBPLL_DIV

#define MIN_BBPLL_DIV   2

MIN_BBPLL_FREQ

#define MIN_BBPLL_FREQ   714928500UL /* 715 MHz - 100ppm */

MIN_RX_CARRIER_FREQ_HZ

#define MIN_RX_CARRIER_FREQ_HZ   70000000ULL

MIN_SYNTH_FREF

#define MIN_SYNTH_FREF   9999000UL /* 10 MHz - 100ppm */

MIN_TX_CARRIER_FREQ_HZ

#define MIN_TX_CARRIER_FREQ_HZ   46875001ULL

MIN_VCO_FREQ_HZ

#define MIN_VCO_FREQ_HZ   6000000000ULL

MIXER_GM_GAIN

#define MIXER_GM_GAIN

(

x

)

Value:

(((x) & 0x1F) << 0) /* Mixer Gm Gain <4:0> */

MUST_BE_ZERO [1/2]

#define MUST_BE_ZERO   (1 << 7) /* Must be zero */

MUST_BE_ZERO [2/2]

#define MUST_BE_ZERO   (1 << 7) /* Must be zero */

MUST_BE_ZEROS

#define MUST_BE_ZEROS

(

x

)

Value:

(((x) & 0x3) << 5) /* Must be zeros */

NUMBER_OF_TAPS

#define NUMBER_OF_TAPS

(

x

)

Value:

(((x) & 0x7) << 5) /* Number of Taps */

NUMBER_SDM_DITHER_BITS

#define NUMBER_SDM_DITHER_BITS

(

x

)

Value:

(((x) & 0xF) << 4) /* Number SDM Dither Bits<3:0> */

OBSERVATION_POINT

#define OBSERVATION_POINT

(

x

)

Value:

(((x) & 0xF) << 1) /* Observation Point<2:0> */

ONE_SHOT_MODE

#define ONE_SHOT_MODE   (1 << 6) /* One Shot Mode */

OPAMP_A_CC

#define OPAMP_A_CC

(

x

)

Value:

(((x) & 0x7) << 0) /* OpAmp A CC<2:0> */

OPAMP_B_CC

#define OPAMP_B_CC

(

x

)

Value:

(((x) & 0x7) << 0) /* OpAmp B CC<2:0> */

OPAMPA_OUTPUT_BIAS

#define OPAMPA_OUTPUT_BIAS

(

x

)

Value:

(((x) & 0x3) << 5) /* OpAmpA Output Bias<1:0> */

OPAMPA_RZ

#define OPAMPA_RZ

(

x

)

Value:

(((x) & 0x3) << 3) /* OpAmpA RZ<1:0> */

OPAMPB_OUTPUT_BIAS

#define OPAMPB_OUTPUT_BIAS

(

x

)

Value:

(((x) & 0x3) << 5) /* OpAmpB Output Bias<1:0> */

OPAMPB_RZ

#define OPAMPB_RZ

(

x

)

Value:

(((x) & 0x3) << 3) /* OpAmpB RZ<1:0> */

OPEN

#define OPEN

(

x

)

Value:

(((x) & 0xF) << 0) /* Open<3:0> */

OPTIMIZE_GAIN_OFFSET

#define OPTIMIZE_GAIN_OFFSET

(

x

)

Value:

(((x) & 0xF) << 0) /* Optimize Gain Offset<3:0> */

OVERRIDE_ENABLE

#define OVERRIDE_ENABLE   (1 << 7) /* Override enable */

PD_TUNE

#define PD_TUNE   (1 << 2) /* PD Tune */

PEAK_OVERLOAD_WAIT_TIME

#define PEAK_OVERLOAD_WAIT_TIME

(

x

)

Value:

(((x) & 0x1F) << 0) /* Peak Overload Wait Time<4:0> */

PFD_CLK_EDGE

#define PFD_CLK_EDGE   (1 << 1) /* PFD Clk Edge */

PFD_WIDTH

#define PFD_WIDTH

(

x

)

Value:

(((x) & 0x3) << 2) /* PFD Width <1:0> */

PHASE_ENABLE

#define PHASE_ENABLE   (1 << 3) /* Phase Enable */

POLE_GAIN_TUNE

#define POLE_GAIN_TUNE

(

x

)

Value:

(((x) & 0x3) << 0) /* Pole Gain Tune<1:0> */

PORB_VCO_LOGIC [1/2]

#define PORB_VCO_LOGIC   (1 << 6) /* PORb VCO Logic */

PORB_VCO_LOGIC [2/2]

#define PORB_VCO_LOGIC   (1 << 6) /* PORb VCO Logic */

POST_LOCK_LEVEL_STP_FOR_LMT_TABLE

#define POST_LOCK_LEVEL_STP_FOR_LMT_TABLE

(

x

)

Value:

(((x) & 0x3) << 6) /* Post Lock Level Step for LMT   Table <1:0> */

POST_LOCK_LEVEL_STP_SIZE_FOR_LPF_TABLE_FULL_TABLE

#define POST_LOCK_LEVEL_STP_SIZE_FOR_LPF_TABLE_FULL_TABLE

(

x

)

Value:

(((x) & 0x3) << 6) /* Post Lock Level Step Size for: LPF Table/ Full Table <1:0> */

POWER_DOWN_BANDGAP_REF

#define POWER_DOWN_BANDGAP_REF   (1 << 7) /* Power Down Bandgap Ref */

POWER_DOWN_CAL_TCF [1/2]

#define POWER_DOWN_CAL_TCF   (1 << 1) /* Power Down Cal Tcf */

POWER_DOWN_CAL_TCF [2/2]

#define POWER_DOWN_CAL_TCF   (1 << 1) /* Power Down Cal Tcf */

POWER_DOWN_RX_SYNTH

#define POWER_DOWN_RX_SYNTH   (1 << 6) /* Power Down Rx Synth */

POWER_DOWN_TX_SYNTH

#define POWER_DOWN_TX_SYNTH   (1 << 5) /* Power Down Tx Synth */

POWER_DOWN_VARACT_REF_TCF

#define POWER_DOWN_VARACT_REF_TCF   (1 << 2) /* Power Down Varact Ref Tcf */

POWER_DOWN_VARACTOR_REF [1/2]

#define POWER_DOWN_VARACTOR_REF   (1 << 3) /* Power Down Varactor Ref */

POWER_DOWN_VARACTOR_REF [2/2]

#define POWER_DOWN_VARACTOR_REF   (1 << 3) /* Power Down Varactor Ref */

POWER_DOWN_VCO_BUFFFER [1/2]

#define POWER_DOWN_VCO_BUFFFER   (1 << 0) /* Power Down VCO Bufffer */

POWER_DOWN_VCO_BUFFFER [2/2]

#define POWER_DOWN_VCO_BUFFFER   (1 << 0) /* Power Down VCO Bufffer */

POWER_MEAS_IN_STATE_5

#define POWER_MEAS_IN_STATE_5

(

x

)

Value:

(((x) & 0x7) << 5) /* Power Meas in State 5<2:0> */

POWER_MEAS_IN_STATE_5_MSB

#define POWER_MEAS_IN_STATE_5_MSB   (1 << 7) /* Power Meas in State 5 <3> */

PP_RX_SWAP_IQ

#define PP_RX_SWAP_IQ   (1 << 6) /* PP Rx Swap IQ */

PP_TX_SWAP_IQ

#define PP_TX_SWAP_IQ   (1 << 7) /* PP Tx Swap IQ */

PRESCALE_BIAS

#define PRESCALE_BIAS

(

x

)

Value:

(((x) & 0x3) << 0) /* Prescale Bias <1:0> */

PREVENT_GAIN_INC

#define PREVENT_GAIN_INC   (1 << 7) /* Prevent Gain Inc */

PREVENT_POS_LOOP_GAIN

#define PREVENT_POS_LOOP_GAIN   (1 << 7) /* Prevent Pos Loop Gain */

PRODUCT_ID_9361

#define PRODUCT_ID_9361   0x08

PRODUCT_ID_MASK

#define PRODUCT_ID_MASK   0xF8

PWR_DOWN_VARACT_REF_TCF

#define PWR_DOWN_VARACT_REF_TCF   (1 << 2) /* Pwr Down Varact Ref Tcf */

QUAD_CAL_SOFT_RESET

#define QUAD_CAL_SOFT_RESET   (1 << 2) /* Quad Cal Soft Reset */

R1

#define R1

(

x

)

Value:

(((x) & 0x1F) << 0) /* R1<4:0> */

R1_WORD

#define R1_WORD

(

x

)

Value:

(((x) & 0x1F) << 0) /* R1 Word<4:0> */

R2

#define R2

(

x

)

Value:

(((x) & 0x1F) << 0) /* R2<4:0> */

R2_WORD

#define R2_WORD   (1 << 7) /* R2 Word<0> */

R2_WORD_LSB

#define R2_WORD_LSB

(

x

)

Value:

(((x) & 0x3) << 0) /* R2 Word<2:1> */

R2B

#define R2B

(

x

)

Value:

(((x) & 0x1F) << 0) /* R2b<4:0> */

R2B_OVR

#define R2B_OVR   (1 << 5) /* R2b Ovr */

R2T2_TIMING

#define R2T2_TIMING   (1 << 2) /* 2R2T Timing */

R3

#define R3

(

x

)

Value:

(((x) & 0x1F) << 0) /* R3<4:0> */

R4

#define R4

(

x

)

Value:

(((x) & 0x1F) << 0) /* R4<4:0> */

READ_BACK_CH_SEL

#define READ_BACK_CH_SEL   (1 << 7) /* Read Back CH Sel */

READ_EFFECTIVE_TUNING_WORD [1/2]

#define READ_EFFECTIVE_TUNING_WORD   (1 << 5) /* Read Effective Tuning Word */

READ_EFFECTIVE_TUNING_WORD [2/2]

#define READ_EFFECTIVE_TUNING_WORD   (1 << 5) /* Read Effective Tuning Word */

READ_SELECT

#define READ_SELECT   (1 << 4) /* Read Select */

RECEIVER_SELECT

#define RECEIVER_SELECT

(

x

)

Value:

(((x) & 0x3) << 3) /* Receiver Select<1:0> */

REF_DIVIDE_CONFIG_1_DFLT

#define REF_DIVIDE_CONFIG_1_DFLT   (1 << 2) /* Set to 1 */

REF_FREQ_SCALER

#define REF_FREQ_SCALER

(

x

)

Value:

(((x) & 0x3) << 0) /* Ref Frequency Scaler */

REFERENCE_CLOCK_CYCLES_PER_US

#define REFERENCE_CLOCK_CYCLES_PER_US

(

x

)

Value:

(((x) & 0x7F) << 0) /* Reference Clock Cycles per us<6:0> */

REG_ADC_LARGE_OVERLOAD_THRESH

#define REG_ADC_LARGE_OVERLOAD_THRESH   0x105 /* ADC Large Overload Threshold */

REG_ADC_MEASURE_DURATION_01

#define REG_ADC_MEASURE_DURATION_01   0x159 /* ADC Measure Duration 0&1 */

REG_ADC_NOISE_CORRECTION_FACTOR

#define REG_ADC_NOISE_CORRECTION_FACTOR   0x102 /* ADC noise Correction Factor */

REG_ADC_OVERLOAD_COUNTERS

#define REG_ADC_OVERLOAD_COUNTERS   0x122 /* ADC Overload Counters */

REG_ADC_SMALL_OVERLOAD_THRESH

#define REG_ADC_SMALL_OVERLOAD_THRESH   0x104 /* ADC Small Overload Threshold */

REG_ADC_WEIGHT_0

#define REG_ADC_WEIGHT_0   0x15A /* ADC Weight 0 */

REG_ADC_WEIGHT_1

#define REG_ADC_WEIGHT_1   0x15B /* ADC Weight 1 */

REG_AGC_ATTACK_DELAY

#define REG_AGC_ATTACK_DELAY   0x022 /* AGC Attack Delay */

REG_AGC_CONFIG_1

#define REG_AGC_CONFIG_1   0x0FA /* AGC Config1 */

REG_AGC_CONFIG_2

#define REG_AGC_CONFIG_2   0x0FB /* AGC config2 */

REG_AGC_CONFIG_3

#define REG_AGC_CONFIG_3   0x0FC /* AGC Config3 */

REG_AGC_GAIN_LOCK_DELAY

#define REG_AGC_GAIN_LOCK_DELAY   0x021 /* AGC Gain Lock Delay */

REG_AGC_INNER_LOW_THRESH

#define REG_AGC_INNER_LOW_THRESH   0x120 /* AGC Inner Low Threshold */

REG_AGC_LOCK_LEVEL

#define REG_AGC_LOCK_LEVEL   0x101 /* AGC Lock Level */

REG_ANALOG_POWER_DOWN_OVERRIDE

#define REG_ANALOG_POWER_DOWN_OVERRIDE   0x057 /* Analog Power Down Override */

REG_AUTO_GPO

#define REG_AUTO_GPO   0x020 /* Auto GPO */

REG_AUXADC_CLOCK_DIVIDER

#define REG_AUXADC_CLOCK_DIVIDER   0x01C /* AuxADC Clock Divider */

REG_AUXADC_CONFIG

#define REG_AUXADC_CONFIG   0x01D /* Aux ADC Config */

REG_AUXADC_LSB

#define REG_AUXADC_LSB   0x01F /* AuxADC LSB */

REG_AUXADC_WORD_MSB

#define REG_AUXADC_WORD_MSB   0x01E /* AuxADC Word MSB */

REG_AUXDAC1_RX_DELAY

#define REG_AUXDAC1_RX_DELAY   0x030 /* AuxDAC1 Rx Delay */

REG_AUXDAC1_TX_DELAY

#define REG_AUXDAC1_TX_DELAY   0x031 /* AuxDAC1 Tx Delay */

REG_AUXDAC2_RX_DELAY

#define REG_AUXDAC2_RX_DELAY   0x032 /* AuxDAC2 Rx Delay */

REG_AUXDAC2_TX_DELAY

#define REG_AUXDAC2_TX_DELAY   0x033 /* AuxDAC2 Tx Delay */

REG_AUXDAC_1_CONFIG

#define REG_AUXDAC_1_CONFIG   0x01A /* AuxDAC 1 Config */

REG_AUXDAC_1_WORD

#define REG_AUXDAC_1_WORD   0x018 /* AuxDAC 1 Word */

REG_AUXDAC_2_CONFIG

#define REG_AUXDAC_2_CONFIG   0x01B /* AuxDAC 2 Config */

REG_AUXDAC_2_WORD

#define REG_AUXDAC_2_WORD   0x019 /* AuxDAC 2 Word */

REG_AUXDAC_ENABLE_CTRL

#define REG_AUXDAC_ENABLE_CTRL   0x023 /* AuxDAC Enable Control */

REG_BAND1_RX1_Q

#define REG_BAND1_RX1_Q   0x1CE /* Band1 RX1 Q */

REG_BANDGAP_CONFIG0

#define REG_BANDGAP_CONFIG0   0x2A6 /* Bandgap Config0 */

REG_BANDGAP_CONFIG1

#define REG_BANDGAP_CONFIG1   0x2A8 /* Bandgap Config1 */

REG_BB_DC_OFFSET_ATTEN

#define REG_BB_DC_OFFSET_ATTEN   0x194 /* BB DC Offset Attenuation */

REG_BB_DC_OFFSET_COUNT

#define REG_BB_DC_OFFSET_COUNT   0x193 /* BB DC Offset Count */

REG_BB_DC_OFFSET_FAST_SETTLE_SHIFT

#define REG_BB_DC_OFFSET_FAST_SETTLE_SHIFT   0x191 /* BB DC Offset Fast Settle Shift */

REG_BB_DC_OFFSET_SHIFT

#define REG_BB_DC_OFFSET_SHIFT   0x190 /* BB DC Offset Shift */

REG_BB_FAST_SETTLE_DUR

#define REG_BB_FAST_SETTLE_DUR   0x192 /* BB Fast Settle Dur */

REG_BB_TRACK_CORR_WORD_I_LSB

#define REG_BB_TRACK_CORR_WORD_I_LSB   0x1A3 /* BB Track corr word I LSB */

REG_BB_TRACK_CORR_WORD_I_MSB

#define REG_BB_TRACK_CORR_WORD_I_MSB   0x1A2 /* BB Track corr word I MSB */

REG_BB_TRACK_CORR_WORD_Q_LSB

#define REG_BB_TRACK_CORR_WORD_Q_LSB   0x1A5 /* BB Track corr word Q LSB */

REG_BB_TRACK_CORR_WORD_Q_MSB

#define REG_BB_TRACK_CORR_WORD_Q_MSB   0x1A4 /* BB Track corr word Q MSB */

REG_BBPLL

#define REG_BBPLL   0x00A /* BBPLL */

REG_BIST_AND_DATA_PORT_TEST_CONFIG

#define REG_BIST_AND_DATA_PORT_TEST_CONFIG   0x3F6 /* BIST and Data Port Test Config */

REG_BIST_CONFIG

#define REG_BIST_CONFIG   0x3F4 /* BIST Config */

REG_CAL_TEMP_SENSOR_WORD

#define REG_CAL_TEMP_SENSOR_WORD   0x149 /* Cal Temp sensor word */

REG_CALIB_COUNT

#define REG_CALIB_COUNT   0x16C /* Calib count */

REG_CALIBRATION_CONFIG_1

#define REG_CALIBRATION_CONFIG_1   0x169 /* Calibration Config 1 */

REG_CALIBRATION_CONFIG_2

#define REG_CALIBRATION_CONFIG_2   0x16A /* Calibration config2 */

REG_CALIBRATION_CONFIG_3

#define REG_CALIBRATION_CONFIG_3   0x16B /* Calibration config3 */

REG_CALIBRATION_CTRL

#define REG_CALIBRATION_CTRL   0x016 /* Calibration Control */

REG_CAPACITOR

#define REG_CAPACITOR   0x0D2 /* Capacitor */

REG_CH1_ADC_POWER

#define REG_CH1_ADC_POWER   0x160 /* CH1 ADC Power */

REG_CH1_RX_FILTER_POWER

#define REG_CH1_RX_FILTER_POWER   0x161 /* CH1 Rx filter Power */

REG_CH2_ADC_POWER

#define REG_CH2_ADC_POWER   0x162 /* CH2 ADC Power */

REG_CH2_RX_FILTER_POWER

#define REG_CH2_RX_FILTER_POWER   0x163 /* CH2 Rx filter Power */

REG_CH_1_OVERFLOW

#define REG_CH_1_OVERFLOW   0x05E /* CH 1 Overflow */

REG_CH_2_OVERFLOW

#define REG_CH_2_OVERFLOW   0x05F /* CH 2 Overflow */

REG_CLOCK_CTRL

#define REG_CLOCK_CTRL   0x045 /* Clock Control */

REG_CLOCK_ENABLE

#define REG_CLOCK_ENABLE   0x009 /* Clock Enable */

REG_CONFIG

#define REG_CONFIG   0x143 /* Config */

REG_CONFIG0

#define REG_CONFIG0   0x0D0 /* Config0 */

REG_CP_BLEED_CURRENT

#define REG_CP_BLEED_CURRENT   0x047 /* CP Bleed Current */

REG_CP_CURRENT

#define REG_CP_CURRENT   0x046 /* CP Current */

REG_CTRL

#define REG_CTRL   0x3DF /* Control */

REG_CTRL_OUTPUT_ENABLE

#define REG_CTRL_OUTPUT_ENABLE   0x036 /* Control Output Enable */

REG_CTRL_OUTPUT_POINTER

#define REG_CTRL_OUTPUT_POINTER   0x035 /* Control Output Pointer */

REG_DAC_TEST_0

#define REG_DAC_TEST_0   0x3FC /* DAC Test 0 */

REG_DAC_TEST_1

#define REG_DAC_TEST_1   0x3FD /* DAC Test 1 */

REG_DAC_TEST_2

#define REG_DAC_TEST_2   0x3FE /* DAC Test 2 */

REG_DC_OFFSET_CONFIG2

#define REG_DC_OFFSET_CONFIG2   0x18B /* DC Offset Config2 */

REG_DCXO_COARSE_TUNE

#define REG_DCXO_COARSE_TUNE   0x292 /* DCXO Coarse Tune */

REG_DCXO_CONFIG

#define REG_DCXO_CONFIG   0x295 /* DCXO Config */

REG_DCXO_FINE_TUNE_HIGH

#define REG_DCXO_FINE_TUNE_HIGH   0x293 /* DCXO Fine Tune2 */

REG_DCXO_FINE_TUNE_LOW

#define REG_DCXO_FINE_TUNE_LOW   0x294 /* DCXO Fine Tune1 */

REG_DCXO_TEMPCO_ADDR

#define REG_DCXO_TEMPCO_ADDR   0x298 /* DCXO Tempco Addr */

REG_DCXO_TEMPCO_READ

#define REG_DCXO_TEMPCO_READ   0x297 /* DCXO Tempco Read */

REG_DCXO_TEMPCO_WRITE

#define REG_DCXO_TEMPCO_WRITE   0x296 /* DCXO Tempco Write */

REG_DEC_POWER_MEASURE_DURATION_0

#define REG_DEC_POWER_MEASURE_DURATION_0   0x15C /* Dec Power Measure Duration 0 */

REG_DELTA_T_READ

#define REG_DELTA_T_READ   0x299 /* Delta T Read */

REG_DIG_GAIN_RX1

#define REG_DIG_GAIN_RX1   0x2B2 /* Dig gain Rx1 */

REG_DIG_GAIN_RX2

#define REG_DIG_GAIN_RX2   0x2B7 /* Dig Gain Rx2 */

REG_DIGITAL_GAIN

#define REG_DIGITAL_GAIN   0x100 /* Digital Gain */

REG_DIGITAL_IO_CTRL

#define REG_DIGITAL_IO_CTRL   0x03B /* Digital I/O Control */

REG_DIGITAL_SAT_COUNTER

#define REG_DIGITAL_SAT_COUNTER   0x128 /* Digital Sat Counter */

REG_ENSM_CONFIG_1

#define REG_ENSM_CONFIG_1   0x014 /* ENSM Config 1 */

REG_ENSM_CONFIG_2

#define REG_ENSM_CONFIG_2   0x015 /* ENSM Config 2 */

REG_ENSM_MODE

#define REG_ENSM_MODE   0x013 /* ENSM Mode */

REG_EXT_LNA_HIGH_GAIN

#define REG_EXT_LNA_HIGH_GAIN   0x12C /* Ext LNA High Gain */

REG_EXT_LNA_LOW_GAIN

#define REG_EXT_LNA_LOW_GAIN   0x12D /* Ext LNA Low Gain */

REG_EXTERNAL_LNA_CTRL

#define REG_EXTERNAL_LNA_CTRL   0x026 /* External LNA control */

REG_FAST_AGCLL_UPPER_LIMIT

#define REG_FAST_AGCLL_UPPER_LIMIT   0x118 /* AGCLL Upper Limit */

REG_FAST_ATTACK_STATE

#define REG_FAST_ATTACK_STATE   0x2B3 /* Fast Attack State */

REG_FAST_CONFIG_1

#define REG_FAST_CONFIG_1   0x110 /* Config 1 */

REG_FAST_CONFIG_2_SETTLING_DELAY

#define REG_FAST_CONFIG_2_SETTLING_DELAY   0x111 /* Config 2 & Settling Delay */

REG_FAST_ENERGY_DETECT_COUNT

#define REG_FAST_ENERGY_DETECT_COUNT   0x117 /* Energy Detect Count */

REG_FAST_ENERGY_LOST_THRESH

#define REG_FAST_ENERGY_LOST_THRESH   0x112 /* Energy Lost Threshold */

REG_FAST_FINAL_OVER_RANGE_AND_OPT_GAIN

#define REG_FAST_FINAL_OVER_RANGE_AND_OPT_GAIN   0x116 /* Final Over Range and Opt Gain */

REG_FAST_GAIN_LOCK_EXIT_COUNT

#define REG_FAST_GAIN_LOCK_EXIT_COUNT   0x119 /* Gain Lock Exit Count */

REG_FAST_INCREMENT_TIME

#define REG_FAST_INCREMENT_TIME   0x11B /* Increment Time */

REG_FAST_INITIAL_LMT_GAIN_LIMIT

#define REG_FAST_INITIAL_LMT_GAIN_LIMIT   0x11A /* Initial LMT Gain Limit */

REG_FAST_LOW_POWER_THRESH

#define REG_FAST_LOW_POWER_THRESH   0x114 /* Low Power Threshold */

REG_FAST_STRONG_SIGNAL_FREEZE

#define REG_FAST_STRONG_SIGNAL_FREEZE   0x115 /* Strong Signal Freeze */

REG_FAST_STRONGER_SIGNAL_THRESH

#define REG_FAST_STRONGER_SIGNAL_THRESH   0x113 /* Stronger Signal Threshold */

REG_FB_DAC_BIAS_CURRENT

#define REG_FB_DAC_BIAS_CURRENT   0x218 /* FB DAC Bias Current */

REG_FB_DAC_CLK_DELAY1

#define REG_FB_DAC_CLK_DELAY1   0x201 /* FB DAC Clk Delay1 */

REG_FB_DAC_CLK_DELAY2

#define REG_FB_DAC_CLK_DELAY2   0x202 /* FB DAC Clk Delay2 */

REG_FLASH_BIAS_CURRENT

#define REG_FLASH_BIAS_CURRENT   0x222 /* Flash Bias Current */

REG_FLASH_LADDER_BIAS

#define REG_FLASH_LADDER_BIAS   0x223 /* Flash Ladder Bias */

REG_FLASH_LADDER_BIAS2

#define REG_FLASH_LADDER_BIAS2   0x225 /* Flash Ladder Bias2 */

REG_FLASH_LADDER_CASCODE_CURRENT

#define REG_FLASH_LADDER_CASCODE_CURRENT   0x224 /* Flash Ladder Cascode Current */

REG_FLASH_SAMPLE_CLK_DELAY_3N

#define REG_FLASH_SAMPLE_CLK_DELAY_3N   0x204 /* Flash Sample Clk Delay 3n */

REG_FLASH_SAMPLE_CLK_DELAY_3P

#define REG_FLASH_SAMPLE_CLK_DELAY_3P   0x203 /* Flash Sample Clk Delay 3p */

REG_FORCE_BITS

#define REG_FORCE_BITS   0x182 /* Force Bits */

REG_FORCE_OS_DAC

#define REG_FORCE_OS_DAC   0x1D2 /* Force OS DAC */

REG_FRACT_BB_FREQ_WORD_1

#define REG_FRACT_BB_FREQ_WORD_1   0x041 /* Fractional BB Freq Word 1 */

REG_FRACT_BB_FREQ_WORD_2

#define REG_FRACT_BB_FREQ_WORD_2   0x042 /* Fractional BB Freq Word 2 */

REG_FRACT_BB_FREQ_WORD_3

#define REG_FRACT_BB_FREQ_WORD_3   0x043 /* Fractional BB Freq Word 3 */

REG_GAIN_DIFF_WORDERROR_WRITE

#define REG_GAIN_DIFF_WORDERROR_WRITE   0x141 /* Gain Diff Word/Error Write */

REG_GAIN_ERROR_READ

#define REG_GAIN_ERROR_READ   0x142 /* Gain Error Read */

REG_GAIN_RX1

#define REG_GAIN_RX1   0x2B0 /* Gain Rx1 */

REG_GAIN_RX2

#define REG_GAIN_RX2   0x2B5 /* Gain Rx2 */

REG_GAIN_STP1

#define REG_GAIN_STP1   0x123 /* Gain Step1 */

REG_GAIN_STP_2

#define REG_GAIN_STP_2   0x12A /* Gain Step 2 */

REG_GAIN_STP_CONFIG1

#define REG_GAIN_STP_CONFIG1   0x103 /* Gain Step Config1 */

REG_GAIN_STP_CONFIG_2

#define REG_GAIN_STP_CONFIG_2   0x106 /* Gain Step Config 2 */

REG_GAIN_TABLE_ADDRESS

#define REG_GAIN_TABLE_ADDRESS   0x130 /* Gain Table Address */

REG_GAIN_TABLE_CONFIG

#define REG_GAIN_TABLE_CONFIG   0x137 /* Gain Table Config */

REG_GAIN_TABLE_READ_DATA1

#define REG_GAIN_TABLE_READ_DATA1   0x134 /* Gain Table Read Data 1 */

REG_GAIN_TABLE_READ_DATA2

#define REG_GAIN_TABLE_READ_DATA2   0x135 /* Gain Table Read Data 2 */

REG_GAIN_TABLE_READ_DATA3

#define REG_GAIN_TABLE_READ_DATA3   0x136 /* Gain Table Read Data 3 */

REG_GAIN_TABLE_WRITE_DATA1

#define REG_GAIN_TABLE_WRITE_DATA1   0x131 /* Gain Table Write Data1 */

REG_GAIN_TABLE_WRITE_DATA2

#define REG_GAIN_TABLE_WRITE_DATA2   0x132 /* Gain Table Write Data2 */

REG_GAIN_TABLE_WRITE_DATA3

#define REG_GAIN_TABLE_WRITE_DATA3   0x133 /* Gain Table Write Data 3 */

REG_GAIN_UPDATE_COUNTER1

#define REG_GAIN_UPDATE_COUNTER1   0x124 /* Gain Update Counter1 */

REG_GAIN_UPDATE_COUNTER2

#define REG_GAIN_UPDATE_COUNTER2   0x125 /* Gain Update Counter2 */

REG_GM_SUB_TABLE_ADDRESS

#define REG_GM_SUB_TABLE_ADDRESS   0x138 /* Gm Sub Table Address */

REG_GM_SUB_TABLE_BIAS_READ

#define REG_GM_SUB_TABLE_BIAS_READ   0x13D /* Gm Sub Table Bias Word Read */

REG_GM_SUB_TABLE_BIAS_WRITE

#define REG_GM_SUB_TABLE_BIAS_WRITE   0x13A /* Gm Sub Table Bias Word Write */

REG_GM_SUB_TABLE_CONFIG

#define REG_GM_SUB_TABLE_CONFIG   0x13F /* Gm Sub Table Config */

REG_GM_SUB_TABLE_CTRL_READ

#define REG_GM_SUB_TABLE_CTRL_READ   0x13E /* Gm Sub Table Control Word Read */

REG_GM_SUB_TABLE_CTRL_WRITE

#define REG_GM_SUB_TABLE_CTRL_WRITE   0x13B /* Gm Sub Table Control Word Write */

REG_GM_SUB_TABLE_GAIN_READ

#define REG_GM_SUB_TABLE_GAIN_READ   0x13C /* Gm Sub Table Gain Word Read */

REG_GM_SUB_TABLE_GAIN_WRITE

#define REG_GM_SUB_TABLE_GAIN_WRITE   0x139 /* Gm Sub Table Gain Word Write */

REG_GPO0_RX_DELAY

#define REG_GPO0_RX_DELAY   0x028 /* GPO0 Rx delay */

REG_GPO0_TX_DELAY

#define REG_GPO0_TX_DELAY   0x02C /* GPO0 Tx Delay */

REG_GPO1_RX_DELAY

#define REG_GPO1_RX_DELAY   0x029 /* GPO1 Rx delay */

REG_GPO1_TX_DELAY

#define REG_GPO1_TX_DELAY   0x02D /* GPO1 Tx Delay */

REG_GPO2_RX_DELAY

#define REG_GPO2_RX_DELAY   0x02A /* GPO2 Rx delay */

REG_GPO2_TX_DELAY

#define REG_GPO2_TX_DELAY   0x02E /* GPO2 Tx Delay */

REG_GPO3_RX_DELAY

#define REG_GPO3_RX_DELAY   0x02B /* GPO3 Rx delay */

REG_GPO3_TX_DELAY

#define REG_GPO3_TX_DELAY   0x02F /* GPO3 Tx Delay */

REG_GPO_FORCE_AND_INIT

#define REG_GPO_FORCE_AND_INIT   0x027 /* GPO Force and Init */

REG_INPUT_A_MSBS

#define REG_INPUT_A_MSBS   0x1C8 /* Input A MSBs */

REG_INPUT_A_OFFSETS_1

#define REG_INPUT_A_OFFSETS_1   0x176 /* Input A Offsets 1 */

REG_INPUT_A_RX1_I

#define REG_INPUT_A_RX1_I   0x1C9 /* Input A RX1 I */

REG_INPUT_A_RX1_Q

#define REG_INPUT_A_RX1_Q   0x1CA /* Input A RX1 Q */

REG_INPUT_A_RX2_I

#define REG_INPUT_A_RX2_I   0x1CB /* Input A RX2 I */

REG_INPUT_A_RX2_Q

#define REG_INPUT_A_RX2_Q   0x1CC /* Input A RX2 Q */

REG_INPUT_BC_OFFSETS_1

#define REG_INPUT_BC_OFFSETS_1   0x17F /* Input B&C Offsets 1 */

REG_INPUT_SELECT

#define REG_INPUT_SELECT   0x004 /* Input Select */

REG_INPUTS_BC_MSBS

#define REG_INPUTS_BC_MSBS   0x1D1 /* Inputs B&C MSBs */

REG_INPUTS_BC_RX1_I

#define REG_INPUTS_BC_RX1_I   0x1CD /* Inputs B&C RX1 I */

REG_INPUTS_BC_RX2_I

#define REG_INPUTS_BC_RX2_I   0x1CF /* Inputs B&C RX2 I */

REG_INPUTS_BC_RX2_Q

#define REG_INPUTS_BC_RX2_Q   0x1D0 /* Inputs B&C RX2 Q */

REG_INT_1_1ST_STAGE_CASCODE_CURRENT

#define REG_INT_1_1ST_STAGE_CASCODE_CURRENT   0x21A /* Int 1 1st Stage Cascode Current */

REG_INT_1_1ST_STAGE_CURRENT

#define REG_INT_1_1ST_STAGE_CURRENT   0x219 /* Int 1 1st Stage Current */

REG_INT_1_2ND_STAGE_CURRENT

#define REG_INT_1_2ND_STAGE_CURRENT   0x21B /* Int 1 2nd Stage Current */

REG_INT_1_FB_DAC_NMOS_CASOADE_BIAS_CURRENT

#define REG_INT_1_FB_DAC_NMOS_CASOADE_BIAS_CURRENT   0x210 /* Int 1 FB DAC NMOS Casoade Bias Current */

REG_INT_1_FB_DAC_NMOS_CURRENT_SOURCE

#define REG_INT_1_FB_DAC_NMOS_CURRENT_SOURCE   0x20F /* Int 1 FB DAC NMOS Current Source */

REG_INT_1_FB_DAC_PMOS_CURRENT_SOURCE

#define REG_INT_1_FB_DAC_PMOS_CURRENT_SOURCE   0x211 /* Int 1 FB DAC PMOS Current Source */

REG_INT_2_1ST_STAGE_CASCODE_CURRENT

#define REG_INT_2_1ST_STAGE_CASCODE_CURRENT   0x21D /* Int 2 1st Stage Cascode Current */

REG_INT_2_2ND_STAGE_CURRENT

#define REG_INT_2_2ND_STAGE_CURRENT   0x21E /* Int 2 2nd Stage Current */

REG_INT_2_FB_DAC_NMOS_CASCODE_BIAS_CURRENT

#define REG_INT_2_FB_DAC_NMOS_CASCODE_BIAS_CURRENT   0x213 /* Int 2 FB DAC NMOS Cascode Bias Current */

REG_INT_2_FB_DAC_NMOS_CURRENT_SOURCE

#define REG_INT_2_FB_DAC_NMOS_CURRENT_SOURCE   0x212 /* Int 2 FB DAC NMOS Current Source */

REG_INT_2_FB_DAC_PMOS_CURRENT_SOURCE

#define REG_INT_2_FB_DAC_PMOS_CURRENT_SOURCE   0x214 /* Int 2 FB DAC PMOS Current Source */

REG_INT_3_1ST_STAGE_CASCODE_CURRENT

#define REG_INT_3_1ST_STAGE_CASCODE_CURRENT   0x220 /* Int 3 1st Stage Cascode Current */

REG_INT_3_1ST_STAGE_CURRENT

#define REG_INT_3_1ST_STAGE_CURRENT   0x21F /* Int 3 1st Stage Current */

REG_INT_3_2ND_STAGE_CURRENT

#define REG_INT_3_2ND_STAGE_CURRENT   0x221 /* Int 3 2nd Stage Current */

REG_INT_3_FB_DAC_NMOS_CASCODE_BIAS_CURRENT

#define REG_INT_3_FB_DAC_NMOS_CASCODE_BIAS_CURRENT   0x216 /* Int 3 FB DAC NMOS Cascode Bias Current */

REG_INT_3_FB_DAC_NMOS_CURRENT_SOURCE

#define REG_INT_3_FB_DAC_NMOS_CURRENT_SOURCE   0x215 /* Int 3 FB DAC NMOS Current Source */

REG_INT_3_FB_DAC_PMOS_CURRENT_SOURCE

#define REG_INT_3_FB_DAC_PMOS_CURRENT_SOURCE   0x217 /* Int 3 FB DAC PMOS Current Source */

REG_INTEGER_BB_FREQ_WORD

#define REG_INTEGER_BB_FREQ_WORD   0x044 /* Integer BB Freq Word */

REG_INTEGRATOR_1_CAPACITANCE

#define REG_INTEGRATOR_1_CAPACITANCE   0x208 /* Integrator 1 Capacitance */

REG_INTEGRATOR_1_RESISTANCE

#define REG_INTEGRATOR_1_RESISTANCE   0x207 /* Integrator 1 Resistance */

REG_INTEGRATOR_23_RESISTANCE

#define REG_INTEGRATOR_23_RESISTANCE   0x209 /* Integrator 23 Resistance */

REG_INTEGRATOR_2_1ST_STAGE_CURRENT

#define REG_INTEGRATOR_2_1ST_STAGE_CURRENT   0x21C /* Integrator 2 1st Stage Current */

REG_INTEGRATOR_2_CAPACITANCE

#define REG_INTEGRATOR_2_CAPACITANCE   0x20B /* Integrator 2 Capacitance */

REG_INTEGRATOR_2_RESISTANCE

#define REG_INTEGRATOR_2_RESISTANCE   0x20A /* Integrator 2 Resistance */

REG_INTEGRATOR_3_CAPACITANCE

#define REG_INTEGRATOR_3_CAPACITANCE   0x20D /* Integrator 3 Capacitance */

REG_INTEGRATOR_3_RESISTANCE

#define REG_INTEGRATOR_3_RESISTANCE   0x20C /* Integrator 3 Resistance */

REG_INTEGRATOR_AMP_CC

#define REG_INTEGRATOR_AMP_CC   0x20E /* Integrator Amp Cc */

REG_INVERT_BITS

#define REG_INVERT_BITS   0x189 /* Invert Bits */

REG_KEXP_1

#define REG_KEXP_1   0x0A2 /* Kexp 1 */

REG_KEXP_2

#define REG_KEXP_2   0x0A3 /* Kexp 2 */

REG_LARGE_LMT_OVERLOAD_THRESH

#define REG_LARGE_LMT_OVERLOAD_THRESH   0x108 /* Large LMT Overload Threshold */

REG_LMT_OVERLOAD_COUNTERS

#define REG_LMT_OVERLOAD_COUNTERS   0x121 /* LMT Overload Counters */

REG_LNA_GAIN

#define REG_LNA_GAIN   0x15D /* LNA Gain */

REG_LNA_GAIN_DIFF_READ_BACK

#define REG_LNA_GAIN_DIFF_READ_BACK   0x144 /* LNA Gain Diff Read Back */

REG_LO_CM

#define REG_LO_CM   0x0D3 /* LO CM */

REG_LOOP_FILTER_1

#define REG_LOOP_FILTER_1   0x048 /* Loop Filter 1 */

REG_LOOP_FILTER_2

#define REG_LOOP_FILTER_2   0x049 /* Loop Filter 2 */

REG_LOOP_FILTER_3

#define REG_LOOP_FILTER_3   0x04A /* Loop Filter 3 */

REG_LPF_GAIN_RX1

#define REG_LPF_GAIN_RX1   0x2B1 /* LPF Gain Rx1 */

REG_LPF_GAIN_RX2

#define REG_LPF_GAIN_RX2   0x2B6 /* LPF Gain Rx2 */

REG_LVDS_BIAS_CTRL

#define REG_LVDS_BIAS_CTRL   0x03C /* LVDS Bias control */

REG_LVDS_INVERT_CTRL1

#define REG_LVDS_INVERT_CTRL1   0x03D /* LVDS Invert control1 */

REG_LVDS_INVERT_CTRL2

#define REG_LVDS_INVERT_CTRL2   0x03E /* LVDS Invert control2 */

REG_MAG_FTEST_THRESH

#define REG_MAG_FTEST_THRESH   0x0A5 /* Mag. Ftest Thresh */

REG_MAG_FTEST_THRESH_2

#define REG_MAG_FTEST_THRESH_2   0x0A6 /* Mag. Ftest Thresh 2 */

REG_MAX_LMT_FULL_GAIN

#define REG_MAX_LMT_FULL_GAIN   0x0FD /* Max LMT/Full Gain */

REG_MAX_MIXER_CALIBRATION_GAIN_INDEX

#define REG_MAX_MIXER_CALIBRATION_GAIN_INDEX   0x145 /* Max Mixer Calibration Gain Index */

REG_MEASURE_DURATION

#define REG_MEASURE_DURATION   0x148 /* Measure Duration */

REG_MEASURE_DURATION_01

#define REG_MEASURE_DURATION_01   0x150 /* Measure Duration 0&1 */

REG_MEASURE_DURATION_23

#define REG_MEASURE_DURATION_23   0x151 /* Measure Duration 2&3 */

REG_MISC_POWER_DOWN_OVERRIDE

#define REG_MISC_POWER_DOWN_OVERRIDE   0x058 /* Misc Power Down Override */

REG_MULTICHIP_SYNC_AND_TX_MON_CTRL

#define REG_MULTICHIP_SYNC_AND_TX_MON_CTRL   0x001 /* Multi-Chip Sync and Tx Mon Control */

REG_OBSERVE_CONFIG

#define REG_OBSERVE_CONFIG   0x3F5 /* Observe Config */

REG_OUTER_POWER_THRESHS

#define REG_OUTER_POWER_THRESHS   0x129 /* Outer Power Thresholds */

REG_OVRG_SIGS_RX1

#define REG_OVRG_SIGS_RX1   0x2B8 /* Ovrg Sigs Rx1 */

REG_OVRG_SIGS_RX2

#define REG_OVRG_SIGS_RX2   0x2B9 /* Ovrg Sigs Rx2 */

REG_PARALLEL_PORT_CONF_1

#define REG_PARALLEL_PORT_CONF_1   0x010 /* Parallel Port Configuration 1 */

REG_PARALLEL_PORT_CONF_2

#define REG_PARALLEL_PORT_CONF_2   0x011 /* Parallel Port Configuration 2 */

REG_PARALLEL_PORT_CONF_3

#define REG_PARALLEL_PORT_CONF_3   0x012 /* Parallel Port Configuration 3 */

REG_PEAK_WAIT_TIME

#define REG_PEAK_WAIT_TIME   0x0FE /* Peak Wait Time */

REG_POLE_GAIN

#define REG_POLE_GAIN   0x1FA /* Pole gain */

REG_PREAMBLE_LSB

#define REG_PREAMBLE_LSB   0x1AC /* Preamble LSB */

REG_PRODUCT_ID

#define REG_PRODUCT_ID   0x037 /* Product ID */

REG_QUAD_CAL_COUNT

#define REG_QUAD_CAL_COUNT   0x0A9 /* Quad cal Count */

REG_QUAD_CAL_CTRL

#define REG_QUAD_CAL_CTRL   0x0A1 /* Quad Cal Control */

REG_QUAD_CAL_NCO_FREQ_PHASE_OFFSET

#define REG_QUAD_CAL_NCO_FREQ_PHASE_OFFSET   0x0A0 /* Quad Cal NCO Freq & Phase Offset */

REG_QUAD_CAL_STATUS_TX1

#define REG_QUAD_CAL_STATUS_TX1   0x0A7 /* Quad cal status Tx1 */

REG_QUAD_CAL_STATUS_TX2

#define REG_QUAD_CAL_STATUS_TX2   0x0A8 /* Quad cal status Tx2 */

REG_QUAD_SETTLE_COUNT

#define REG_QUAD_SETTLE_COUNT   0x0A4 /* QUAD Settle count */

REG_REF_DIVIDE_CONFIG_1

#define REG_REF_DIVIDE_CONFIG_1   0x2AB /* Ref Divide Config 1 */

REG_REF_DIVIDE_CONFIG_2

#define REG_REF_DIVIDE_CONFIG_2   0x2AC /* Ref Divide Config 2 */

REG_REFERENCE_CLOCK_CYCLES

#define REG_REFERENCE_CLOCK_CYCLES   0x03A /* Reference Clock Cycles */

REG_RESET

#define REG_RESET   0x226 /* Reset */

REG_RESISTOR

#define REG_RESISTOR   0x0D1 /* Resistor */

REG_RF_CAL_GAIN_INDEX

#define REG_RF_CAL_GAIN_INDEX   0x18C /* RF Cal Gain Index */

REG_RF_DC_OFFSET_ATTEN

#define REG_RF_DC_OFFSET_ATTEN   0x188 /* RF DC Offset Attenuation */

REG_RF_DC_OFFSET_CONFIG_1

#define REG_RF_DC_OFFSET_CONFIG_1   0x187 /* RF DC Offset Config1 */

REG_RF_DC_OFFSET_COUNT

#define REG_RF_DC_OFFSET_COUNT   0x186 /* RF DC Offset Count */

REG_RFPLL_DIVIDERS

#define REG_RFPLL_DIVIDERS   0x005 /* RFPLL Dividers */

REG_RSSI_CONFIG

#define REG_RSSI_CONFIG   0x158 /* RSSI Config */

REG_RSSI_DELAY

#define REG_RSSI_DELAY   0x156 /* RSSI delay */

REG_RSSI_WAIT_TIME

#define REG_RSSI_WAIT_TIME   0x157 /* RSSI wait time */

REG_RSSI_WEIGHT_0

#define REG_RSSI_WEIGHT_0   0x152 /* RSSI Weight 0 */

REG_RSSI_WEIGHT_1

#define REG_RSSI_WEIGHT_1   0x153 /* RSSI Weight 1 */

REG_RSSI_WEIGHT_2

#define REG_RSSI_WEIGHT_2   0x154 /* RSSI Weight 2 */

REG_RSSI_WEIGHT_3

#define REG_RSSI_WEIGHT_3   0x155 /* RSSI Weight 3 */

REG_RX1_ADC_POWER_DOWN_OVERRIDE

#define REG_RX1_ADC_POWER_DOWN_OVERRIDE   0x054 /* Rx1 ADC Power Down Override */

REG_RX1_BB_DC_WORD_I_LSB

#define REG_RX1_BB_DC_WORD_I_LSB   0x19B /* RX1 BB DC word I LSB */

REG_RX1_BB_DC_WORD_I_MSB

#define REG_RX1_BB_DC_WORD_I_MSB   0x19A /* RX1 BB DC word I MSB */

REG_RX1_BB_DC_WORD_Q_LSB

#define REG_RX1_BB_DC_WORD_Q_LSB   0x19D /* RX1 BB DC word Q LSB */

REG_RX1_BB_DC_WORD_Q_MSB

#define REG_RX1_BB_DC_WORD_Q_MSB   0x19C /* RX1 BB DC word Q MSB */

REG_RX1_BBF_MAN_GAIN

#define REG_RX1_BBF_MAN_GAIN   0x1F4 /* Rx1 BBF Man Gain */

REG_RX1_BBF_R1A

#define REG_RX1_BBF_R1A   0x1E0 /* Rx1 BBF R1A */

REG_RX1_BBF_R5

#define REG_RX1_BBF_R5   0x1E4 /* Rx1 BBF R5 */

REG_RX1_INPUT_A_GAIN_CORR

#define REG_RX1_INPUT_A_GAIN_CORR   0x171 /* Rx1 Input A Gain Corr */

REG_RX1_INPUT_A_OFFSETS

#define REG_RX1_INPUT_A_OFFSETS   0x175 /* Rx1 Input A Offsets */

REG_RX1_INPUT_A_PHASE_CORR

#define REG_RX1_INPUT_A_PHASE_CORR   0x170 /* Rx1 Input A Phase Corr */

REG_RX1_INPUT_A_Q_OFFSET

#define REG_RX1_INPUT_A_Q_OFFSET   0x174 /* Rx1 Input A Q" Offset */

REG_RX1_INPUT_BC_GAIN_CORR

#define REG_RX1_INPUT_BC_GAIN_CORR   0x17A /* Rx1 Input B&C Gain Corr */

REG_RX1_INPUT_BC_OFFSETS

#define REG_RX1_INPUT_BC_OFFSETS   0x17E /* Rx1 Input B&C Offsets */

REG_RX1_INPUT_BC_PHASE_CORR

#define REG_RX1_INPUT_BC_PHASE_CORR   0x179 /* Rx1 Input B&C Phase Corr */

REG_RX1_INPUT_BC_Q_OFFSET

#define REG_RX1_INPUT_BC_Q_OFFSET   0x17D /* Rx1 Input B&C "Q" Offset */

REG_RX1_MANUAL_DIGITALFORCED_GAIN

#define REG_RX1_MANUAL_DIGITALFORCED_GAIN   0x10B /* Rx1 Manual Digital/Forced Gain */

REG_RX1_MANUAL_LMT_FULL_GAIN

#define REG_RX1_MANUAL_LMT_FULL_GAIN   0x109 /* Rx1 Manual LMT/Full Gain */

REG_RX1_MANUAL_LPF_GAIN

#define REG_RX1_MANUAL_LPF_GAIN   0x10A /* Rx1 Manual LPF gain */

REG_RX1_MIX_GM_BIAS_FORCE

#define REG_RX1_MIX_GM_BIAS_FORCE   0x1C2 /* Rx1 Mix Gm Bias (Force) */

REG_RX1_MIX_GM_FORCE

#define REG_RX1_MIX_GM_FORCE   0x1C1 /* Rx1 Mix Gm Force */

REG_RX1_RSSI_PREAMBLE

#define REG_RX1_RSSI_PREAMBLE   0x1A8 /* Rx1 RSSI preamble */

REG_RX1_RSSI_SYMBOL

#define REG_RX1_RSSI_SYMBOL   0x1A7 /* Rx1 RSSI Symbol */

REG_RX1_TUNE_CTRL

#define REG_RX1_TUNE_CTRL   0x1E2 /* Rx1 Tune Control */

REG_RX2_ADC_POWER_DOWN_OVERRIDE

#define REG_RX2_ADC_POWER_DOWN_OVERRIDE   0x055 /* Rx2 ADC Power Down Override */

REG_RX2_BB_DC_WORD_I_LSB

#define REG_RX2_BB_DC_WORD_I_LSB   0x19F /* RX2 BB DC word I LSB */

REG_RX2_BB_DC_WORD_I_MSB

#define REG_RX2_BB_DC_WORD_I_MSB   0x19E /* RX2 BB DC word I MSB */

REG_RX2_BB_DC_WORD_Q_LSB

#define REG_RX2_BB_DC_WORD_Q_LSB   0x1A1 /* RX2 BB DC word Q LSB */

REG_RX2_BB_DC_WORD_Q_MSB

#define REG_RX2_BB_DC_WORD_Q_MSB   0x1A0 /* RX2 BB DC word Q MSB */

REG_RX2_BBF_MAN_GAIN

#define REG_RX2_BBF_MAN_GAIN   0x1F5 /* Rx2 BBF Man Gain */

REG_RX2_BBF_R1A

#define REG_RX2_BBF_R1A   0x1E1 /* Rx2 BBF R1A */

REG_RX2_BBF_R5

#define REG_RX2_BBF_R5   0x1E5 /* Rx2 BBF R5 */

REG_RX2_INPUT_A_GAIN_CORR

#define REG_RX2_INPUT_A_GAIN_CORR   0x173 /* Rx2 Input A Gain Corr */

REG_RX2_INPUT_A_I_OFFSET

#define REG_RX2_INPUT_A_I_OFFSET   0x178 /* Rx2 Input A "I" Offset */

REG_RX2_INPUT_A_OFFSETS

#define REG_RX2_INPUT_A_OFFSETS   0x177 /* Rx2 Input A Offsets */

REG_RX2_INPUT_A_PHASE_CORR

#define REG_RX2_INPUT_A_PHASE_CORR   0x172 /* Rx2 Input A Phase Corr */

REG_RX2_INPUT_BC_GAIN_CORR

#define REG_RX2_INPUT_BC_GAIN_CORR   0x17C /* Rx2 Input B&C Gain Corr */

REG_RX2_INPUT_BC_I_OFFSET

#define REG_RX2_INPUT_BC_I_OFFSET   0x181 /* Rx2 Input B&C "I" Offset */

REG_RX2_INPUT_BC_OFFSETS

#define REG_RX2_INPUT_BC_OFFSETS   0x180 /* Rx2 Input B&C Offsets */

REG_RX2_INPUT_BC_PHASE_CORR

#define REG_RX2_INPUT_BC_PHASE_CORR   0x17B /* Rx2 Input B&C Phase Corr */

REG_RX2_MANUAL_DIGITALFORCED_GAIN

#define REG_RX2_MANUAL_DIGITALFORCED_GAIN   0x10E /* Rx2 Manual Digital/Forced Gain */

REG_RX2_MANUAL_LMT_FULL_GAIN

#define REG_RX2_MANUAL_LMT_FULL_GAIN   0x10C /* Rx2 Manual LMT/Full Gain */

REG_RX2_MANUAL_LPF_GAIN

#define REG_RX2_MANUAL_LPF_GAIN   0x10D /* Rx2 Manual LPF Gain */

REG_RX2_MIX_GM_BIAS_FORCE

#define REG_RX2_MIX_GM_BIAS_FORCE   0x1C4 /* Rx2 Mix Gm Bias (Force) */

REG_RX2_MIX_GM_FORCE

#define REG_RX2_MIX_GM_FORCE   0x1C3 /* Rx2 Mix Gm Force */

REG_RX2_RSSI_PREAMBLE

#define REG_RX2_RSSI_PREAMBLE   0x1AA /* Rx2 RSSI preamble */

REG_RX2_RSSI_SYMBOL

#define REG_RX2_RSSI_SYMBOL   0x1A9 /* Rx2 RSSI symbol */

REG_RX2_TUNE_CTRL

#define REG_RX2_TUNE_CTRL   0x1E3 /* Rx2 Tune Control */

REG_RX_ALC_VARACTOR

#define REG_RX_ALC_VARACTOR   0x239 /* RX ALC/Varactor */

REG_RX_ANALOG_POWER_DOWN_OVERRIDE_1

#define REG_RX_ANALOG_POWER_DOWN_OVERRIDE_1   0x052 /* Rx Analog Power Down Override 1 */

REG_RX_ANALOG_POWER_DOWN_OVERRIDE_2

#define REG_RX_ANALOG_POWER_DOWN_OVERRIDE_2   0x053 /* Rx Analog Power Down Override 2 */

REG_RX_BBBW_KHZ

#define REG_RX_BBBW_KHZ   0x1FC /* Rx BBBW kHz */

REG_RX_BBBW_MHZ

#define REG_RX_BBBW_MHZ   0x1FB /* Rx BBBW MHz */

REG_RX_BBF_C1_LSB

#define REG_RX_BBF_C1_LSB   0x1E8 /* Rx BBF C1 LSB */

REG_RX_BBF_C1_MSB

#define REG_RX_BBF_C1_MSB   0x1E7 /* Rx BBF C1 MSB */

REG_RX_BBF_C2_LSB

#define REG_RX_BBF_C2_LSB   0x1EA /* Rx BBF C2 LSB */

REG_RX_BBF_C2_MSB

#define REG_RX_BBF_C2_MSB   0x1E9 /* Rx BBF C2 MSB */

REG_RX_BBF_C3_LSB

#define REG_RX_BBF_C3_LSB   0x1EC /* Rx BBF C3 LSB */

REG_RX_BBF_C3_MSB

#define REG_RX_BBF_C3_MSB   0x1EB /* Rx BBF C3 MSB */

REG_RX_BBF_CC1_CTR

#define REG_RX_BBF_CC1_CTR   0x1ED /* Rx BBF CC1 Ctr */

REG_RX_BBF_CC2_CTR

#define REG_RX_BBF_CC2_CTR   0x1EF /* Rx BBF CC2 Ctr */

REG_RX_BBF_CC3_CTR

#define REG_RX_BBF_CC3_CTR   0x1F1 /* Rx BBF CC3 Ctr */

REG_RX_BBF_POW_RZ_BYTE0

#define REG_RX_BBF_POW_RZ_BYTE0   0x1EE /* Rx BBF Pow Rz Byte0 */

REG_RX_BBF_POW_RZ_BYTE1

#define REG_RX_BBF_POW_RZ_BYTE1   0x1F0 /* Rx BBF Pow Rz Byte1 */

REG_RX_BBF_R2346

#define REG_RX_BBF_R2346   0x1E6 /* Rx BBF R2346 */

REG_RX_BBF_R5_TUNE

#define REG_RX_BBF_R5_TUNE   0x1F2 /* Rx BBF R5 Tune */

REG_RX_BBF_TUNE

#define REG_RX_BBF_TUNE   0x1F3 /* Rx BBF Tune */

REG_RX_BBF_TUNE_CONFIG

#define REG_RX_BBF_TUNE_CONFIG   0x1F9 /* RX BBF Tune Config */

REG_RX_BBF_TUNE_DIVIDE

#define REG_RX_BBF_TUNE_DIVIDE   0x1F8 /* RX BBF Tune Divide */

REG_RX_CAL_STATUS

#define REG_RX_CAL_STATUS   0x244 /* RX Cal Status */

REG_RX_CGB_SEG_ENABLE

#define REG_RX_CGB_SEG_ENABLE   0x1D6 /* Rx CGB Seg Enable */

REG_RX_CLOCK_DATA_DELAY

#define REG_RX_CLOCK_DATA_DELAY   0x006 /* Rx Clock & Data Delay */

REG_RX_CORRECTION_WORD0

#define REG_RX_CORRECTION_WORD0   0x24E /* RX Correction Word0 */

REG_RX_CORRECTION_WORD1

#define REG_RX_CORRECTION_WORD1   0x24F /* RX Correction Word1 */

REG_RX_CP_CONFIG

#define REG_RX_CP_CONFIG   0x23D /* RX CP Config */

REG_RX_CP_CURRENT

#define REG_RX_CP_CURRENT   0x23B /* RX CP Current */

REG_RX_CP_LEVEL_DETECT

#define REG_RX_CP_LEVEL_DETECT   0x24B /* RX CP Level Detect */

REG_RX_CP_OFFSET

#define REG_RX_CP_OFFSET   0x23C /* RX CP Offset */

REG_RX_CP_OVERRANGE_VCO_LOCK

#define REG_RX_CP_OVERRANGE_VCO_LOCK   0x247 /* RX CP Over Range/VCO Lock */

REG_RX_DIFF_LNA_FORCE

#define REG_RX_DIFF_LNA_FORCE   0x1B0 /* Rx Diff LNA Force */

REG_RX_DITHERCP_CAL

#define REG_RX_DITHERCP_CAL   0x241 /* RX Dither/CP Cal */

REG_RX_DSM_SETUP_0

#define REG_RX_DSM_SETUP_0   0x24C /* RX DSM Setup 0 */

REG_RX_DSM_SETUP_1

#define REG_RX_DSM_SETUP_1   0x24D /* RX DSM Setup 1 */

REG_RX_ENABLE_FILTER_CTRL

#define REG_RX_ENABLE_FILTER_CTRL   0x003 /* Rx Enable & Filter Control */

REG_RX_FAST_LOCK_PROGRAM_ADDR

#define REG_RX_FAST_LOCK_PROGRAM_ADDR   0x25C /* Rx Fast Lock Program Addr */

REG_RX_FAST_LOCK_PROGRAM_CTRL

#define REG_RX_FAST_LOCK_PROGRAM_CTRL   0x25F /* Rx Fast Lock Program Control */

REG_RX_FAST_LOCK_PROGRAM_DATA

#define REG_RX_FAST_LOCK_PROGRAM_DATA   0x25D /* Rx Fast Lock Program Data */

REG_RX_FAST_LOCK_PROGRAM_READ

#define REG_RX_FAST_LOCK_PROGRAM_READ   0x25E /* Rx Fast Lock Program Read */

REG_RX_FAST_LOCK_SETUP

#define REG_RX_FAST_LOCK_SETUP   0x25A /* Rx Fast Lock Setup */

REG_RX_FAST_LOCK_SETUP_INIT_DELAY

#define REG_RX_FAST_LOCK_SETUP_INIT_DELAY   0x25B /* Rx Fast Lock Setup Init Delay */

REG_RX_FILTER_COEF_ADDR

#define REG_RX_FILTER_COEF_ADDR   0x0F0 /* Rx Filter Coeff Addr */

REG_RX_FILTER_COEF_DATA_1

#define REG_RX_FILTER_COEF_DATA_1   0x0F1 /* Rx Filter Coeff Data 1 */

REG_RX_FILTER_COEF_DATA_2

#define REG_RX_FILTER_COEF_DATA_2   0x0F2 /* Rx Filter Coeff Data 2 */

REG_RX_FILTER_COEF_READ_DATA_1

#define REG_RX_FILTER_COEF_READ_DATA_1   0x0F3 /* Rx Filter Coeff Read Data 1 */

REG_RX_FILTER_COEF_READ_DATA_2

#define REG_RX_FILTER_COEF_READ_DATA_2   0x0F4 /* Rx Filter Coeff Read Data 2 */

REG_RX_FILTER_CONFIG

#define REG_RX_FILTER_CONFIG   0x0F5 /* Rx Filter Config */

REG_RX_FILTER_GAIN

#define REG_RX_FILTER_GAIN   0x0F6 /* Rx Filter Gain */

REG_RX_FORCE_ALC

#define REG_RX_FORCE_ALC   0x236 /* RX Force ALC */

REG_RX_FORCE_VCO_TUNE_0

#define REG_RX_FORCE_VCO_TUNE_0   0x237 /* RX Force VCO Tune 0 */

REG_RX_FORCE_VCO_TUNE_1

#define REG_RX_FORCE_VCO_TUNE_1   0x238 /* RX Force VCO Tune 1 */

REG_RX_FRACT_BYTE_0

#define REG_RX_FRACT_BYTE_0   0x233 /* RX Fractional Byte 0 */

REG_RX_FRACT_BYTE_1

#define REG_RX_FRACT_BYTE_1   0x234 /* RX Fractional Byte 1 */

REG_RX_FRACT_BYTE_2

#define REG_RX_FRACT_BYTE_2   0x235 /* RX Fractional Byte 2 */

REG_RX_INTEGER_BYTE_0

#define REG_RX_INTEGER_BYTE_0   0x231 /* RX Integer Byte 0 */

REG_RX_INTEGER_BYTE_1

#define REG_RX_INTEGER_BYTE_1   0x232 /* RX Integer Byte 1 */

REG_RX_LNA_BIAS_COARSE

#define REG_RX_LNA_BIAS_COARSE   0x1B1 /* Rx LNA Bias Coarse */

REG_RX_LNA_BIAS_FINE_0

#define REG_RX_LNA_BIAS_FINE_0   0x1B2 /* Rx LNA Bias Fine 0 */

REG_RX_LNA_BIAS_FINE_1

#define REG_RX_LNA_BIAS_FINE_1   0x1B3 /* Rx LNA Bias Fine 1 */

REG_RX_LO_GEN_POWER_MODE

#define REG_RX_LO_GEN_POWER_MODE   0x261 /* Rx LO Gen Power Mode */

REG_RX_LOAD_SYNTH_DELAY

#define REG_RX_LOAD_SYNTH_DELAY   0x024 /* RX Load Synth Delay */

REG_RX_LOCK_DETECT_CONFIG

#define REG_RX_LOCK_DETECT_CONFIG   0x24A /* RX Lock Detect Config */

REG_RX_LOOP_FILTER_1

#define REG_RX_LOOP_FILTER_1   0x23E /* RX Loop Filter 1 */

REG_RX_LOOP_FILTER_2

#define REG_RX_LOOP_FILTER_2   0x23F /* RX Loop Filter 2 */

REG_RX_LOOP_FILTER_3

#define REG_RX_LOOP_FILTER_3   0x240 /* RX Loop Filter 3 */

REG_RX_MIX_GM_CONFIG

#define REG_RX_MIX_GM_CONFIG   0x1C0 /* Rx Mix Gm Config */

REG_RX_MIX_INPUTBIAS

#define REG_RX_MIX_INPUTBIAS   0x1D7 /* Rx Mix Input/Bias */

REG_RX_MIX_LO_CM

#define REG_RX_MIX_LO_CM   0x1D5 /* Rx Mix LO CM */

REG_RX_PATH_GAIN_LSB

#define REG_RX_PATH_GAIN_LSB   0x1AE /* Rx Path Gain */

REG_RX_PATH_GAIN_MSB

#define REG_RX_PATH_GAIN_MSB   0x1AD /* Rx Path Gain */

REG_RX_PFD_CONFIG

#define REG_RX_PFD_CONFIG   0x230 /* RX PFD Config */

REG_RX_QUAD_CAL_LEVEL

#define REG_RX_QUAD_CAL_LEVEL   0x168 /* Rx Quad Cal Level */

REG_RX_QUAD_GAIN1

#define REG_RX_QUAD_GAIN1   0x16E /* Rx Quad gain1 */

REG_RX_QUAD_GAIN2

#define REG_RX_QUAD_GAIN2   0x16F /* Rx Quad gain2 */

REG_RX_SYNTH_POWER_DOWN_OVERRIDE

#define REG_RX_SYNTH_POWER_DOWN_OVERRIDE   0x050 /* Rx Synth Power Down Override */

REG_RX_TIA_CONFIG

#define REG_RX_TIA_CONFIG   0x1DB /* Rx TIA Config */

REG_RX_VCO_BIAS_1

#define REG_RX_VCO_BIAS_1   0x242 /* RX VCO Bias 1 */

REG_RX_VCO_CAL

#define REG_RX_VCO_CAL   0x249 /* RX VCO Cal */

REG_RX_VCO_CAL_REF

#define REG_RX_VCO_CAL_REF   0x245 /* RX VCO Cal Ref */

REG_RX_VCO_LDO

#define REG_RX_VCO_LDO   0x248 /* RX VCO LDO */

REG_RX_VCO_OUTPUT

#define REG_RX_VCO_OUTPUT   0x23A /* RX VCO Output */

REG_RX_VCO_PD_OVERRIDES

#define REG_RX_VCO_PD_OVERRIDES   0x246 /* RX VCO Pd Overrides */

REG_RX_VCO_VARACTOR_CTRL_0

#define REG_RX_VCO_VARACTOR_CTRL_0   0x250 /* RX VCO Varactor Control 0 */

REG_RX_VCO_VARACTOR_CTRL_1

#define REG_RX_VCO_VARACTOR_CTRL_1   0x251 /* RX VCO Varactor Control 1 */

REG_SDM_CTRL

#define REG_SDM_CTRL   0x04E /* SDM Control */

REG_SDM_CTRL_1

#define REG_SDM_CTRL_1   0x03F /* SDM Control 1 */

REG_SETTLE_COUNT

#define REG_SETTLE_COUNT   0x16D /* Settle count */

REG_SETTLE_TIME

#define REG_SETTLE_TIME   0x147 /* Settle Time */

REG_SLOW_LOOP_STATE

#define REG_SLOW_LOOP_STATE   0x2B4 /* Slow Loop State */

REG_SMALL_LMT_OVERLOAD_THRESH

#define REG_SMALL_LMT_OVERLOAD_THRESH   0x107 /* Small LMT Overload Threshold */

REG_SOI_THRESH

#define REG_SOI_THRESH   0x18D /* SOI Threshold */

REG_SPI_CONF

#define REG_SPI_CONF   0x000 /* SPI Configuration */

REG_SQUARER_CONFIG

#define REG_SQUARER_CONFIG   0x0AB /* Squarer Config */

REG_START_TEMP_READING

#define REG_START_TEMP_READING   0x00C /* Start Temp Reading */

REG_STATE

#define REG_STATE   0x017 /* State */

REG_SYMBOL_LSB

#define REG_SYMBOL_LSB   0x1AB /* Symbol LSB */

REG_TEMP_GAIN_COEF

#define REG_TEMP_GAIN_COEF   0x146 /* Temp Gain Coefficient */

REG_TEMP_OFFSET

#define REG_TEMP_OFFSET   0x00B /* Offset */

REG_TEMP_SENSE2

#define REG_TEMP_SENSE2   0x00D /* Temp Sense2 */

REG_TEMP_SENSOR_CONFIG

#define REG_TEMP_SENSOR_CONFIG   0x00F /* Temp Sensor Config */

REG_TEMPERATURE

#define REG_TEMPERATURE   0x00E /* Temperature */

REG_TEST_MUX_2I

#define REG_TEST_MUX_2I   0x205 /* Test MUX 2i */

REG_TEST_MUX_2Q

#define REG_TEST_MUX_2Q   0x206 /* Test MUX 2q */

REG_THRESH_ACCUM

#define REG_THRESH_ACCUM   0x0AD /* Thresh Accum */

REG_TIA1_C_LSB

#define REG_TIA1_C_LSB   0x1DC /* TIA1 C LSB */

REG_TIA1_C_MSB

#define REG_TIA1_C_MSB   0x1DD /* TIA1 C MSB */

REG_TIA2_C_LSB

#define REG_TIA2_C_LSB   0x1DE /* TIA2 C LSB */

REG_TIA2_C_MSB

#define REG_TIA2_C_MSB   0x1DF /* TIA2 C MSB */

REG_TPM_MODE_ENABLE

#define REG_TPM_MODE_ENABLE   0x06E /* TPM Mode Enable */

REG_TX1_ATTEN_0

#define REG_TX1_ATTEN_0   0x073 /* Tx1 Atten 0 */

REG_TX1_ATTEN_1

#define REG_TX1_ATTEN_1   0x074 /* Tx1 Atten 1 */

REG_TX1_DIG_ATTEN

#define REG_TX1_DIG_ATTEN   0x079 /* Tx1 Dig Attenuation */

REG_TX1_OUT_1_GAIN_CORR

#define REG_TX1_OUT_1_GAIN_CORR   0x08F /* Tx1 Out 1 Gain Corr */

REG_TX1_OUT_1_OFFSET_I

#define REG_TX1_OUT_1_OFFSET_I   0x092 /* Tx1 Out 1 Offset I */

REG_TX1_OUT_1_OFFSET_Q

#define REG_TX1_OUT_1_OFFSET_Q   0x093 /* Tx1 Out 1 Offset Q */

REG_TX1_OUT_1_PHASE_CORR

#define REG_TX1_OUT_1_PHASE_CORR   0x08E /* Tx1 Out 1 Phase Corr */

REG_TX1_OUT_2_GAIN_CORR

#define REG_TX1_OUT_2_GAIN_CORR   0x097 /* Tx1 Out 2 Gain Corr */

REG_TX1_OUT_2_OFFSET_I

#define REG_TX1_OUT_2_OFFSET_I   0x09A /* Tx1 Out 2 Offset I */

REG_TX1_OUT_2_OFFSET_Q

#define REG_TX1_OUT_2_OFFSET_Q   0x09B /* Tx1 Out 2 Offset Q */

REG_TX1_OUT_2_PHASE_CORR

#define REG_TX1_OUT_2_PHASE_CORR   0x096 /* Tx1 Out 2 Phase Corr */

REG_TX1_SYMBOL_ATTEN

#define REG_TX1_SYMBOL_ATTEN   0x07F /* TX1 Symbol Attenuation */

REG_TX2_ATTEN_0

#define REG_TX2_ATTEN_0   0x075 /* Tx2 Atten 0 */

REG_TX2_ATTEN_1

#define REG_TX2_ATTEN_1   0x076 /* Tx2 Atten 1 */

REG_TX2_DIG_ATTEN

#define REG_TX2_DIG_ATTEN   0x07C /* Tx2 Dig Attenuation */

REG_TX2_OUT_1_GAIN_CORR

#define REG_TX2_OUT_1_GAIN_CORR   0x091 /* Tx2 Out 1 Gain Corr */

REG_TX2_OUT_1_OFFSET_I

#define REG_TX2_OUT_1_OFFSET_I   0x094 /* Tx2 Out 1 Offset I */

REG_TX2_OUT_1_OFFSET_Q

#define REG_TX2_OUT_1_OFFSET_Q   0x095 /* Tx2 Out 1 Offset Q */

REG_TX2_OUT_1_PHASE_CORR

#define REG_TX2_OUT_1_PHASE_CORR   0x090 /* Tx2 Out 1 Phase Corr */

REG_TX2_OUT_2_GAIN_CORR

#define REG_TX2_OUT_2_GAIN_CORR   0x099 /* Tx2 Out 2 Gain Corr */

REG_TX2_OUT_2_OFFSET_I

#define REG_TX2_OUT_2_OFFSET_I   0x09C /* Tx2 Out 2 Offset I */

REG_TX2_OUT_2_OFFSET_Q

#define REG_TX2_OUT_2_OFFSET_Q   0x09D /* Tx2 Out 2 Offset Q */

REG_TX2_OUT_2_PHASE_CORR

#define REG_TX2_OUT_2_PHASE_CORR   0x098 /* Tx2 Out 2 Phase Corr */

REG_TX2_SYMBOL_ATTEN

#define REG_TX2_SYMBOL_ATTEN   0x080 /* TX2 Symbol Attenuation */

REG_TX_ALCVARACT_OR

#define REG_TX_ALCVARACT_OR   0x279 /* TX ALC/Varact or */

REG_TX_ANALOG_POWER_DOWN_OVERRIDE_1

#define REG_TX_ANALOG_POWER_DOWN_OVERRIDE_1   0x056 /* Tx Analog Power Down Override 1 */

REG_TX_ATTEN_OFFSET

#define REG_TX_ATTEN_OFFSET   0x077 /* Tx Atten Offset */

REG_TX_ATTEN_THRESH

#define REG_TX_ATTEN_THRESH   0x078 /* Tx Atten Threshold */

REG_TX_BBF_C1

#define REG_TX_BBF_C1   0x0C7 /* Tx BBF C1 */

REG_TX_BBF_C2

#define REG_TX_BBF_C2   0x0C8 /* Tx BBF C2 */

REG_TX_BBF_CP

#define REG_TX_BBF_CP   0x0C9 /* Tx BBF Cp */

REG_TX_BBF_R1

#define REG_TX_BBF_R1   0x0C2 /* Tx BBF R1 */

REG_TX_BBF_R2

#define REG_TX_BBF_R2   0x0C3 /* Tx BBF R2 */

REG_TX_BBF_R2B

#define REG_TX_BBF_R2B   0x0CB /* Tx BBF R2b */

REG_TX_BBF_R3

#define REG_TX_BBF_R3   0x0C4 /* Tx BBF R3 */

REG_TX_BBF_R4

#define REG_TX_BBF_R4   0x0C5 /* Tx BBF R4 */

REG_TX_BBF_RP

#define REG_TX_BBF_RP   0x0C6 /* Tx BBF RP */

REG_TX_BBF_TUNE

#define REG_TX_BBF_TUNE   0x0CC /* Tx BBF Tune */

REG_TX_BBF_TUNE_DIVIDER

#define REG_TX_BBF_TUNE_DIVIDER   0x0D6 /* TX BBF Tune Divider */

REG_TX_BBF_TUNE_MODE

#define REG_TX_BBF_TUNE_MODE   0x0D7 /* TX BBF Tune Mode */

REG_TX_CAL_STATUS

#define REG_TX_CAL_STATUS   0x284 /* TX Cal Status */

REG_TX_CLOCK_DATA_DELAY

#define REG_TX_CLOCK_DATA_DELAY   0x007 /* Tx Clock & Data Delay */

REG_TX_CORRECTION_WORD0

#define REG_TX_CORRECTION_WORD0   0x28E /* TX Correction Word0 */

REG_TX_CORRECTION_WORD1

#define REG_TX_CORRECTION_WORD1   0x28F /* TX Correction Word1 */

REG_TX_CP_CONFIG

#define REG_TX_CP_CONFIG   0x27D /* TX CP Config */

REG_TX_CP_CURRENT

#define REG_TX_CP_CURRENT   0x27B /* TX CP Current */

REG_TX_CP_LEVEL_DETECT

#define REG_TX_CP_LEVEL_DETECT   0x28B /* TX CP Level Detect */

REG_TX_CP_OFFSET

#define REG_TX_CP_OFFSET   0x27C /* TX CP Offset */

REG_TX_CP_OVERRANGE_VCO_LOCK

#define REG_TX_CP_OVERRANGE_VCO_LOCK   0x287 /* TX CP Over Range/VCO Lock */

REG_TX_DITHERCP_CAL

#define REG_TX_DITHERCP_CAL   0x281 /* TX Dither/CP Cal */

REG_TX_DSM_SETUP_0

#define REG_TX_DSM_SETUP_0   0x28C /* TX DSM Setup 0 */

REG_TX_DSM_SETUP_1

#define REG_TX_DSM_SETUP_1   0x28D /* TX DSM Setup 1 */

REG_TX_ENABLE_FILTER_CTRL

#define REG_TX_ENABLE_FILTER_CTRL   0x002 /* Tx Enable & Filter Control */

REG_TX_FAST_LOCK_PROGRAM_ADDR

#define REG_TX_FAST_LOCK_PROGRAM_ADDR   0x29C /* Tx Fast Lock Program Addr */

REG_TX_FAST_LOCK_PROGRAM_CTRL

#define REG_TX_FAST_LOCK_PROGRAM_CTRL   0x29F /* Tx Fast Lock Program Ctrl */

REG_TX_FAST_LOCK_PROGRAM_DATA

#define REG_TX_FAST_LOCK_PROGRAM_DATA   0x29D /* Tx Fast Lock Program Data */

REG_TX_FAST_LOCK_PROGRAM_READ

#define REG_TX_FAST_LOCK_PROGRAM_READ   0x29E /* Tx Fast Lock Program Read */

REG_TX_FAST_LOCK_SETUP

#define REG_TX_FAST_LOCK_SETUP   0x29A /* Tx Fast Lock Setup */

REG_TX_FAST_LOCK_SETUP_INIT_DELAY

#define REG_TX_FAST_LOCK_SETUP_INIT_DELAY   0x29B /* Tx Fast Lock Setup Init Delay */

REG_TX_FILTER_COEF_ADDR

#define REG_TX_FILTER_COEF_ADDR   0x060 /* TX Filter Coefficient Address */

REG_TX_FILTER_COEF_READ_DATA_1

#define REG_TX_FILTER_COEF_READ_DATA_1   0x063 /* TX Filter Coefficient Read Data 1 */

REG_TX_FILTER_COEF_READ_DATA_2

#define REG_TX_FILTER_COEF_READ_DATA_2   0x064 /* TX Filter Coefficient Read Data 2 */

REG_TX_FILTER_COEF_WRITE_DATA_1

#define REG_TX_FILTER_COEF_WRITE_DATA_1   0x061 /* TX Filter Coefficient Write Data 1 */

REG_TX_FILTER_COEF_WRITE_DATA_2

#define REG_TX_FILTER_COEF_WRITE_DATA_2   0x062 /* TX Filter Coefficient Write Data 2 */

REG_TX_FILTER_CONF

#define REG_TX_FILTER_CONF   0x065 /* TX Filter Configuration */

REG_TX_FORCE_ALC

#define REG_TX_FORCE_ALC   0x276 /* TX Force ALC */

REG_TX_FORCE_BITS

#define REG_TX_FORCE_BITS   0x09F /* Force Bits */

REG_TX_FORCE_VCO_TUNE_0

#define REG_TX_FORCE_VCO_TUNE_0   0x277 /* TX Force VCO Tune 0 */

REG_TX_FORCE_VCO_TUNE_1

#define REG_TX_FORCE_VCO_TUNE_1   0x278 /* TX Force VCO Tune 1 */

REG_TX_FRACT_BYTE_0

#define REG_TX_FRACT_BYTE_0   0x273 /* TX Fractional Byte 0 */

REG_TX_FRACT_BYTE_1

#define REG_TX_FRACT_BYTE_1   0x274 /* TX Fractional Byte 1 */

REG_TX_FRACT_BYTE_2

#define REG_TX_FRACT_BYTE_2   0x275 /* TX Fractional Byte 2 */

REG_TX_INTEGER_BYTE_0

#define REG_TX_INTEGER_BYTE_0   0x271 /* TX Integer Byte 0 */

REG_TX_INTEGER_BYTE_1

#define REG_TX_INTEGER_BYTE_1   0x272 /* TX Integer Byte 1 */

REG_TX_LEVEL_THRESH

#define REG_TX_LEVEL_THRESH   0x06A /* Tx Level Threshold */

REG_TX_LO_GEN_POWER_MODE

#define REG_TX_LO_GEN_POWER_MODE   0x2A1 /* Tx LO Gen Power Mode */

REG_TX_LOAD_SYNTH_DELAY

#define REG_TX_LOAD_SYNTH_DELAY   0x025 /* TX Load Synth Delay */

REG_TX_LOCK_DETECT_CONFIG

#define REG_TX_LOCK_DETECT_CONFIG   0x28A /* TX Lock Detect Config */

REG_TX_LOOP_FILTER_1

#define REG_TX_LOOP_FILTER_1   0x27E /* TX Loop Filter 1 */

REG_TX_LOOP_FILTER_2

#define REG_TX_LOOP_FILTER_2   0x27F /* TX Loop Filter 2 */

REG_TX_LOOP_FILTER_3

#define REG_TX_LOOP_FILTER_3   0x280 /* TX Loop Filter 3 */

REG_TX_MON_1_CONFIG

#define REG_TX_MON_1_CONFIG   0x070 /* Tx Mon 1 Config */

REG_TX_MON_2_CONFIG

#define REG_TX_MON_2_CONFIG   0x071 /* Tx Mon 2 Config */

REG_TX_MON_DELAY

#define REG_TX_MON_DELAY   0x069 /* Tx Mon Delay */

REG_TX_MON_HIGH_GAIN

#define REG_TX_MON_HIGH_GAIN   0x068 /* Tx Mon High Gain */

REG_TX_MON_LOW_GAIN

#define REG_TX_MON_LOW_GAIN   0x067 /* Tx Mon Low Gain */

REG_TX_MON_TEMP_GAIN_COEF

#define REG_TX_MON_TEMP_GAIN_COEF   0x06F /* Temp Gain Coefficient */

REG_TX_PFD_CONFIG

#define REG_TX_PFD_CONFIG   0x270 /* TX PFD Config */

REG_TX_QUAD_CAL_ATTEN

#define REG_TX_QUAD_CAL_ATTEN   0x0AC /* TX Quad Cal Atten */

REG_TX_QUAD_FULL_LMT_GAIN

#define REG_TX_QUAD_FULL_LMT_GAIN   0x0AA /* Tx Quad Full/LMT Gain */

REG_TX_QUAD_LPF_GAIN

#define REG_TX_QUAD_LPF_GAIN   0x0AE /* Tx Quad LPF Gain */

REG_TX_RSSI1

#define REG_TX_RSSI1   0x06B /* TX RSSI1 */

REG_TX_RSSI2

#define REG_TX_RSSI2   0x06C /* TX RSSI2 */

REG_TX_RSSI_LSB

#define REG_TX_RSSI_LSB   0x06D /* TX RSSI LSB */

REG_TX_SYMBOL_ATTEN_CONFIG

#define REG_TX_SYMBOL_ATTEN_CONFIG   0x081 /* TX Symbol Atten Config */

REG_TX_SYNTH_POWER_DOWN_OVERRIDE

#define REG_TX_SYNTH_POWER_DOWN_OVERRIDE   0x051 /* TX Synth Power Down Override */

REG_TX_TUNE_CTRL

#define REG_TX_TUNE_CTRL   0x0CA /* Tx Tune Control */

REG_TX_VCO_BIAS_1

#define REG_TX_VCO_BIAS_1   0x282 /* TX VCO Bias 1 */

REG_TX_VCO_BIAS_2

#define REG_TX_VCO_BIAS_2   0x283 /* TX VCO Bias 2 */

REG_TX_VCO_CAL

#define REG_TX_VCO_CAL   0x289 /* TX VCO Cal */

REG_TX_VCO_CAL_REF

#define REG_TX_VCO_CAL_REF   0x285 /* TX VCO Cal Ref */

REG_TX_VCO_LDO

#define REG_TX_VCO_LDO   0x288 /* TX VCO LDO */

REG_TX_VCO_OUTPUT

#define REG_TX_VCO_OUTPUT   0x27A /* TX VCO Output */

REG_TX_VCO_PD_OVERRIDES

#define REG_TX_VCO_PD_OVERRIDES   0x286 /* TX VCO Pd Overrides */

REG_TX_VCO_VARACTOR_CTRL_0

#define REG_TX_VCO_VARACTOR_CTRL_0   0x290 /* TX VCO Varactor Control 0 */

REG_TX_VCO_VARACTOR_CTRL_1

#define REG_TX_VCO_VARACTOR_CTRL_1   0x291 /* TX VCO Varactor Control 1 */

REG_TXBBF_OPAMP_A

#define REG_TXBBF_OPAMP_A   0x0C0 /* TxBBF OpAmp A */

REG_TXBBF_OPAMP_B

#define REG_TXBBF_OPAMP_B   0x0C1 /* TxBBF OpAmp B */

REG_TXDAC_GN_I

#define REG_TXDAC_GN_I   0x0B2 /* TxDAC gn I */

REG_TXDAC_GN_Q

#define REG_TXDAC_GN_Q   0x0B3 /* TxDAC gn Q */

REG_TXDAC_VDS_I

#define REG_TXDAC_VDS_I   0x0B0 /* TxDAC Vds I */

REG_TXDAC_VDS_Q

#define REG_TXDAC_VDS_Q   0x0B1 /* TxDAC Vds Q */

REG_VCO_CTRL

#define REG_VCO_CTRL   0x04B /* VCO Control */

REG_VCO_PROGRAM_1

#define REG_VCO_PROGRAM_1   0x04C

REG_VCO_PROGRAM_2

#define REG_VCO_PROGRAM_2   0x04D

REG_WAIT_COUNT

#define REG_WAIT_COUNT   0x185 /* Wait Count */

REG_WORD_ADDRESS

#define REG_WORD_ADDRESS   0x140 /* Word Address */

RESET_ACC_ON_GAIN_CHANGE

#define RESET_ACC_ON_GAIN_CHANGE   (1 << 4) /* Reset Acc on Gain Change */

RESISTOR

#define RESISTOR

(

x

)

Value:

(((x) & 0xF) << 0) /* Resistor<3:0> */

REV_MASK

#define REV_MASK   0x07

RF_DC_CAL

#define RF_DC_CAL   (1 << 5) /* RF DC Cal */

RF_DC_CALIBRATION_COUNT

#define RF_DC_CALIBRATION_COUNT

(

x

)

Value:

(((x) & 0xF) << 0) /* RF DC Calibration Count<3:0> */

RF_DC_OFFSET_ATTEN

#define RF_DC_OFFSET_ATTEN

(

x

)

Value:

(((x) & 0x1F) << 0) /* RF DC Offset Attenuation<4:0> */

RF_DC_OFFSET_TABLE_UPDATE_COUNT

#define RF_DC_OFFSET_TABLE_UPDATE_COUNT

(

x

)

Value:

(((x) & 0x7) << 5) /* RF DC Offset Table Update Count<2:0> */

RF_MINIMUM_CALIBRATION_GAIN_INDEX

#define RF_MINIMUM_CALIBRATION_GAIN_INDEX

(

x

)

Value:

(((x) & 0x7F) << 0) /* RF Minimum Calibration Gain Index<6:0> */

RF_SOI_THRESH

#define RF_SOI_THRESH

(

x

)

Value:

(((x) & 0x7F) << 0) /* RF SOI Threshold<6:0> */

RFDC_CAL

#define RFDC_CAL   (1 << 1) /* DC Cal RF Start */

RFIR_FOR_RSSI_MEASUREMENT

#define RFIR_FOR_RSSI_MEASUREMENT

(

x

)

Value:

(((x) & 0x3) << 6) /* RFIR for RSSI measurement<1:0> */

RFPLL_MODULUS

#define RFPLL_MODULUS   8388593UL

RGM

#define RGM

(

x

)

Value:

(((x) & 0x3) << 4) /* Rgm<1:0> */

RHB1_EN

#define RHB1_EN   (1 << 2) /* RHB1 Enable */

RHB2_EN

#define RHB2_EN   (1 << 3) /* RHB2 Enable */

RP

#define RP

(

x

)

Value:

(((x) & 0x1F) << 0) /* Rp<4:0> */

RSSI_LSB_MASK1

#define RSSI_LSB_MASK1   0x01

RSSI_LSB_MASK2

#define RSSI_LSB_MASK2   0x02

RSSI_LSB_SHIFT

#define RSSI_LSB_SHIFT   1

RSSI_MAX_WEIGHT

#define RSSI_MAX_WEIGHT   255

RSSI_MODE_SELECT

#define RSSI_MODE_SELECT

(

x

)

Value:

(((x) & 0x7) << 2) /* RSSI Mode Select<2:0> */

RSSI_MULTIPLIER

#define RSSI_MULTIPLIER   100

RSSI_RESOLUTION

#define RSSI_RESOLUTION   ((int) (0.25 * RSSI_MULTIPLIER))

RX1_BB_DC_OFFSET_CORRECTION_WORD_I

#define RX1_BB_DC_OFFSET_CORRECTION_WORD_I

(

x

)

Value:

(((x) & 0x7F) << 0) /* RX1 BB DC Offset Correction word I<14:8> */

RX1_BB_DC_OFFSET_CORRECTION_WORD_Q

#define RX1_BB_DC_OFFSET_CORRECTION_WORD_Q

(

x

)

Value:

(((x) & 0x7F) << 0) /* RX1 BB DC Offset Correction word Q<14:8> */

RX1_BBF_BQ_GAIN

#define RX1_BBF_BQ_GAIN

(

x

)

Value:

(((x) & 0x3) << 3) /* Rx1 BBF BQ Gain<1:0> */

RX1_BBF_FORCE_GAIN

#define RX1_BBF_FORCE_GAIN   (1 << 5) /* Rx1 BBF Force Gain */

RX1_BBF_POLE_GAIN

#define RX1_BBF_POLE_GAIN

(

x

)

Value:

(((x) & 0x7) << 0) /* Rx1 BBF Pole Gain<2:0> */

RX1_BBF_POW_CTR

#define RX1_BBF_POW_CTR

(

x

)

Value:

(((x) & 0x3) << 5) /* Rx1 BBF Pow Ctr<1:0> */

RX1_BBF_R1A

#define RX1_BBF_R1A

(

x

)

Value:

(((x) & 0x3F) << 0) /* Rx1 BBF R1A<5:0> */

RX1_BBF_TUNE_COMP_I

#define RX1_BBF_TUNE_COMP_I   (1 << 3) /* Rx1 BBF Tune Comp I */

RX1_BBF_TUNE_COMP_Q

#define RX1_BBF_TUNE_COMP_Q   (1 << 2) /* Rx1 BBF Tune Comp Q */

RX1_FAST_ATK_SHIFT

#define RX1_FAST_ATK_SHIFT   0

RX1_GAIN_CTRL_SETUP

#define RX1_GAIN_CTRL_SETUP

(

x

)

Value:

(((x) & 0x3) << 0) /* Rx 1 Gain Control Setup<1:0> */

RX1_GAIN_CTRL_SHIFT

#define RX1_GAIN_CTRL_SHIFT   0

RX1_INPUT_A_FORCE_OFFSET

#define RX1_INPUT_A_FORCE_OFFSET   (1 << 2) /* Rx1 Input A Force offset */

RX1_INPUT_A_FORCE_PHGAIN

#define RX1_INPUT_A_FORCE_PHGAIN   (1 << 0) /* Rx1 Input A Force Ph/Gain */

RX1_INPUT_A_I_DC_OFFSET_LSB

#define RX1_INPUT_A_I_DC_OFFSET_LSB

(

x

)

Value:

(((x) & 0x3F) << 2) /* Rx1 Input A "I" DC Offset<5:0> */

RX1_INPUT_A_I_DC_OFFSET_MSB

#define RX1_INPUT_A_I_DC_OFFSET_MSB

(

x

)

Value:

(((x) & 0xF) << 0) /* Rx1 Input A "I" DC Offset<9:6> */

RX1_INPUT_A_Q_DC_OFFSET

#define RX1_INPUT_A_Q_DC_OFFSET

(

x

)

Value:

(((x) & 0x3) << 0) /* Rx1 Input A "Q" DC Offset<9:8> */

RX1_INPUT_BC_FORCE_OFFSET

#define RX1_INPUT_BC_FORCE_OFFSET   (1 << 6) /* Rx1 Input B&C Force offset */

RX1_INPUT_BC_FORCE_PHGAIN

#define RX1_INPUT_BC_FORCE_PHGAIN   (1 << 4) /* Rx1 Input B&C Force Ph/Gain */

RX1_INPUT_BC_I_DC_OFFSET_LSB

#define RX1_INPUT_BC_I_DC_OFFSET_LSB

(

x

)

Value:

(((x) & 0x3F) << 2) /* Rx1 Input B&C "I" DC Offset<5:0> */

RX1_INPUT_BC_I_DC_OFFSET_MSB

#define RX1_INPUT_BC_I_DC_OFFSET_MSB

(

x

)

Value:

(((x) & 0xF) << 0) /* Rx1 Input B&C "I" DC Offset<9:6> */

RX1_INPUT_BC_Q_DC_OFFSET

#define RX1_INPUT_BC_Q_DC_OFFSET

(

x

)

Value:

(((x) & 0x3) << 0) /* Rx1 Input B&C "Q" DC Offset<9:8> */

RX1_LNA_BYPASS

#define RX1_LNA_BYPASS   (1 << 2) /* Rx1 LNA Bypass */

RX1_LNA_GAIN

#define RX1_LNA_GAIN

(

x

)

Value:

(((x) & 0x3) << 0) /* Rx1 LNA Gain<1:0> */

RX1_MANUAL_FULL_TABLE_LMT_TABLE_GAIN_INDEX

#define RX1_MANUAL_FULL_TABLE_LMT_TABLE_GAIN_INDEX

(

x

)

Value:

(((x) & 0x7F) << 0) /* Rx1 Manual Full table/LMT table Gain Index<6:0> */

RX1_MANUAL_LPF_GAIN

#define RX1_MANUAL_LPF_GAIN

(

x

)

Value:

(((x) & 0x1F) << 0) /* Rx1 Manual LPF Gain <4:0> */

RX1_MANUALFORCED_DIGITAL_GAIN

#define RX1_MANUALFORCED_DIGITAL_GAIN

(

x

)

Value:

(((x) & 0x1F) << 0) /* Rx1 Manual/Forced Digital Gain<4:0> */

RX1_MIX_GM_BIAS

#define RX1_MIX_GM_BIAS

(

x

)

Value:

(((x) & 0x1F) << 0) /* Rx1 Mix Gm Bias<4:0> */

RX1_MIX_GM_GAIN

#define RX1_MIX_GM_GAIN

(

x

)

Value:

(((x) & 0x3F) << 0) /* Rx1 Mix Gm Gain<5:0> */

RX1_PD_TUNE

#define RX1_PD_TUNE   (1 << 0) /* Rx1 PD Tune */

RX1_RSSI_PREAMBLE

#define RX1_RSSI_PREAMBLE   (1 << 0) /* Rx1 RSSI preamble <0> */

RX1_RSSI_SYMBOL

#define RX1_RSSI_SYMBOL   (1 << 0) /* Rx1 RSSI symbol <0> */

RX1_TUNE_RESAMPLE

#define RX1_TUNE_RESAMPLE   (1 << 1) /* Rx1 Tune Resample */

RX1_TUNE_RESAMPLE_PHASE

#define RX1_TUNE_RESAMPLE_PHASE   (1 << 2) /* Rx1 Tune Resample Phase */

RX1RX2_BB_DC_OFFSET_TRACKING_CORRECTION_WORD_I

#define RX1RX2_BB_DC_OFFSET_TRACKING_CORRECTION_WORD_I

(

x

)

Value:

(((x) & 0x7F) << 0) /* RX1/RX2 BB DC Offset Tracking correction word I<14:8> */

RX1RX2_BB_DC_OFFSET_TRACKING_CORRECTION_WORD_Q

#define RX1RX2_BB_DC_OFFSET_TRACKING_CORRECTION_WORD_Q

(

x

)

Value:

(((x) & 0x7F) << 0) /* RX1/RX2 BB DC Offset Tracking correction word Q<14:8> */

RX2_BB_DC_OFFSET_CORRECTION_WORD_I

#define RX2_BB_DC_OFFSET_CORRECTION_WORD_I

(

x

)

Value:

(((x) & 0x7F) << 0) /* RX2 BB DC Offset Correction word I<14:8> */

RX2_BB_DC_OFFSET_CORRECTION_WORD_Q

#define RX2_BB_DC_OFFSET_CORRECTION_WORD_Q

(

x

)

Value:

(((x) & 0x7F) << 0) /* RX2 BB DC Offset Correction word Q<14:8> */

RX2_BBF_BQ_GAIN

#define RX2_BBF_BQ_GAIN

(

x

)

Value:

(((x) & 0x3) << 3) /* Rx2 BBF BQ Gain<1:0> */

RX2_BBF_FORCE_GAIN

#define RX2_BBF_FORCE_GAIN   (1 << 5) /* Rx2 BBF Force Gain */

RX2_BBF_POLE_GAIN

#define RX2_BBF_POLE_GAIN

(

x

)

Value:

(((x) & 0x7) << 0) /* Rx2 BBF Pole Gain<2:0> */

RX2_BBF_R1A

#define RX2_BBF_R1A

(

x

)

Value:

(((x) & 0x3F) << 0) /* Rx2 BBF R1A<5:0> */

RX2_BBF_TUNE_COMP_I

#define RX2_BBF_TUNE_COMP_I   (1 << 1) /* Rx2 BBF Tune Comp I */

RX2_BBF_TUNE_COMP_Q

#define RX2_BBF_TUNE_COMP_Q   (1 << 0) /* Rx2 BBF Tune Comp Q */

RX2_FAST_ATK_SHIFT

#define RX2_FAST_ATK_SHIFT   4

RX2_GAIN_CTRL_SETUP

#define RX2_GAIN_CTRL_SETUP

(

x

)

Value:

(((x) & 0x3) << 2) /* Rx 2 Gain Control Setup<1:0> */

RX2_GAIN_CTRL_SHIFT

#define RX2_GAIN_CTRL_SHIFT   2

RX2_INPUT_A_FORCE_OFFSET

#define RX2_INPUT_A_FORCE_OFFSET   (1 << 3) /* Rx2 Input A Force offset */

RX2_INPUT_A_FORCE_PHGAIN

#define RX2_INPUT_A_FORCE_PHGAIN   (1 << 1) /* Rx2 Input A Force Ph/Gain */

RX2_INPUT_A_I_DC_OFFSET

#define RX2_INPUT_A_I_DC_OFFSET

(

x

)

Value:

(((x) & 0x3) << 6) /* Rx2 Input A "I" DC Offset<1:0> */

RX2_INPUT_A_Q_DC_OFFSET_LSB

#define RX2_INPUT_A_Q_DC_OFFSET_LSB

(

x

)

Value:

(((x) & 0xF) << 4) /* Rx2 Input A "Q" DC Offset<3:0> */

RX2_INPUT_A_Q_DC_OFFSET_MSB

#define RX2_INPUT_A_Q_DC_OFFSET_MSB

(

x

)

Value:

(((x) & 0x3F) << 0) /* Rx2 Input A "Q" DC Offset<9:4> */

RX2_INPUT_BC_FORCE_OFFSET

#define RX2_INPUT_BC_FORCE_OFFSET   (1 << 7) /* Rx2 Input B&C Force offset */

RX2_INPUT_BC_FORCE_PHGAIN

#define RX2_INPUT_BC_FORCE_PHGAIN   (1 << 5) /* Rx2 Input B&C Force Ph/Gain */

RX2_INPUT_BC_I_DC_OFFSET

#define RX2_INPUT_BC_I_DC_OFFSET

(

x

)

Value:

(((x) & 0x3) << 6) /* Rx2 Input B&C "I" DC Offset<1:0> */

RX2_INPUT_BC_Q_DC_OFFSET_LSB

#define RX2_INPUT_BC_Q_DC_OFFSET_LSB

(

x

)

Value:

(((x) & 0xF) << 4) /* Rx2 Input B&C "Q" DC Offset<3:0> */

RX2_INPUT_BC_Q_DC_OFFSET_MSB

#define RX2_INPUT_BC_Q_DC_OFFSET_MSB

(

x

)

Value:

(((x) & 0x3F) << 0) /* Rx2 Input B&C "Q" DC Offset<9:4> */

RX2_LNA_BYPASS

#define RX2_LNA_BYPASS   (1 << 6) /* Rx2 LNA Bypass */

RX2_LNA_GAIN

#define RX2_LNA_GAIN

(

x

)

Value:

(((x) & 0x3) << 4) /* Rx2 LNA Gain<1:0> */

RX2_MANUAL_FULL_TABLE_LMT_TABLE_GAIN_INDEX

#define RX2_MANUAL_FULL_TABLE_LMT_TABLE_GAIN_INDEX

(

x

)

Value:

(((x) & 0x7F) << 0) /* Rx2 Manual Full table/ LMT table Gain Index<6:0> */

RX2_MANUAL_LPF_GAIN

#define RX2_MANUAL_LPF_GAIN

(

x

)

Value:

(((x) & 0x1F) << 0) /* Rx2 Manual LPF Gain<4:0> */

RX2_MANUALFORCED_DIGITAL_GAIN

#define RX2_MANUALFORCED_DIGITAL_GAIN

(

x

)

Value:

(((x) & 0x1F) << 0) /* Rx2 Manual/Forced Digital Gain<4:0> */

RX2_MIX_GM_BIAS

#define RX2_MIX_GM_BIAS

(

x

)

Value:

(((x) & 0x1F) << 0) /* Rx2 Mix Gm Bias<4:0> */

RX2_MIX_GM_GAIN

#define RX2_MIX_GM_GAIN

(

x

)

Value:

(((x) & 0x3F) << 0) /* Rx2 Mix Gm Gain<5:0> */

RX2_PD_TUNE

#define RX2_PD_TUNE   (1 << 0) /* Rx2 PD Tune */

RX2_RSSI_PREAMBLE

#define RX2_RSSI_PREAMBLE   (1 << 1) /* Rx2 RSSI preamble <0> */

RX2_RSSI_SYMBOL

#define RX2_RSSI_SYMBOL   (1 << 1) /* Rx2 RSSI symbol <0> */

RX2_TUNE_RESAMPLE

#define RX2_TUNE_RESAMPLE   (1 << 1) /* Rx2 Tune Resample */

RX2_TUNE_RESAMPLE_PHASE

#define RX2_TUNE_RESAMPLE_PHASE   (1 << 2) /* Rx2 Tune Resam ple Phase */

RX_1

#define RX_1   1

RX_2

#define RX_2   2

RX_BB_TUNE_CAL

#define RX_BB_TUNE_CAL   (1 << 7) /* Rx BB Tune */

RX_BBF_C1_LSB

#define RX_BBF_C1_LSB

(

x

)

Value:

(((x) & 0x7F) << 0) /* Rx BBF C1 LSB<6:0> */

RX_BBF_C1_MSB

#define RX_BBF_C1_MSB

(

x

)

Value:

(((x) & 0x3F) << 0) /* Rx BBF C1 MSB<5:0> */

RX_BBF_C2_LSB

#define RX_BBF_C2_LSB

(

x

)

Value:

(((x) & 0x7F) << 0) /* Rx BBF C2 LSB<6:0> */

RX_BBF_C2_MSB

#define RX_BBF_C2_MSB

(

x

)

Value:

(((x) & 0x3F) << 0) /* Rx BBF C2 MSB<5:0> */

RX_BBF_C3_LSB

#define RX_BBF_C3_LSB

(

x

)

Value:

(((x) & 0x7F) << 0) /* Rx BBF C3 LSB<6:0> */

RX_BBF_C3_MSB

#define RX_BBF_C3_MSB

(

x

)

Value:

(((x) & 0x3F) << 0) /* Rx BBF C3 MSB<5:0> */

RX_BBF_CC1_CTR

#define RX_BBF_CC1_CTR

(

x

)

Value:

(((x) & 0x7F) << 0) /* Rx BBF CC1 Ctr<6:0> */

RX_BBF_CC2_CTR

#define RX_BBF_CC2_CTR

(

x

)

Value:

(((x) & 0x7F) << 0) /* Rx BBF CC2 Ctr<6:0> */

RX_BBF_CC3_CTR

#define RX_BBF_CC3_CTR

(

x

)

Value:

(((x) & 0x7F) << 0) /* Rx BBF CC3 Ctr<6:0> */

RX_BBF_POW2_CTR

#define RX_BBF_POW2_CTR

(

x

)

Value:

(((x) & 0x3) << 2) /* Rx BBF Pow2 Ctr<1:0> */

RX_BBF_POW3_CTR

#define RX_BBF_POW3_CTR

(

x

)

Value:

(((x) & 0x3) << 6) /* Rx BBF Pow3 Ctr<1:0> */

RX_BBF_POWER_DOWN

#define RX_BBF_POWER_DOWN

(

x

)

Value:

(((x) & 0x3) << 6) /* Rx BBF Power Down<1:0> */

RX_BBF_R2346

#define RX_BBF_R2346

(

x

)

Value:

(((x) & 0x7) << 0) /* Rx BBF R2346<2:0> */

RX_BBF_R5_TUNE

#define RX_BBF_R5_TUNE   (1 << 4) /* Rx BBF R5 Tune */

RX_BBF_RZ1_CTR

#define RX_BBF_RZ1_CTR

(

x

)

Value:

(((x) & 0x3) << 3) /* Rx BBF Rz1 Ctr<1:0> */

RX_BBF_RZ2_CTR

#define RX_BBF_RZ2_CTR

(

x

)

Value:

(((x) & 0x3) << 0) /* Rx BBF Rz2 Ctr<1:0> */

RX_BBF_RZ3_CTR

#define RX_BBF_RZ3_CTR

(

x

)

Value:

(((x) & 0x3) << 4) /* Rx BBF RZ3 Ctr<1:0> */

RX_BBF_TUNE_CTR

#define RX_BBF_TUNE_CTR

(

x

)

Value:

(((x) & 0x3) << 5) /* Rx BBF Tune Ctr<1:0> */

RX_BBF_TUNE_DIVIDE

#define RX_BBF_TUNE_DIVIDE   (1 << 0) /* RX BBF Tune Divide<8> */

RX_CALIBRATION_POWER_DOWN

#define RX_CALIBRATION_POWER_DOWN

(

x

)

Value:

(((x) & 0x3) << 2) /* Rx Calibration Power Down<1:0> */

RX_CGB_BIAS

#define RX_CGB_BIAS

(

x

)

Value:

(((x) & 0xF) << 0) /* Rx CGB Bias<3:0> */

RX_CGB_INPUT_CM_SEL

#define RX_CGB_INPUT_CM_SEL

(

x

)

Value:

(((x) & 0x3) << 4) /* Rx CGB Input CM Sel<1:0> */

RX_CGB_POWER_DOWN

#define RX_CGB_POWER_DOWN

(

x

)

Value:

(((x) & 0x3) << 0) /* Rx CGB Power Down<1:0> */

RX_CGB_SEG_ENABLE

#define RX_CGB_SEG_ENABLE

(

x

)

Value:

(((x) & 0x3F) << 0) /* Rx CGB Seg Enable<5:0> */

RX_CHANNEL_ENABLE

#define RX_CHANNEL_ENABLE

(

x

)

Value:

(((x) & 0x3) << 6) /* Rx channel Enable<1:0> */

RX_CHANNEL_SWAP

#define RX_CHANNEL_SWAP   (1 << 4) /* Rx Channel swap */

RX_DATA_DELAY

#define RX_DATA_DELAY

(

x

)

Value:

(((x) & 0xF) << 0) /* Rx Data Delay <3:0> */

RX_DIGITAL_IDX_MASK

#define RX_DIGITAL_IDX_MASK   RX1_MANUALFORCED_DIGITAL_GAIN(~0)

RX_DISABLE

#define RX_DISABLE   0

RX_ENABLE

#define RX_ENABLE   1

RX_EXT_VCO_BUFFER_POWER_DOWN

#define RX_EXT_VCO_BUFFER_POWER_DOWN   (1 << 5) /* Rx Ext VCO Buffer Power Down */

RX_FAST_LOCK_CONFIG_WORD_NUM

#define RX_FAST_LOCK_CONFIG_WORD_NUM   16

RX_FAST_LOCK_LOAD_SYNTH

#define RX_FAST_LOCK_LOAD_SYNTH   (1 << 3) /* Rx Fast Lock Load Synth */

RX_FAST_LOCK_MODE_ENABLE

#define RX_FAST_LOCK_MODE_ENABLE   (1 << 0) /* Rx Fast Lock Mode Enable */

RX_FAST_LOCK_PROFILE

#define RX_FAST_LOCK_PROFILE

(

x

)

Value:

(((x) & 0x7) << 5) /* Rx Fast Lock Profile<2:0> */

RX_FAST_LOCK_PROFILE_ADDR

#define RX_FAST_LOCK_PROFILE_ADDR

(

x

)

Value:

(((x) & 0x7) << 4) /* Rx Fast Lock Profile<2:0> */

RX_FAST_LOCK_PROFILE_INIT

#define RX_FAST_LOCK_PROFILE_INIT   (1 << 2) /* Rx Fast Lock Profile Init */

RX_FAST_LOCK_PROFILE_PIN_SELECT

#define RX_FAST_LOCK_PROFILE_PIN_SELECT   (1 << 1) /* Rx Fast Lock Profile Pin Select */

RX_FAST_LOCK_PROFILE_WORD

#define RX_FAST_LOCK_PROFILE_WORD

(

x

)

Value:

(((x) & 0xF) << 0) /* Configuration Word <3:0> */

RX_FAST_LOCK_PROGRAM_CLOCK_ENABLE

#define RX_FAST_LOCK_PROGRAM_CLOCK_ENABLE   (1 << 0) /* Rx Fast Lock Program Clock Enable */

RX_FAST_LOCK_PROGRAM_WRITE

#define RX_FAST_LOCK_PROGRAM_WRITE   (1 << 1) /* Rx Fast Lock Program Write */

RX_FIR_ENABLE_DECIMATION

#define RX_FIR_ENABLE_DECIMATION

(

x

)

Value:

(((x) & 0x3) << 0) /* Rx FIR Enable & Decimation<1:0> */

RX_FRAME_PULSE_MODE

#define RX_FRAME_PULSE_MODE   (1 << 3) /* Rx Frame Pulse Mode */

RX_FULL_TABLELMT_TABLE_GAIN [1/2]

#define RX_FULL_TABLELMT_TABLE_GAIN

(

x

)

Value:

(((x) & 0x7F) << 0) /* RX Full table/LMT table gain<6:0> */

RX_FULL_TABLELMT_TABLE_GAIN [2/2]

#define RX_FULL_TABLELMT_TABLE_GAIN

(

x

)

Value:

(((x) & 0x7F) << 0) /* Rx Full table/LMT table gain<6:0> */

RX_FULL_TBL_IDX_MASK

#define RX_FULL_TBL_IDX_MASK   RX1_MANUAL_FULL_TABLE_LMT_TABLE_GAIN_INDEX(~0)

RX_GAIN_CTL_AGC_FAST_ATK

#define RX_GAIN_CTL_AGC_FAST_ATK   0x01

RX_GAIN_CTL_AGC_SLOW_ATK

#define RX_GAIN_CTL_AGC_SLOW_ATK   0x02

RX_GAIN_CTL_AGC_SLOW_ATK_HYBD

#define RX_GAIN_CTL_AGC_SLOW_ATK_HYBD   0x03

RX_GAIN_CTL_MASK

#define RX_GAIN_CTL_MASK   0x03

RX_GAIN_CTL_MGC

#define RX_GAIN_CTL_MGC   0x00

RX_GAIN_STEP_CAL

#define RX_GAIN_STEP_CAL   (1 << 3) /* Rx Gain Step Cal */

RX_INPUT

#define RX_INPUT

(

x

)

Value:

(((x) & 0x3F) << 0) /* RX Input <5:0> */

RX_LMT_OVERLOAD_POWER_DOWN

#define RX_LMT_OVERLOAD_POWER_DOWN

(

x

)

Value:

(((x) & 0x3) << 4) /* Rx LMT Overload Power Down<1:0> */

RX_LNA_BIAS

#define RX_LNA_BIAS

(

x

)

Value:

(((x) & 0x1F) << 0) /* Rx LNA Bias<4:0> */

RX_LNA_BIAS_COARSE

#define RX_LNA_BIAS_COARSE

(

x

)

Value:

(((x) & 0xF) << 0) /* Rx LNA Bias Coarse<3:0> */

RX_LNA_P_CASCODE_BIAS_FINE

#define RX_LNA_P_CASCODE_BIAS_FINE

(

x

)

Value:

(((x) & 0x3) << 0) /* Rx LNA p- Cascode Bias Fine<4:3> */

RX_LNA_PCASCODE_BIAS

#define RX_LNA_PCASCODE_BIAS

(

x

)

Value:

(((x) & 0x7) << 5) /* Rx LNA p-Cascode Bias<2:0> */

RX_LNA_POWER_DOWN

#define RX_LNA_POWER_DOWN   (1 << 6) /* Rx LNA Power Down */

RX_LO_GEN_POWER_MODE

#define RX_LO_GEN_POWER_MODE

(

x

)

Value:

(((x) & 0x3) << 4) /* Power Mode<3:0> */

RX_LO_POWER_DOWN

#define RX_LO_POWER_DOWN   (1 << 4) /* Rx LO Power Down */

RX_LPF_GAIN [1/2]

#define RX_LPF_GAIN

(

x

)

Value:

(((x) & 0x1F) << 0) /* RX LPF gain<4:0> */

RX_LPF_GAIN [2/2]

#define RX_LPF_GAIN

(

x

)

Value:

(((x) & 0x1F) << 0) /* Rx LPF gain<4:0> */

RX_LPF_IDX_MASK

#define RX_LPF_IDX_MASK   RX1_MANUAL_LPF_GAIN(~0)

RX_MASK

#define RX_MASK   (1 << 6) /* Rx Mask */

RX_MIX_GM_CM_OUT

#define RX_MIX_GM_CM_OUT

(

x

)

Value:

(((x) & 0x7) << 5) /* Rx Mix Gm CM Out<2:0> */

RX_MIX_GM_PLOAD

#define RX_MIX_GM_PLOAD

(

x

)

Value:

(((x) & 0x3) << 0) /* Rx Mix Gm pload <1:0> */

RX_MIX_LO_CM

#define RX_MIX_LO_CM

(

x

)

Value:

(((x) & 0x3F) << 0) /* Rx Mix LO CM<5:0> */

RX_MIXER_GM_POWER_DOWN

#define RX_MIXER_GM_POWER_DOWN

(

x

)

Value:

(((x) & 0x3) << 2) /* Rx Mixer Gm Power Down<1:0> */

RX_MIXER_POWER_DOWN

#define RX_MIXER_POWER_DOWN

(

x

)

Value:

(((x) & 0x3) << 2) /* Rx Mixer Power Down<1:0> */

RX_NCO_FREQ

#define RX_NCO_FREQ

(

x

)

Value:

(((x) & 0x3) << 5) /* Rx NCO Frequency<1:0> */

RX_NCO_PHASE_OFFSET

#define RX_NCO_PHASE_OFFSET

(

x

)

Value:

(((x) & 0x1F) << 0) /* Rx NCO Phase Offset<4:0> */

RX_OFFSET_DAC_CGIN_POWER_DOWN

#define RX_OFFSET_DAC_CGIN_POWER_DOWN

(

x

)

Value:

(((x) & 0x3) << 6) /* Rx Offset DAC CGin Power Down<1:0> */

RX_OFFSET_DAC_CGOUT_POWER_DOWN

#define RX_OFFSET_DAC_CGOUT_POWER_DOWN

(

x

)

Value:

(((x) & 0x3) << 0) /* Rx Offset DAC CGOut Power Down<1:0> */

RX_ON_CHIP_TERM

#define RX_ON_CHIP_TERM   (1 << 5) /* Rx On Chip Term */

RX_PATH_GAIN

#define RX_PATH_GAIN   (1 << 0) /* Rx Path Gain<0> */

RX_QUAD_CAL

#define RX_QUAD_CAL   (1 << 5) /* Rx Quad Cal */

RX_QUAD_CAL_LEVEL

#define RX_QUAD_CAL_LEVEL

(

x

)

Value:

(((x) & 0xF) << 0) /* Rx Quad Cal Level <3 :0> */

RX_REF_DIVIDER_LSB

#define RX_REF_DIVIDER_LSB   (1 << 7) /* Rx Ref Divider< 0> */

RX_REF_DIVIDER_MSB

#define RX_REF_DIVIDER_MSB   (1 << 0) /* Rx Ref Divider<1> */

RX_REF_DOUBLER_FB_DELAY

#define RX_REF_DOUBLER_FB_DELAY

(

x

)

Value:

(((x) & 0x3) << 5) /* Rx Ref Doubler FB Delay<1:0> */

RX_REF_RESET_BAR

#define RX_REF_RESET_BAR   (1 << 1) /* Rx Ref Reset Bar */

RX_SYNTH_PTAT_POWER_DOWN

#define RX_SYNTH_PTAT_POWER_DOWN   (1 << 2) /* Rx Synth PTAT Power Down */

RX_SYNTH_READY_MASK

#define RX_SYNTH_READY_MASK   (1 << 1) /* Rx Synth Ready Mask */

RX_SYNTH_VCO_ALC_POWER_DOWN

#define RX_SYNTH_VCO_ALC_POWER_DOWN   (1 << 3) /* Rx Synth VCO ALC Power Down */

RX_SYNTH_VCO_LDO_POWER_DOWN

#define RX_SYNTH_VCO_LDO_POWER_DOWN   (1 << 0) /* Rx Synth VCO LDO Power Down */

RX_SYNTH_VCO_POWER_DOWN

#define RX_SYNTH_VCO_POWER_DOWN   (1 << 1) /* Rx Synth VCO Power Down */

RX_TIA_POWER_DOWN

#define RX_TIA_POWER_DOWN

(

x

)

Value:

(((x) & 0x3) << 4) /* Rx TIA Power Down<1:0> */

RX_TUNE_BBBW_KHZ

#define RX_TUNE_BBBW_KHZ

(

x

)

Value:

(((x) & 0x7F) << 0) /* Rx Tune BBBW kHz<6:0> */

RX_TUNE_BBBW_MHZ

#define RX_TUNE_BBBW_MHZ

(

x

)

Value:

(((x) & 0x1F) << 0) /* Rx Tune BBBW MHz<4::0> */

RX_TUNE_EVALTIME

#define RX_TUNE_EVALTIME   (1 << 4) /* Rx Tune Evaltime */

RX_TUNE_MODE

#define RX_TUNE_MODE

(

x

)

Value:

(((x) & 0x7) << 1) /* Rx Tune Mode<2:0> */

RX_VCO_DIVIDER

#define RX_VCO_DIVIDER

(

x

)

Value:

(((x) & 0xF) << 0) /* RX VCO  Divider<3:0> */

RXBBF_BYPASS_BIAS_R

#define RXBBF_BYPASS_BIAS_R   (1 << 7) /* RxBBF Bypass Bias R */

SDM_BYPASS

#define SDM_BYPASS   (1 << 7) /* SDM Bypass */

SDM_POWER_DOWN

#define SDM_POWER_DOWN   (1 << 6) /* SDM Power Down */

SEL_TX1_TX2

#define SEL_TX1_TX2   (1 << 6) /* Sel Tx1 & Ttx2 */

SELECT_RX_CH

#define SELECT_RX_CH

(

x

)

Value:

(((x) & 0x3) << 3) /* Select Rx Ch<1:0> */

SETTLE_MAIN_ENABLE

#define SETTLE_MAIN_ENABLE   (1 << 6) /* Settle Main Enable */

SETTLE_TIME

#define SETTLE_TIME

(

x

)

Value:

(((x) & 0x3F) << 0) /* Settle Time<5:0> */

SETTLING_DELAY

#define SETTLING_DELAY

(

x

)

Value:

(((x) & 0x1F) << 0) /* Settling Delay<4:0> */

SIF_ADDR [1/2]

#define SIF_ADDR

(

x

)

Value:

(((x) & 0x1F) << 0) /* SIF Addr<4:0> */

SIF_ADDR [2/2]

#define SIF_ADDR

(

x

)

Value:

(((x) & 0x1F) << 0) /* SIF Addr<4:0> */

SIF_CLOCK [1/2]

#define SIF_CLOCK   (1 << 6) /* SIF clock */

SIF_CLOCK [2/2]

#define SIF_CLOCK   (1 << 6) /* SIF clock */

SIF_RESET_BAR [1/2]

#define SIF_RESET_BAR   (1 << 5) /* SIF Reset Bar */

SIF_RESET_BAR [2/2]

#define SIF_RESET_BAR   (1 << 5) /* SIF Reset Bar */

SINGLE_DATA_RATE

#define SINGLE_DATA_RATE   (1 << 5) /* Single Data Rate */

SINGLE_PORT_MODE

#define SINGLE_PORT_MODE   (1 << 2) /* Single Port Mode */

SLOW_ATTACK_HYBRID_MODE

#define SLOW_ATTACK_HYBRID_MODE   (1 << 4) /* Slow Attack Hybrid Mode */

SLOW_LOOP_STATE_RX1

#define SLOW_LOOP_STATE_RX1

(

x

)

Value:

(((x) & 0x7) << 0) /* Slow Loop State Rx1<2:0> */

SLOW_LOOP_STATE_RX2

#define SLOW_LOOP_STATE_RX2

(

x

)

Value:

(((x) & 0x7) << 4) /* Slow Loop State Rx2<2:0> */

SMALL_ADC_OL

#define SMALL_ADC_OL   (1 << 1) /* Small ADC OL */

SMALL_ADC_OVERLOAD_EXED_COUNTER

#define SMALL_ADC_OVERLOAD_EXED_COUNTER

(

x

)

Value:

(((x) & 0xF) << 0) /* Small ADC Overload Exceeded Counter<3:0> */

SMALL_LMT_OL

#define SMALL_LMT_OL   (1 << 3) /* Small LMT OL */

SMALL_LMT_OVERLOAD_EXED_COUNTER

#define SMALL_LMT_OVERLOAD_EXED_COUNTER

(

x

)

Value:

(((x) & 0xF) << 0) /* Small LMT Overload Exceeded Counter<3:0> */

SMALL_LMT_OVERLOAD_THRESH

#define SMALL_LMT_OVERLOAD_THRESH

(

x

)

Value:

(((x) & 0x3F) << 0) /* Small LMT Overload Threshold<5:0> */

SOFT_RESET [1/2]

#define SOFT_RESET   (1 << 7) /* Soft Reset */

SOFT_RESET [2/2]

#define SOFT_RESET   (1 << 7) /* Soft Reset */

START_CALIB_TABLE_CLOCK

#define START_CALIB_TABLE_CLOCK   (1 << 0) /* Start Calib Table Clock */

START_GAIN_TABLE_CLOCK

#define START_GAIN_TABLE_CLOCK   (1 << 1) /* Start Gain Table Clock */

START_GM_SUB_TABLE_CLOCK

#define START_GM_SUB_TABLE_CLOCK   (1 << 1) /* Start Gm Sub Table Clock */

START_RSSI_MEAS

#define START_RSSI_MEAS   (1 << 5) /* Start RSSI Meas (Mode 4) */

START_RX_CLOCK

#define START_RX_CLOCK   (1 << 1) /* Start Rx Clock */

START_TEMP_READING

#define START_TEMP_READING   (1 << 0) /* Start Temp Reading */

STRONGER_SIGNAL_THRESH

#define STRONGER_SIGNAL_THRESH

(

x

)

Value:

(((x) & 0x3F) << 0) /* Stronger Signal Threshold<5:0> */

SWAP_PORTS

#define SWAP_PORTS   (1 << 6) /* Swap Ports */

SYNTH_ENABLE_PIN_CTRL_MODE

#define SYNTH_ENABLE_PIN_CTRL_MODE   (1 << 3) /* Synth Enable Pin Control Mode */

SYNTH_FRACT_WORD [1/2]

#define SYNTH_FRACT_WORD

(

x

)

Value:

(((x) & 0x7F) << 0) /* Synthesizer Fractional Word <22:16> */

SYNTH_FRACT_WORD [2/2]

#define SYNTH_FRACT_WORD

(

x

)

Value:

(((x) & 0x7F) << 0) /* Synthesizer Fractional Word <22:16> */

SYNTH_INTEGER_WORD [1/2]

#define SYNTH_INTEGER_WORD

(

x

)

Value:

(((x) & 0x7) << 0) /* Synthesizer Integer Word<10:8> */

SYNTH_INTEGER_WORD [2/2]

#define SYNTH_INTEGER_WORD

(

x

)

Value:

(((x) & 0x7) << 0) /* Synthesizer Integer Word<10:8> */

SYNTH_RECAL [1/2]

#define SYNTH_RECAL   (1 << 7) /* Synth Re-Cal */

SYNTH_RECAL [2/2]

#define SYNTH_RECAL   (1 << 7) /* Synth Re-Cal */

TEMP_SENSE_PERIODIC_ENABLE

#define TEMP_SENSE_PERIODIC_ENABLE   (1 << 0) /* Temp Sense Periodic Enable */

TEMP_SENSE_VBE_TEST

#define TEMP_SENSE_VBE_TEST

(

x

)

Value:

(((x) & 0x3) << 6) /* Temp Sense Vbe Test<1:0> */

TEMP_SENSOR_DECIMATION

#define TEMP_SENSOR_DECIMATION

(

x

)

Value:

(((x) & 0x7) << 0) /* Temp Sensor Decimation<2:0> */

THB1_EN

#define THB1_EN   (1 << 2) /* THB1 Enable */

THB2_EN

#define THB2_EN   (1 << 3) /* THB2 Enable */

THB3_ENABLE_INTERP

#define THB3_ENABLE_INTERP

(

x

)

Value:

(((x) & 0x3) << 4) /* THB3 Enable & Interp<1:0> */

THRESH_ACCUMULATOR

#define THRESH_ACCUMULATOR

(

x

)

Value:

(((x) & 0xF) << 0) /* Threshold Accumulator<3:0> */

TIA1_C_LSB

#define TIA1_C_LSB

(

x

)

Value:

(((x) & 0x3F) << 0) /* TIA1  C LSB<5:0> */

TIA1_C_MSB

#define TIA1_C_MSB

(

x

)

Value:

(((x) & 0x7F) << 0) /* TIA1 C MSB<6:0> */

TIA1_OVERRIDE_C

#define TIA1_OVERRIDE_C   (1 << 1) /* TIA1 Override C */

TIA1_OVERRIDE_R

#define TIA1_OVERRIDE_R   (1 << 0) /* TIA1 Override R */

TIA1_RF

#define TIA1_RF

(

x

)

Value:

(((x) & 0x3) << 6) /* TIA1 RF<1:0> */

TIA2_C_LSB

#define TIA2_C_LSB

(

x

)

Value:

(((x) & 0x3F) << 0) /* TIA2 C LSB<5:0> */

TIA2_C_MSB

#define TIA2_C_MSB

(

x

)

Value:

(((x) & 0x7F) << 0) /* TIA2 C MSB<6:0> */

TIA2_OVERRIDE_C

#define TIA2_OVERRIDE_C   (1 << 3) /* TIA2 Override C */

TIA2_OVERRIDE_R

#define TIA2_OVERRIDE_R   (1 << 2) /* TIA2 Override R */

TIA2_RF

#define TIA2_RF

(

x

)

Value:

(((x) & 0x3) << 6) /* TIA2 RF<1:0> */

TIA_GAIN

#define TIA_GAIN   (1 << 5) /* TIA Gain */

TIA_SEL_CC

#define TIA_SEL_CC

(

x

)

Value:

(((x) & 0x7) << 5) /* TIA Sel CC<2:0> */

TO_ALERT

#define TO_ALERT   (1 << 0) /* To Alert */

TO_DIGITAL_GAIN

#define TO_DIGITAL_GAIN

(

x

)

Value:

(((x) >> 0) & 0x1F) /* Digital Gain <4:0> */

TO_LNA_GAIN

#define TO_LNA_GAIN

(

x

)

Value:

(((x) >> 5) & 0x3) /* LNA Gain <1:0> */

TO_LPF_GAIN

#define TO_LPF_GAIN

(

x

)

Value:

(((x) >> 0) & 0x1F) /* LPF Gain <4:0> */

TO_MIXER_GM_GAIN

#define TO_MIXER_GM_GAIN

(

x

)

Value:

(((x) >> 0) & 0x1F) /* Mixer Gm Gain <4:0> */

TONE_FREQ

#define TONE_FREQ

(

x

)

Value:

(((x) & 0x3) << 6) /* Tone Frequency<1:0> */

TONE_LEVEL

#define TONE_LEVEL

(

x

)

Value:

(((x) & 0x3) << 4) /* Tone Level<1:0> */

TONE_PRBS

#define TONE_PRBS   (1 << 1) /* Tone/ PRBS */

TUNE_COMP_MASK [1/2]

#define TUNE_COMP_MASK

(

x

)

Value:

(((x) & 0x3) << 5) /* Tune Comp Mask<1:0> */

TUNE_COMP_MASK [2/2]

#define TUNE_COMP_MASK

(

x

)

Value:

(((x) & 0x3) << 5) /* Tune Comp Mask <1:0> */

TUNE_CTRL

#define TUNE_CTRL

(

x

)

Value:

(((x) & 0x3) << 5) /* Tune Control<1:0> */

TUNE_OVERRIDE

#define TUNE_OVERRIDE   (1 << 7) /* Tune Override */

TUNER_MODE

#define TUNER_MODE

(

x

)

Value:

(((x) & 0x7) << 1) /* Tuner Mode<2:0> */

TUNER_RESAMPLE

#define TUNER_RESAMPLE   (1 << 1) /* Tuner Resample */

TUNER_RESAMPLE_PHASE

#define TUNER_RESAMPLE_PHASE   (1 << 0) /* Tuner Resample Phase */

TX1_CONVERGENCE_COUNT

#define TX1_CONVERGENCE_COUNT

(

x

)

Value:

(((x) & 0x3F) << 2) /* Tx1 Convergence Count<5:0> */

TX1_LO_CONV

#define TX1_LO_CONV   (1 << 1) /* Tx1 LO Conv */

TX1_MON_ENABLE

#define TX1_MON_ENABLE   (1 << 5) /* Tx1 Monitor Enable */

TX1_MONITOR_ENABLE

#define TX1_MONITOR_ENABLE   (1 << 5) /* Tx1 Monitor Enable */

TX1_SSB_CONV

#define TX1_SSB_CONV   (1 << 0) /* Tx1 SSB Conv */

TX2_CONVERGENCE_COUNT

#define TX2_CONVERGENCE_COUNT

(

x

)

Value:

(((x) & 0x3F) << 2) /* Tx2 Convergence Count<5:0> */

TX2_LO_CONV

#define TX2_LO_CONV   (1 << 1) /* Tx2 LO Conv */

TX2_MON_ENABLE

#define TX2_MON_ENABLE   (1 << 7) /* Tx2 Monitor Enable */

TX2_MONITOR_ENABLE

#define TX2_MONITOR_ENABLE   (1 << 6) /* Tx2 Monitor Enable */

TX2_SSB_CONV

#define TX2_SSB_CONV   (1 << 0) /* Tx2 SSB Conv */

TX_1

#define TX_1   1

TX_1_ATTEN

#define TX_1_ATTEN   (1 << 0) /* Tx 1 Atten <8> */

TX_1_SYMBOL_ATTEN

#define TX_1_SYMBOL_ATTEN

(

x

)

Value:

(((x) & 0x7F) << 0) /* Tx 1 Symbol Attenuation<6:0> */

TX_2

#define TX_2   2

TX_2_ATTEN

#define TX_2_ATTEN   (1 << 0) /* Tx 2 Atten <8> */

TX_2_SYMBOL_ATTEN

#define TX_2_SYMBOL_ATTEN

(

x

)

Value:

(((x) & 0x7F) << 0) /* Tx 2 Symbol Attenuation<6:0> */

TX_ATTEN_OFFSET

#define TX_ATTEN_OFFSET

(

x

)

Value:

(((x) & 0x3F) << 0) /* Tx Atten Offset<5:0> */

TX_BB_TUNE_CAL

#define TX_BB_TUNE_CAL   (1 << 6) /* Tx BB Tune */

TX_BBF_BYPASS_BIAS_R

#define TX_BBF_BYPASS_BIAS_R   (1 << 7) /* Bypass Bias R */

TX_BBF_POWER_DOWN

#define TX_BBF_POWER_DOWN

(

x

)

Value:

(((x) & 0x3) << 4) /* Tx BBF Power Down<1:0> */

TX_BBF_TUNE_DIVIDER

#define TX_BBF_TUNE_DIVIDER   (1 << 0) /* TX BBF Tune Divider<8> */

TX_CHANNEL_ENABLE

#define TX_CHANNEL_ENABLE

(

x

)

Value:

(((x) & 0x3) << 6) /* Tx channel Enable<1:0> */

TX_CHANNEL_SWAP

#define TX_CHANNEL_SWAP   (1 << 5) /* Tx Channel swap */

TX_CP_CURRENT_DFLT

#define TX_CP_CURRENT_DFLT   (1 << 7) /* Set to 1 */

TX_DAC_BIAS_POWER_DOWN

#define TX_DAC_BIAS_POWER_DOWN

(

x

)

Value:

(((x) & 0x3) << 0) /* Tx DAC Bias Power Down<1:0> */

TX_DAC_POWER_DOWN

#define TX_DAC_POWER_DOWN

(

x

)

Value:

(((x) & 0x3) << 2) /* Tx DAC Power Down<1:0> */

TX_DATA_DELAY

#define TX_DATA_DELAY

(

x

)

Value:

(((x) & 0xF) << 0) /* Tx Data Delay <3:0> */

TX_DISABLE

#define TX_DISABLE   0

TX_ENABLE

#define TX_ENABLE   1

TX_EXT_VCO_BUFFER_POWER_DOWN

#define TX_EXT_VCO_BUFFER_POWER_DOWN   (1 << 4) /* Tx Ext VCO Buffer Power Down */

TX_FAST_LOCK_LOAD_SYNTH

#define TX_FAST_LOCK_LOAD_SYNTH   (1 << 3) /* Tx Fast Lock Load Synth */

TX_FAST_LOCK_MODE_ENABLE

#define TX_FAST_LOCK_MODE_ENABLE   (1 << 0) /* Tx Fast Lock Mode Enable */

TX_FAST_LOCK_PROFILE

#define TX_FAST_LOCK_PROFILE

(

x

)

Value:

(((x) & 0x7) << 5) /* Tx Fast Lock Profile<2:0> */

TX_FAST_LOCK_PROFILE_INIT

#define TX_FAST_LOCK_PROFILE_INIT   (1 << 2) /* Tx Fast Lock Profile Init */

TX_FAST_LOCK_PROFILE_PIN_SELECT

#define TX_FAST_LOCK_PROFILE_PIN_SELECT   (1 << 1) /* Tx Fast Lock Profile Pin Select */

TX_FAST_LOCK_PROGRAM_CLOCK_ENABLE

#define TX_FAST_LOCK_PROGRAM_CLOCK_ENABLE   (1 << 0) /* Tx Fast Lock Program Clock Enable */

TX_FAST_LOCK_PROGRAM_WRITE

#define TX_FAST_LOCK_PROGRAM_WRITE   (1 << 1) /* Tx Fast Lock Program Write */

TX_FIR_ENABLE_INTERPOLATION

#define TX_FIR_ENABLE_INTERPOLATION

(

x

)

Value:

(((x) & 0x3) << 0) /* Tx FIR Enable & Interpolation<1:0> */

TX_FIR_GAIN_6DB

#define TX_FIR_GAIN_6DB   (1 << 0) /* Filter Gain */

TX_LEVEL_THRESH

#define TX_LEVEL_THRESH

(

x

)

Value:

(((x) & 0x3F) << 2) /* Tx Level Threshold<5:0> */

TX_LO_GEN_POWER_MODE

#define TX_LO_GEN_POWER_MODE

(

x

)

Value:

(((x) & 0xF) << 4) /* Power Mode<3:0> */

TX_LO_POWER_DOWN

#define TX_LO_POWER_DOWN   (1 << 4) /* Tx LO Power Down */

TX_MON_1_GAIN

#define TX_MON_1_GAIN

(

x

)

Value:

(((x) & 0x3) << 0) /* Tx Mon 1 Gain<1:0> */

TX_MON_1_LO_CM

#define TX_MON_1_LO_CM

(

x

)

Value:

(((x) & 0x3F) << 2) /* Tx Mon 1 LO CM<5:0> */

TX_MON_2_GAIN

#define TX_MON_2_GAIN

(

x

)

Value:

(((x) & 0x3) << 0) /* Tx Mon 2 Gain<1:0> */

TX_MON_2_LO_CM

#define TX_MON_2_LO_CM

(

x

)

Value:

(((x) & 0x3F) << 2) /* Tx Mon 2 LO CM<5:0> */

TX_MON_DELAY_COUNTER

#define TX_MON_DELAY_COUNTER

(

x

)

Value:

(((x) & 0x3) << 0) /* Tx Mon Delay Counter<9:8> */

TX_MON_DURATION

#define TX_MON_DURATION

(

x

)

Value:

(((x) & 0xF) << 0) /* Tx Mon Duration<3:0> */

TX_MON_HIGH_GAIN

#define TX_MON_HIGH_GAIN

(

x

)

Value:

(((x) & 0x1F) << 0) /* Tx Mon High Gain<4:0> */

TX_MON_LOW_GAIN

#define TX_MON_LOW_GAIN

(

x

)

Value:

(((x) & 0x1F) << 0) /* Tx Mon Low Gain<4:0> */

TX_MON_TRACK

#define TX_MON_TRACK   (1 << 5) /* Tx Mon Track */

TX_MONITOR_POWER_DOWN

#define TX_MONITOR_POWER_DOWN

(

x

)

Value:

(((x) & 0x3) << 2) /* Tx Monitor Power Down<1:0> */

TX_NCO_FREQ

#define TX_NCO_FREQ

(

x

)

Value:

(((x) & 0x3) << 6) /* Tx NCO frequency<1:0> */

TX_OUTPUT

#define TX_OUTPUT   (1 << 6) /* TX Output */

TX_QUAD_CAL

#define TX_QUAD_CAL   (1 << 4) /* Tx Quad Cal */

TX_REF_DIVIDER

#define TX_REF_DIVIDER

(

x

)

Value:

(((x) & 0x3) << 2) /* Tx Ref Divider<1:0> */

TX_REF_DOUBLER_FB_DELAY

#define TX_REF_DOUBLER_FB_DELAY

(

x

)

Value:

(((x) & 0x3) << 0) /* Tx Ref Doubler FB Delay<1:0> */

TX_REF_RESET_BAR

#define TX_REF_RESET_BAR   (1 << 4) /* Tx Ref Reset Bar */

TX_RSSI_1

#define TX_RSSI_1   (1 << 0) /* TX RSSI 1<0> */

TX_RSSI_2

#define TX_RSSI_2   (1 << 1) /* Tx RSSI 2<0> */

TX_SECONDARY_FILTER_POWER_DOWN

#define TX_SECONDARY_FILTER_POWER_DOWN

(

x

)

Value:

(((x) & 0x3) << 6) /* Tx Secondary Filter Power Down<1:0> */

TX_SYNTH_PTAT_POWER_DOWN

#define TX_SYNTH_PTAT_POWER_DOWN   (1 << 2) /* Tx Synth PTAT Power Down */

TX_SYNTH_READY_MASK

#define TX_SYNTH_READY_MASK   (1 << 0) /* Tx Synth Ready Mask */

TX_SYNTH_VCO_ALC_POWER_DOWN

#define TX_SYNTH_VCO_ALC_POWER_DOWN   (1 << 3) /* Tx Synth VCO ALC Power Down */

TX_SYNTH_VCO_LDO_POWER_DOWN

#define TX_SYNTH_VCO_LDO_POWER_DOWN   (1 << 0) /* Tx Synth VCO LDO Power Down */

TX_SYNTH_VCO_POWER_DOWN

#define TX_SYNTH_VCO_POWER_DOWN   (1 << 1) /* Tx Synth VCO Power Down */

TX_UPCONVERTER_POWER_DOWN

#define TX_UPCONVERTER_POWER_DOWN

(

x

)

Value:

(((x) & 0x3) << 0) /* Tx Upconverter Power Down<1:0> */

TX_VCO_DIVIDER

#define TX_VCO_DIVIDER

(

x

)

Value:

(((x) & 0xF) << 4) /* TX VCO  Divider<3:0> */

TXDAC_GN_I

#define TXDAC_GN_I

(

x

)

Value:

(((x) & 0x3F) << 0) /* txDAC_gn_I<5:0> */

TXDAC_GN_Q

#define TXDAC_GN_Q

(

x

)

Value:

(((x) & 0x3F) << 0) /* txDAC_gn_Q<5:0> */

TXDAC_VDS_I

#define TXDAC_VDS_I

(

x

)

Value:

(((x) & 0x3F) << 0) /* TxDAC Vds I<5:0> */

TXDAC_VDS_Q

#define TXDAC_VDS_Q

(

x

)

Value:

(((x) & 0x3F) << 0) /* TxDAC Vds Q<5:0> */

TXMON_CAL

#define TXMON_CAL   (1 << 2)

TXNRX_SPI_CTRL

#define TXNRX_SPI_CTRL   (1 << 4) /* TXNRX SPI Control */

UPDATE_FREQ_WORD [1/4]

#define UPDATE_FREQ_WORD   (1 << 7) /* Update Freq Word */

UPDATE_FREQ_WORD [2/4]

#define UPDATE_FREQ_WORD   (1 << 7) /* Update Freq Word */

UPDATE_FREQ_WORD [3/4]

#define UPDATE_FREQ_WORD   (1 << 7) /* Update Freq Word */

UPDATE_FREQ_WORD [4/4]

#define UPDATE_FREQ_WORD   (1 << 7) /* Update Freq Word */

UPDATE_TRACKING_WORD

#define UPDATE_TRACKING_WORD   (1 << 6) /* Update Tracking Word */

USE_AGC_FOR_LMTLPF_GAIN

#define USE_AGC_FOR_LMTLPF_GAIN   (1 << 3) /* Use AGC for LMT/LPF Gain */

USE_CTRL_IN_FOR_SYMBOL_ATTEN

#define USE_CTRL_IN_FOR_SYMBOL_ATTEN   (1 << 1) /* Use CTRL IN for symbol Atten */

USE_DATA_PORT

#define USE_DATA_PORT   (1 << 0) /* Use Data Port */

USE_HB1_OUT_FOR_DEC_PWR_MEAS

#define USE_HB1_OUT_FOR_DEC_PWR_MEAS   (1 << 6) /* Use HB1 Out for Dec pwr Meas */

USE_HB3_OUT_FOR_ADC_PWR_MEAS

#define USE_HB3_OUT_FOR_ADC_PWR_MEAS   (1 << 7) /* Use HB3 Out for ADC Pwr Meas */

USE_LAST_LOCK_LEVEL_FOR_SET_GAIN

#define USE_LAST_LOCK_LEVEL_FOR_SET_GAIN   (1 << 7) /* Use Last Lock Level for Set Gain */

USE_SETTLE_COUNT_FOR_DC_CAL_WAIT

#define USE_SETTLE_COUNT_FOR_DC_CAL_WAIT   (1 << 5) /* Use Settle Count for DC Cal Wait */

USE_TX1_PIN_SYMBOL_ATTEN

#define USE_TX1_PIN_SYMBOL_ATTEN   (1 << 3) /* Use Tx1 Pin & Symbol Atten */

USE_WAIT_COUNTER_FOR_RF_DC_INIT_CAL

#define USE_WAIT_COUNTER_FOR_RF_DC_INIT_CAL   (1 << 7) /* Use Wait Counter for RF DC Init Cal */

VBIAS_CTRL

#define VBIAS_CTRL

(

x

)

Value:

(((x) & 0x3) << 1) /* Vbias  Control<1:0> */

VCO_BIAS_REF [1/2]

#define VCO_BIAS_REF

(

x

)

Value:

(((x) & 0x7) << 0) /* VCO Bias Ref<2:0> */

VCO_BIAS_REF [2/2]

#define VCO_BIAS_REF

(

x

)

Value:

(((x) & 0x7) << 0) /* VCO Bias Ref<2:0> */

VCO_BIAS_TCF [1/2]

#define VCO_BIAS_TCF

(

x

)

Value:

(((x) & 0x3) << 3) /* VCO Bias Tcf<1:0> */

VCO_BIAS_TCF [2/2]

#define VCO_BIAS_TCF

(

x

)

Value:

(((x) & 0x3) << 3) /* VCO Bias Tcf<1:0> */

VCO_BYPASS_BIAS_DAC_R

#define VCO_BYPASS_BIAS_DAC_R   (1 << 7) /* VCO Bypass Bias DAC R */

VCO_CAL_ALC_WAIT [1/2]

#define VCO_CAL_ALC_WAIT

(

x

)

Value:

(((x) & 0x7) << 4) /* VCO Cal ALC Wait <2:0> */

VCO_CAL_ALC_WAIT [2/2]

#define VCO_CAL_ALC_WAIT

(

x

)

Value:

(((x) & 0x7) << 4) /* VCO Cal ALC Wait<2:0) */

VCO_CAL_BUSY [1/2]

#define VCO_CAL_BUSY   (1 << 4) /* VCO Cal Busy */

VCO_CAL_BUSY [2/2]

#define VCO_CAL_BUSY   (1 << 4) /* VCO Cal Busy */

VCO_CAL_COUNT [1/2]

#define VCO_CAL_COUNT

(

x

)

Value:

(((x) & 0x3) << 2) /* VCO Cal Count <1:0> */

VCO_CAL_COUNT [2/2]

#define VCO_CAL_COUNT

(

x

)

Value:

(((x) & 0x3) << 2) /* VCO Cal Count<1:0> */

VCO_CAL_EN [1/2]

#define VCO_CAL_EN   (1 << 7) /* VCO Cal En */

VCO_CAL_EN [2/2]

#define VCO_CAL_EN   (1 << 7) /* VCO Cal En */

VCO_CAL_OFFSET [1/2]

#define VCO_CAL_OFFSET

(

x

)

Value:

(((x) & 0xF) << 3) /* VCO Cal Offset<3:0> */

VCO_CAL_OFFSET [2/2]

#define VCO_CAL_OFFSET

(

x

)

Value:

(((x) & 0xF) << 3) /* VCO Cal Offset<3:0> */

VCO_CAL_REF_MONITOR

#define VCO_CAL_REF_MONITOR   (1 << 3) /* VCO Cal Ref Monitor */

VCO_CAL_REF_TCF [1/2]

#define VCO_CAL_REF_TCF

(

x

)

Value:

(((x) & 0x7) << 0) /* VCO Cal Ref Tcf<2:0> */

VCO_CAL_REF_TCF [2/2]

#define VCO_CAL_REF_TCF

(

x

)

Value:

(((x) & 0x7) << 0) /* VCO Cal Ref Tcf<2:0> */

VCO_COMP_BYPASS_BIAS_R

#define VCO_COMP_BYPASS_BIAS_R   (1 << 4) /* VCO Comp Bypass Bias R */

VCO_LDO_BYPASS [1/2]

#define VCO_LDO_BYPASS   (1 << 7) /* VCO LDO Bypass */

VCO_LDO_BYPASS [2/2]

#define VCO_LDO_BYPASS   (1 << 7) /* VCO LDO Bypass */

VCO_LDO_FILTER_BYPASS

#define VCO_LDO_FILTER_BYPASS   (1 << 7) /* VCO LDO Filter Bypass */

VCO_LDO_INRUSH [1/2]

#define VCO_LDO_INRUSH

(

x

)

Value:

(((x) & 0x3) << 5) /* VCO LDO Inrush<1:0> */

VCO_LDO_INRUSH [2/2]

#define VCO_LDO_INRUSH

(

x

)

Value:

(((x) & 0x3) << 5) /* VCO LDO Inrush<1:0> */

VCO_LDO_REF_SEL

#define VCO_LDO_REF_SEL   (1 << 6) /* VCO LDO Ref Sel */

VCO_LDO_SEL

#define VCO_LDO_SEL

(

x

)

Value:

(((x) & 0x7) << 2) /* VCO LDO Sel<2:0> */

VCO_LDO_VDROP_SEL [1/2]

#define VCO_LDO_VDROP_SEL

(

x

)

Value:

(((x) & 0x3) << 0) /* VCO LDO Vdrop Sel<1:0> */

VCO_LDO_VDROP_SEL [2/2]

#define VCO_LDO_VDROP_SEL

(

x

)

Value:

(((x) & 0x3) << 0) /* VCO LDO Vdrop Sel<1:0> */

VCO_LDO_VOUT_SEL

#define VCO_LDO_VOUT_SEL

(

x

)

Value:

(((x) & 0x7) << 2) /* VCO LDO Vout Sel<2:0> */

VCO_LOCK [1/2]

#define VCO_LOCK   (1 << 1) /* Lock */

VCO_LOCK [2/2]

#define VCO_LOCK   (1 << 1) /* Lock */

VCO_OUTPUT_LEVEL [1/2]

#define VCO_OUTPUT_LEVEL

(

x

)

Value:

(((x) & 0xF) << 0) /* VCO Output Level<3:0> */

VCO_OUTPUT_LEVEL [2/2]

#define VCO_OUTPUT_LEVEL

(

x

)

Value:

(((x) & 0xF) << 0) /* VCO Output Level<3:0> */

VCO_VARACTOR [1/2]

#define VCO_VARACTOR

(

x

)

Value:

(((x) & 0xF) << 0) /* VCO Varactor<3:0> */

VCO_VARACTOR [2/2]

#define VCO_VARACTOR

(

x

)

Value:

(((x) & 0xF) << 0) /* VCO Varactor<3:0> */

VCO_VARACTOR_OFFSET [1/2]

#define VCO_VARACTOR_OFFSET

(

x

)

Value:

(((x) & 0xF) << 0) /* VCO Varactor Offset<3:0> */

VCO_VARACTOR_OFFSET [2/2]

#define VCO_VARACTOR_OFFSET

(

x

)

Value:

(((x) & 0xF) << 0) /* VCO Varactor Offset<3:0> */

VCO_VARACTOR_REFERENCE [1/2]

#define VCO_VARACTOR_REFERENCE

(

x

)

Value:

(((x) & 0xF) << 0) /* VCO Varactor Reference<3:0> */

VCO_VARACTOR_REFERENCE [2/2]

#define VCO_VARACTOR_REFERENCE

(

x

)

Value:

(((x) & 0xF) << 0) /* VCO Varactor Reference<3:0> */

VCO_VARACTOR_REFERENCE_TCF [1/2]

#define VCO_VARACTOR_REFERENCE_TCF

(

x

)

Value:

(((x) & 0x7) << 4) /* VCO Varactor Reference Tcf<2:0> */

VCO_VARACTOR_REFERENCE_TCF [2/2]

#define VCO_VARACTOR_REFERENCE_TCF

(

x

)

Value:

(((x) & 0x7) << 4) /* VCO Varactor Reference Tcf<2:0> */

VTUNE_FORCE

#define VTUNE_FORCE   (1 << 6) /* Vtune Force */

WIRE3_SPI

#define WIRE3_SPI   (1 << 6) /* 3-Wire SPI */

WRITE_GAIN_TABLE

#define WRITE_GAIN_TABLE   (1 << 2) /* Write Gain Table */

WRITE_GM_SUB_TABLE

#define WRITE_GM_SUB_TABLE   (1 << 2) /* Write Gm Sub Table */

WRITE_LNA_ERROR_TABLE

#define WRITE_LNA_ERROR_TABLE   (1 << 2) /* Write LNA Error Table */

WRITE_LNA_GAIN_DIFF

#define WRITE_LNA_GAIN_DIFF   (1 << 1) /* Write LNA Gain Diff */

WRITE_MIXER_ERROR_TABLE

#define WRITE_MIXER_ERROR_TABLE   (1 << 3) /* Write Mixer Error Table */

WRITE_RX

#define WRITE_RX   (1 << 2) /* Write Rx */

XO_BYPASS

#define XO_BYPASS   (1 << 4) /* XO Bypass */

Enumeration Type Documentation

anonymous enum

anonymous enum

Enumerator
LUT_FTDD_40
LUT_FTDD_60
LUT_FTDD_80
LUT_FTDD_ENT

ad9361_bist_mode

enum ad9361_bist_mode

Enumerator
BIST_DISABLE
BIST_INJ_TX
BIST_INJ_RX

ad9361_clkout

enum ad9361_clkout

Enumerator
CLKOUT_DISABLE
BUFFERED_XTALN_DCXO
ADC_CLK_DIV_2
ADC_CLK_DIV_3
ADC_CLK_DIV_4
ADC_CLK_DIV_8
ADC_CLK_DIV_16

ad9361_clocks

enum ad9361_clocks

Enumerator
BB_REFCLK
RX_REFCLK
TX_REFCLK
BBPLL_CLK
ADC_CLK
R2_CLK
R1_CLK
CLKRF_CLK
RX_SAMPL_CLK
DAC_CLK
T2_CLK
T1_CLK
CLKTF_CLK
TX_SAMPL_CLK
RX_RFPLL_INT
TX_RFPLL_INT
RX_RFPLL_DUMMY
TX_RFPLL_DUMMY
RX_RFPLL
TX_RFPLL
NUM_AD9361_CLKS
EXT_REF_CLK

ad9361_pdata_rx_freq

enum ad9361_pdata_rx_freq

Enumerator
BBPLL_FREQ
ADC_FREQ
R2_FREQ
R1_FREQ
CLKRF_FREQ
RX_SAMPL_FREQ
NUM_RX_CLOCKS

ad9361_pdata_tx_freq

enum ad9361_pdata_tx_freq

Enumerator
IGNORE
DAC_FREQ
T2_FREQ
T1_FREQ
CLKTF_FREQ
TX_SAMPL_FREQ
NUM_TX_CLOCKS

debugfs_cmd

enum debugfs_cmd

Enumerator
DBGFS_NONE
DBGFS_INIT
DBGFS_LOOPBACK
DBGFS_BIST_PRBS
DBGFS_BIST_TONE
DBGFS_BIST_DT_ANALYSIS
DBGFS_RXGAIN_1
DBGFS_RXGAIN_2

dev_id

enum dev_id

Enumerator
ID_AD9361
ID_AD9364
ID_AD9363A

dig_tune_flags

enum dig_tune_flags

Enumerator
BE_VERBOSE
BE_MOREVERBOSE
DO_IDELAY
DO_ODELAY
SKIP_STORE_RESULT
RESTORE_DEFAULT

f_agc_target_gain_index_type

enum f_agc_target_gain_index_type

Enumerator
MAX_GAIN
SET_GAIN
OPTIMIZED_GAIN
NO_GAIN_CHANGE

fir_dest

enum fir_dest

Enumerator
FIR_TX1
FIR_TX2
FIR_TX1_TX2
FIR_RX1
FIR_RX2
FIR_RX1_RX2
FIR_IS_RX

rf_gain_ctrl_mode

enum rf_gain_ctrl_mode

Enumerator
RF_GAIN_MGC
RF_GAIN_FASTATTACK_AGC
RF_GAIN_SLOWATTACK_AGC
RF_GAIN_HYBRID_AGC

rssi_restart_mode

enum rssi_restart_mode

Enumerator
AGC_IN_FAST_ATTACK_MODE_LOCKS_THE_GAIN
EN_AGC_PIN_IS_PULLED_HIGH
ENTERS_RX_MODE
GAIN_CHANGE_OCCURS
SPI_WRITE_TO_REGISTER
GAIN_CHANGE_OCCURS_OR_EN_AGC_PIN_PULLED_HIGH

rx_gain_table_name

enum rx_gain_table_name

Enumerator
TBL_200_1300_MHZ
TBL_1300_4000_MHZ
TBL_4000_6000_MHZ
RXGAIN_TBLS_END

rx_gain_table_type

enum rx_gain_table_type

Enumerator
RXGAIN_FULL_TBL
RXGAIN_SPLIT_TBL

synth_pd_ctrl

enum synth_pd_ctrl

Enumerator
LO_DONTCARE
LO_OFF
LO_ON

Function Documentation

ad9361_1rx1tx_channel_map()

int32_t ad9361_1rx1tx_channel_map	(	struct ad9361_rf_phy *	phy,
		bool	tx,
		int32_t	channel )

Select the channel mapping in 1rx1tx mode.

Parameters

phy	The AD9361 state structure.
tx	TX
channel	Channel

Returns

The channel number.

ad9361_bbpll_recalc_rate()

uint32_t ad9361_bbpll_recalc_rate	(	struct refclk_scale *	clk_priv,
		uint32_t	parent_rate )

Recalculate the clock rate.

Parameters

clk_priv	The refclk_scale structure.
parent_rate	The parent clock rate.

Returns

The clock rate.

ad9361_bbpll_round_rate()

int32_t ad9361_bbpll_round_rate	(	struct refclk_scale *	clk_priv,
		uint32_t	rate,
		uint32_t *	prate )

Calculate the closest possible clock rate that can be set.

Parameters

clk_priv	The refclk_scale structure.
rate	The clock rate.
prate	The parent clock rate.

Returns

The closest possible clock rate that can be set.

ad9361_bbpll_set_rate()

int32_t ad9361_bbpll_set_rate	(	struct refclk_scale *	clk_priv,
		uint32_t	rate,
		uint32_t	parent_rate )

Set the clock rate.

Parameters

clk_priv	The refclk_scale structure.
rate	The clock rate.
parent_rate	The parent clock rate.

Returns

0 in case of success, negative error code otherwise.

ad9361_bist_loopback()

int32_t ad9361_bist_loopback	(	struct ad9361_rf_phy *	phy,
		int32_t	mode )

BIST loopback mode.

Parameters

phy	The AD9361 state structure.
mode	BIST loopback mode.

Returns

0 in case of success, negative error code otherwise.

ad9361_bist_prbs()

int32_t ad9361_bist_prbs	(	struct ad9361_rf_phy *	phy,
		enum ad9361_bist_mode	mode )

BIST mode.

Parameters

phy	The AD9361 state structure.
mode	Bist mode.

Returns

0 in case of success, negative error code otherwise.

ad9361_bist_tone()

int32_t ad9361_bist_tone	(	struct ad9361_rf_phy *	phy,
		enum ad9361_bist_mode	mode,
		uint32_t	freq_Hz,
		uint32_t	level_dB,
		uint32_t	mask )

BIST tone.

Parameters

phy	The AD9361 state structure.
mode	Bist tone mode.
freq_Hz	Bist tone frequency.
level_dB	Bist tone level.
mask	Bist reg mask.

Returns

0 in case of success, negative error code otherwise.

ad9361_calculate_rf_clock_chain()

int32_t ad9361_calculate_rf_clock_chain	(	struct ad9361_rf_phy *	phy,
		uint32_t	tx_sample_rate,
		uint32_t	rate_gov,
		uint32_t *	rx_path_clks,
		uint32_t *	tx_path_clks )

Calculate the RX and TX path rates to obtain the desired sample rate.

Parameters

phy	The AD9361 state structure.
tx_sample_rate	The desired sample rate.
rate_gov	The rate governor option.
rx_path_clks	RX path rates buffer.
tx_path_clks	TX path rates buffer.

Returns

0 in case of success, negative error code otherwise.

ad9361_clear_state()

void ad9361_clear_state

(

struct ad9361_rf_phy *

phy

)

Clear state.

Parameters

phy	The AD9361 state structure.

ad9361_clk_factor_recalc_rate()

uint32_t ad9361_clk_factor_recalc_rate	(	struct refclk_scale *	clk_priv,
		uint32_t	parent_rate )

Recalculate the clock rate.

Parameters

clk_priv	The refclk_scale structure.
parent_rate	The parent clock rate.

Returns

The clock rate.

ad9361_clk_factor_round_rate()

int32_t ad9361_clk_factor_round_rate	(	struct refclk_scale *	clk_priv,
		uint32_t	rate,
		uint32_t *	prate )

Calculate the closest possible clock rate that can be set.

Parameters

clk_priv	The refclk_scale structure.
rate	The clock rate.
prate	The parent clock rate.

Returns

The closest possible clock rate that can be set.

ad9361_clk_factor_set_rate()

int32_t ad9361_clk_factor_set_rate	(	struct refclk_scale *	clk_priv,
		uint32_t	rate,
		uint32_t	parent_rate )

Set the clock rate.

Parameters

clk_priv	The refclk_scale structure.
rate	The clock rate.
parent_rate	The parent clock rate.

Returns

0 in case of success, negative error code otherwise.

ad9361_clk_mux_set_parent()

int32_t ad9361_clk_mux_set_parent	(	struct refclk_scale *	clk_priv,
		uint8_t	index )

Set clock mux parent.

Parameters

clk_priv	The refclk_scale structure.
index	Index - Enable (1) external LO, disable (0) = use internal PLL.

Returns

0 in case of success, negative error code otherwise.

ad9361_dig_interface_timing_analysis()

int32_t ad9361_dig_interface_timing_analysis	(	struct ad9361_rf_phy *	phy,
		char *	buf,
		int32_t	buflen )

Digital interface timing analysis.

Parameters

phy	The AD9361 state structure.
buf	The buffer.
buflen	The buffer length.

Returns

The size in case of success, negative error code otherwise.

ad9361_dig_tune()

int32_t ad9361_dig_tune	(	struct ad9361_rf_phy *	phy,
		uint32_t	max_freq,
		enum dig_tune_flags	flags )

Digital tune.

Parameters

phy	The AD9361 state structure.
max_freq	Maximum frequency.
flags	Flags: BE_VERBOSE, BE_MOREVERBOSE, DO_IDELAY, DO_ODELAY.

Returns

0 in case of success, negative error code otherwise.

ad9361_do_calib_run()

int32_t ad9361_do_calib_run	(	struct ad9361_rf_phy *	phy,
		uint32_t	cal,
		int32_t	arg )

Perform the selected calibration

Parameters

phy	The AD9361 state structure.
cal	The selected calibration.
arg	The argument of the calibration.

Returns

0 in case of success, negative error code otherwise.

ad9361_en_dis_rx()

int32_t ad9361_en_dis_rx	(	struct ad9361_rf_phy *	phy,
		uint32_t	rx_if,
		uint32_t	enable )

Enable/disable the desired RX channel.

Parameters

phy	The AD9361 state structure.
rx_if	The desired channel number [1, 2].
enable	Enable/disable option.

Returns

0 in case of success, negative error code otherwise.

ad9361_en_dis_tx()

int32_t ad9361_en_dis_tx	(	struct ad9361_rf_phy *	phy,
		uint32_t	tx_if,
		uint32_t	enable )

Enable/disable the desired TX channel.

Parameters

phy	The AD9361 state structure.
tx_if	The desired channel number [1, 2].
enable	Enable/disable option.

Returns

0 in case of success, negative error code otherwise.

ad9361_ensm_force_state()

void ad9361_ensm_force_state	(	struct ad9361_rf_phy *	phy,
		uint8_t	ensm_state )

Force Enable State Machine (ENSM) to the desired state (internally used only).

Parameters

phy	The AD9361 state structure.
ensm_state	The ENSM state [ENSM_STATE_SLEEP_WAIT, ENSM_STATE_ALERT, ENSM_STATE_TX, ENSM_STATE_TX_FLUSH, ENSM_STATE_RX, ENSM_STATE_RX_FLUSH, ENSM_STATE_FDD, ENSM_STATE_FDD_FLUSH].

ad9361_ensm_get_state()

uint8_t ad9361_ensm_get_state

(

struct ad9361_rf_phy *

phy

)

Get Enable State Machine (ENSM) state.

Parameters

phy	The AD9361 state structure.

Returns

The state.

ad9361_ensm_mode_disable_pinctrl()

int32_t ad9361_ensm_mode_disable_pinctrl

(

struct ad9361_rf_phy *

phy

)

Temporarily disable ENSM pin control by forcing TDD SPI mode. Useful before calibration sequences that must use SPI-driven state.

Parameters

phy	The AD9361 state structure.

Returns

0 on success, negative error code otherwise.

ad9361_ensm_mode_restore_pinctrl()

int32_t ad9361_ensm_mode_restore_pinctrl

(

struct ad9361_rf_phy *

phy

)

Restore ENSM pin control to the state configured in pdata.

Parameters

phy	The AD9361 state structure.

Returns

0 on success, negative error code otherwise.

ad9361_ensm_restore_prev_state()

void ad9361_ensm_restore_prev_state

(

struct ad9361_rf_phy *

phy

)

Restore the previous Enable State Machine (ENSM) state.

Parameters

phy	The AD9361 state structure.

ad9361_ensm_restore_state()

void ad9361_ensm_restore_state	(	struct ad9361_rf_phy *	phy,
		uint8_t	ensm_state )

Restore an Enable State Machine (ENSM) state.

Parameters

phy	The AD9361 state structure.
ensm_state	The state.

ad9361_ensm_set_state()

int32_t ad9361_ensm_set_state	(	struct ad9361_rf_phy *	phy,
		uint8_t	ensm_state,
		bool	pinctrl )

Set the desired Enable State Machine (ENSM) state.

Parameters

phy	The AD9361 state structure.
ensm_state	The ENSM state [ENSM_STATE_SLEEP_WAIT, ENSM_STATE_ALERT, ENSM_STATE_TX, ENSM_STATE_TX_FLUSH, ENSM_STATE_RX, ENSM_STATE_RX_FLUSH, ENSM_STATE_FDD, ENSM_STATE_FDD_FLUSH].
pinctrl	Set true, will enable the ENSM pin control.

Returns

0 in case of success, negative error code otherwise.

ad9361_fastlock_load()

int32_t ad9361_fastlock_load	(	struct ad9361_rf_phy *	phy,
		bool	tx,
		uint32_t	profile,
		uint8_t *	values )

Fastlock load values.

Parameters

phy	The AD9361 state structure.
tx
profile
values

Returns

0 in case of success, negative error code otherwise.

ad9361_fastlock_recall()

int32_t ad9361_fastlock_recall	(	struct ad9361_rf_phy *	phy,
		bool	tx,
		uint32_t	profile )

Fastlock recall.

Parameters

phy	The AD9361 state structure.
tx
profile

Returns

0 in case of success, negative error code otherwise.

ad9361_fastlock_save()

int32_t ad9361_fastlock_save	(	struct ad9361_rf_phy *	phy,
		bool	tx,
		uint32_t	profile,
		uint8_t *	values )

Fastlock save.

Parameters

phy	The AD9361 state structure.
tx
profile
values

Returns

0 in case of success, negative error code otherwise.

ad9361_fastlock_store()

int32_t ad9361_fastlock_store	(	struct ad9361_rf_phy *	phy,
		bool	tx,
		uint32_t	profile )

Fastlock store.

Parameters

phy	The AD9361 state structure.
tx
profile

Returns

0 in case of success, negative error code otherwise.

ad9361_find_opt()

int32_t ad9361_find_opt	(	uint8_t *	field,
		uint32_t	size,
		uint32_t *	ret_start )

Find optimal value.

Parameters

field
size
ret_start

Returns

The optimal delay in case of success, negative error code otherwise.

ad9361_from_clk()

uint64_t ad9361_from_clk

(

uint32_t

freq

)

Shift back the frequency value, so it reflects the real value. Note: PLL operates between 47 .. 6000 MHz which is > 2^32.

Parameters

freq	The frequency value [Hz].

Returns

The shifted frequency value.

ad9361_get_bist_loopback()

void ad9361_get_bist_loopback	(	struct ad9361_rf_phy *	phy,
		int32_t *	mode )

Get BIST loopback mode.

Parameters

phy	The AD9361 state structure.
mode	BIST loopback mode.

ad9361_get_bist_prbs()

void ad9361_get_bist_prbs	(	struct ad9361_rf_phy *	phy,
		enum ad9361_bist_mode *	mode )

Get BIST mode settings.

Parameters

phy	The AD9361 state structure.
mode	Bist mode.

ad9361_get_bist_tone()

void ad9361_get_bist_tone	(	struct ad9361_rf_phy *	phy,
		enum ad9361_bist_mode *	mode,
		uint32_t *	freq_Hz,
		uint32_t *	level_dB,
		uint32_t *	mask )

Get BIST tone settings.

Parameters

phy	The AD9361 state structure.
mode	Bist tone mode.
freq_Hz	Bist tone frequency.
level_dB	Bist tone level.
mask	Bist reg mask.

ad9361_get_dig_tune_data()

int32_t ad9361_get_dig_tune_data	(	struct ad9361_rf_phy *	phy,
		struct ad9361_dig_tune_data *	data )

Return the current digital interface tuning state.

Parameters

phy	The AD9361 state structure.
data	Output: populated with skip_mode and current delay register values.

Returns

0 on success, negative error code otherwise.

ad9361_get_rx_gain()

int32_t ad9361_get_rx_gain	(	struct ad9361_rf_phy *	phy,
		uint32_t	rx_id,
		struct rf_rx_gain *	rx_gain )

Get current RX gain for the selected channel.

Parameters

phy	The AD9361 state structure.
rx_id	The desired channel number (0, 1).
rx_gain	A rf_rx_gain struct to store the RF gain.

Returns

0 in case of success, negative error code otherwise.

ad9361_get_temp()

int32_t ad9361_get_temp

(

struct ad9361_rf_phy *

phy

)

Get the measured temperature of the device.

Parameters

phy	The AD9361 state structure.

Returns

The measured temperature of the device.

ad9361_get_trx_clock_chain()

int32_t ad9361_get_trx_clock_chain	(	struct ad9361_rf_phy *	phy,
		uint32_t *	rx_path_clks,
		uint32_t *	tx_path_clks )

Get the RX and TX path rates.

Parameters

phy	The AD9361 state structure.
rx_path_clks	RX path rates buffer.
tx_path_clks	TX path rates buffer.

Returns

0 in case of success, negative error code otherwise.

ad9361_get_tx_atten()

int32_t ad9361_get_tx_atten	(	struct ad9361_rf_phy *	phy,
		uint32_t	tx_num )

Get the attenuation for the selected TX channel.

Parameters

phy	The AD9361 state structure.
tx_num	The selected channel [1, 2].

Returns

The attenuation value [mdB] or negative error code in case of failure.

ad9361_gt()

uint32_t ad9361_gt

(

struct ad9361_rf_phy *

phy

)

Return the current gain table index.

Parameters

phy	The AD9361 state structure.

Returns

The current gain table index or 0 if the table was not chosen.

ad9361_hdl_loopback()

int32_t ad9361_hdl_loopback	(	struct ad9361_rf_phy *	phy,
		bool	enable )

HDL loopback enable/disable.

Parameters

phy	The AD9361 state structure.
enable	Enable/disable option.

Returns

0 in case of success, negative error code otherwise.

ad9361_init_gain_tables()

int32_t ad9361_init_gain_tables

(

struct ad9361_rf_phy *

phy

)

ad9361_load_fir_filter_coef()

int32_t ad9361_load_fir_filter_coef	(	struct ad9361_rf_phy *	phy,
		enum fir_dest	dest,
		int32_t	gain_dB,
		uint32_t	ntaps,
		short *	coef )

ad9361_mcs()

int32_t ad9361_mcs	(	struct ad9361_rf_phy *	phy,
		int32_t	step )

Multi Chip Sync (MCS) config.

Parameters

phy	The AD9361 state structure.
step	MCS step.

Returns

0 in case of success, negative error code otherwise.

ad9361_post_setup()

int32_t ad9361_post_setup

(

struct ad9361_rf_phy *

phy

)

Setup the AD9361 device.

Parameters

phy	The AD9361 state structure.

Returns

0 in case of success, negative error code otherwise.

ad9361_read_clock_data_delays()

int32_t ad9361_read_clock_data_delays

(

struct ad9361_rf_phy *

phy

)

Read the current RX and TX clock/data delay register values back into pdata. Call this after ad9361_dig_tune() to persist the tuned values.

Parameters

phy	The AD9361 state structure.

Returns

0 on success, negative error code otherwise.

ad9361_read_rssi()

int32_t ad9361_read_rssi	(	struct ad9361_rf_phy *	phy,
		struct rf_rssi *	rssi )

Get the RSSI.

Parameters

phy	The AD9361 state structure.
rssi	A rf_rssi struct to store the RSSI.

Returns

0 in case of success, negative error code otherwise.

ad9361_reg_read()

int32_t ad9361_reg_read	(	struct ad9361_rf_phy *	phy,
		uint32_t	reg,
		uint32_t *	val )

IIO SPI register read.

Parameters

phy	The AD9361 state structure.
reg	The register address.
val	The value read from register address.

Returns

The register value or negative error code in case of failure.

ad9361_reg_write()

int32_t ad9361_reg_write	(	struct ad9361_rf_phy *	phy,
		uint32_t	reg,
		uint32_t	val )

IIO SPI register write.

Parameters

phy	The AD9361 state structure.
reg	The register address.
val	The value of the register.

Returns

0 in case of success, negative error code otherwise.

ad9361_register_clocks()

int32_t ad9361_register_clocks

(

struct ad9361_rf_phy *

phy

)

Register and initialize all the system clocks.

Parameters

phy	The AD9361 state structure.

Returns

0 in case of success, negative error code otherwise.

ad9361_reset()

int32_t ad9361_reset

(

struct ad9361_rf_phy *

phy

)

AD9361 Device Reset

Parameters

phy	The AD9361 state structure.

Returns

0 in case of success, negative error code otherwise.

ad9361_rf_port_setup()

int32_t ad9361_rf_port_setup	(	struct ad9361_rf_phy *	phy,
		bool	is_out,
		uint32_t	rx_inputs,
		uint32_t	txb )

Setup the RF port. Note: val 0 (RX1A_N & RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced 1 (RX1B_N & RX1B_P) and (RX2B_N & RX2B_P) enabled; balanced 2 (RX1C_N & RX1C_P) and (RX2C_N & RX2C_P) enabled; balanced

3 RX1A_N and RX2A_N enabled; unbalanced 4 RX1A_P and RX2A_P enabled; unbalanced 5 RX1B_N and RX2B_N enabled; unbalanced 6 RX1B_P and RX2B_P enabled; unbalanced 7 RX1C_N and RX2C_N enabled; unbalanced 8 RX1C_P and RX2C_P enabled; unbalanced 9 TX_MON1 10 TX_MON2 11 TX_MON1 & TX_MON2

Parameters

phy	The AD9361 state structure.
is_out	TX RF output port enabled.
rx_inputs	RX input option identifier
txb	TX output option identifier

Returns

0 in case of success, negative error code otherwise.

ad9361_rfpll_dummy_recalc_rate()

uint32_t ad9361_rfpll_dummy_recalc_rate

(

struct refclk_scale *

clk_priv

)

Recalculate the clock rate.

Parameters

clk_priv

The refclk_scale structure.

Returns

The clock rate.

ad9361_rfpll_dummy_set_rate()

int32_t ad9361_rfpll_dummy_set_rate	(	struct refclk_scale *	clk_priv,
		uint32_t	rate )

Set the clock rate.

Parameters

clk_priv	The refclk_scale structure.
rate	The clock rate.

Returns

0 in case of success, negative error code otherwise.

ad9361_rfpll_int_recalc_rate()

uint32_t ad9361_rfpll_int_recalc_rate	(	struct refclk_scale *	clk_priv,
		uint32_t	parent_rate )

Recalculate the clock rate.

Parameters

clk_priv	The refclk_scale structure.
parent_rate	The parent clock rate.

Returns

The clock rate.

ad9361_rfpll_int_round_rate()

int32_t ad9361_rfpll_int_round_rate	(	struct refclk_scale *	clk_priv,
		uint32_t	rate,
		uint32_t *	prate )

Calculate the closest possible clock rate that can be set.

Parameters

clk_priv	The refclk_scale structure.
rate	The clock rate.
prate	The parent clock rate.

Returns

The closest possible clock rate that can be set.

ad9361_rfpll_int_set_rate()

int32_t ad9361_rfpll_int_set_rate	(	struct refclk_scale *	clk_priv,
		uint32_t	rate,
		uint32_t	parent_rate )

Set the clock rate.

Parameters

clk_priv	The refclk_scale structure.
rate	The clock rate.
parent_rate	The parent clock rate.

Returns

0 in case of success, negative error code otherwise.

ad9361_rfpll_recalc_rate()

uint32_t ad9361_rfpll_recalc_rate

(

struct refclk_scale *

clk_priv

)

Recalculate the clock rate.

Parameters

clk_priv

The refclk_scale structure.

Returns

The clock rate.

ad9361_rfpll_round_rate()

int32_t ad9361_rfpll_round_rate	(	struct refclk_scale *	clk_priv,
		uint32_t	rate )

Calculate the closest possible clock rate that can be set.

Parameters

clk_priv	The refclk_scale structure.
rate	The clock rate.

Returns

The closest possible clock rate that can be set.

ad9361_rfpll_set_rate()

int32_t ad9361_rfpll_set_rate	(	struct refclk_scale *	clk_priv,
		uint32_t	rate )

Set the clock rate.

Parameters

clk_priv	The refclk_scale structure.
rate	The clock rate.

Returns

0 in case of success, negative error code otherwise.

ad9361_rssi_gain_step_calib()

int32_t ad9361_rssi_gain_step_calib

(

struct ad9361_rf_phy *

phy

)

Perform an RSSI gain step calibration. Note: Before running the function, provide a single tone within the channel bandwidth and monitor the received data. Adjust the tone amplitude until the received data is within a few dB of full scale but not overloading.

Parameters

phy	The AD9361 state structure.

Returns

0 in case of success, negative error code otherwise.

ad9361_rssi_program_lna_gain()

int32_t ad9361_rssi_program_lna_gain

(

struct ad9361_rf_phy *

phy

)

Program the LNA gain step values from pdata->rssi_gain_step_calib_reg_val into the AD9361 gain-step calibration table.

Parameters

phy	The AD9361 state structure.

Returns

0 on success, negative error code otherwise.

ad9361_rssi_write_err_tbl()

int32_t ad9361_rssi_write_err_tbl

(

struct ad9361_rf_phy *

phy

)

Write the pre-loaded LNA and mixer error tables from pdata into hardware.

Parameters

phy	The AD9361 state structure.

Returns

0 on success, negative error code otherwise.

ad9361_set_cal_sw()

int32_t ad9361_set_cal_sw	(	struct ad9361_rf_phy *	phy,
		uint32_t	val )

Drive the external calibration switch GPIOs (cal-sw1, cal-sw2). Bit 0 of val controls cal-sw1, bit 1 controls cal-sw2. These GPIOs route signals for TX quad / LO calibration on boards that have external calibration switch hardware.

Parameters

phy	The AD9361 state structure.
val	2-bit value: bit0 = cal_sw1, bit1 = cal_sw2.

Returns

0 on success, -ENODEV if GPIOs are not configured.

ad9361_set_dcxo_tune()

int32_t ad9361_set_dcxo_tune	(	struct ad9361_rf_phy *	phy,
		uint32_t	coarse,
		uint32_t	fine )

Setup the DCXO tune.

Parameters

phy	The AD9361 state structure.
coarse	The DCXO tune coarse.
fine	The DCXO tune fine.

Returns

0 in case of success, negative error code otherwise.

ad9361_set_ensm_mode()

int32_t ad9361_set_ensm_mode	(	struct ad9361_rf_phy *	phy,
		bool	fdd,
		bool	pinctrl )

Internal ENSM mode options helper function.

Parameters

phy	The AD9361 state structure.
fdd
pinctrl

Returns

0 in case of success, negative error code otherwise.

ad9361_set_gain_ctrl_mode()

int32_t ad9361_set_gain_ctrl_mode	(	struct ad9361_rf_phy *	phy,
		struct rf_gain_ctrl *	gain_ctrl )

Set the gain control mode.

Parameters

phy	The AD9361 state structure.
gain_ctrl	A rf_gain_ctrl struct that contains the the desired channel information and the gain control mode.

Returns

0 in case of success, negative error code otherwise.

ad9361_set_rx_gain()

int32_t ad9361_set_rx_gain	(	struct ad9361_rf_phy *	phy,
		uint32_t	rx_id,
		struct rf_rx_gain *	rx_gain )

Set the RX gain for the selected channel.

Parameters

phy	The AD9361 state structure.
rx_id	The desired channel number (0, 1).
rx_gain	The rf_rx_gain struct containing the RF gain.

Returns

0 in case of success, negative error code otherwise.

ad9361_set_trx_clock_chain()

int32_t ad9361_set_trx_clock_chain	(	struct ad9361_rf_phy *	phy,
		uint32_t *	rx_path_clks,
		uint32_t *	tx_path_clks )

Set the RX and TX path rates.

Parameters

phy	The AD9361 state structure.
rx_path_clks	RX path rates buffer.
tx_path_clks	TX path rates buffer.

Returns

0 in case of success, negative error code otherwise.

ad9361_set_trx_clock_chain_freq()

int32_t ad9361_set_trx_clock_chain_freq	(	struct ad9361_rf_phy *	phy,
		uint32_t	freq )

Set the desired sample rate.

Parameters

phy	The AD9361 state structure.
freq	The desired sample rate.

Returns

0 in case of success, negative error code otherwise.

ad9361_set_tx_atten()

int32_t ad9361_set_tx_atten	(	struct ad9361_rf_phy *	phy,
		uint32_t	atten_mdb,
		bool	tx1,
		bool	tx2,
		bool	immed )

Set the attenuation for the selected TX channels.

Parameters

phy	The AD9361 state structure.
atten_mdb	Attenuation value [mdB].
tx1	Set true, the attenuation of the TX1 will be affected.
tx2	Set true, the attenuation of the TX2 will be affected.
immed	Set true, an immediate update will take place.

Returns

0 in case of success, negative error code otherwise.

ad9361_setup()

int32_t ad9361_setup

(

struct ad9361_rf_phy *

phy

)

Setup the AD9361 device.

Parameters

phy	The AD9361 state structure.

Returns

0 in case of success, negative error code otherwise.

ad9361_spi_read()

int32_t ad9361_spi_read	(	struct no_os_spi_desc *	spi,
		uint32_t	reg )

SPI register read.

Parameters

spi
reg	The register address.

Returns

The register value or negative error code in case of failure.

ad9361_spi_readm()

int32_t ad9361_spi_readm	(	struct no_os_spi_desc *	spi,
		uint32_t	reg,
		uint8_t *	rbuf,
		uint32_t	num )

SPI multiple bytes register read.

Parameters

spi
reg	The register address.
rbuf	The data buffer.
num	The number of bytes to read.

Returns

0 in case of success, negative error code otherwise.

ad9361_spi_write()

int32_t ad9361_spi_write	(	struct no_os_spi_desc *	spi,
		uint32_t	reg,
		uint32_t	val )

SPI register write.

Parameters

spi
reg	The register address.
val	The value of the register.

Returns

0 in case of success, negative error code otherwise.

ad9361_synth_lo_powerdown()

int ad9361_synth_lo_powerdown	(	struct ad9361_rf_phy *	phy,
		enum synth_pd_ctrl	rx,
		enum synth_pd_ctrl	tx )

Power down the TX and/or RX Local Oscillators.

Parameters

phy	The AD9361 state structure.
rx	The RX LO setting.
tx	The TX LO setting.

Returns

0 in case of success, negative error code otherwise.

ad9361_to_clk()

uint32_t ad9361_to_clk

(

uint64_t

freq

)

Shift the real frequency value, so it fits type unsigned long Note: PLL operates between 47 .. 6000 MHz which is > 2^32.

Parameters

freq	The frequency value [Hz].

Returns

The shifted frequency value.

ad9361_tracking_control()

int32_t ad9361_tracking_control	(	struct ad9361_rf_phy *	phy,
		bool	bbdc_track,
		bool	rfdc_track,
		bool	rxquad_track )

Setup RX tracking calibrations.

Parameters

phy	The AD9361 state structure.
bbdc_track	Set true, will enable the BBDC tracking.
rfdc_track	Set true, will enable the RFDC tracking.
rxquad_track	Set true, will enable the RXQUAD tracking.

Returns

0 in case of success, negative error code otherwise.

ad9361_tx_mute()

int32_t ad9361_tx_mute	(	struct ad9361_rf_phy *	phy,
		uint32_t	state )

Mute TX.

Parameters

phy	The AD9361 state structure.
state	The state - 0 mute; 1 - unmute.

Returns

0 in case of success

ad9361_unregister_clocks()

int32_t ad9361_unregister_clocks

(

struct ad9361_rf_phy *

phy

)

Unregister all the system clocks.

Parameters

phy	The AD9361 state structure.

Returns

0 in case of success, negative error code otherwise.

ad9361_update_rf_bandwidth()

int32_t ad9361_update_rf_bandwidth	(	struct ad9361_rf_phy *	phy,
		uint32_t	rf_rx_bw,
		uint32_t	rf_tx_bw )

Set the RF bandwidth.

Parameters

phy	The AD9361 state structure.
rf_rx_bw	The desired RX bandwidth [Hz].
rf_tx_bw	The desired TX bandwidth [Hz].

Returns

0 in case of success, negative error code otherwise.

ad9361_validate_enable_fir()

int32_t ad9361_validate_enable_fir

(

struct ad9361_rf_phy *

phy

)

Validate FIR filter configuration - on pass enable.

Parameters

phy	The AD9361 state structure.

Returns

0 in case of success, negative error code otherwise.

ad9361_validate_rf_bw()

uint32_t ad9361_validate_rf_bw	(	struct ad9361_rf_phy *	phy,
		uint32_t	bw )

Validate RF BW frequency.

Parameters

phy	The AD9361 state structure.
bw	The RF BW frequency.

Returns

The validated RF BW frequency.

ad9361_write_bist_reg()

int32_t ad9361_write_bist_reg	(	struct ad9361_rf_phy *	phy,
		uint32_t	val )

Write directly to the AD9361 BIST configuration register.

Parameters

phy	The AD9361 state structure.
val	Value to write.

Returns

0 on success, negative error code otherwise.

ad9361_write_clock_data_delays()

int32_t ad9361_write_clock_data_delays

(

struct ad9361_rf_phy *

phy

)

Write the saved RX and TX clock/data delay values from pdata to hardware. Call this at startup to restore previously tuned values and skip dig_tune.

Parameters

phy	The AD9361 state structure.

Returns

0 on success, negative error code otherwise.