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36#include "app_config.h"
40#include "xparameters.h"
47#define GPIO_DEVICE_ID 0
48#define SPI_DEVICE_ID 0
50#define GPIO_BASEADDR SYS_GPIO_OUT_BASE
51#define SPI_BASEADDR SYS_SPI_BASE
53#define DDR_MEM_BASEADDR SYS_DDR3_CNTRL_ARCH_BASE
54#define ADC_DDR_BASEADDR SYS_DDR3_CNTRL_ARCH_BASE + 0x800000
55#define DAC_DDR_BASEADDR SYS_DDR3_CNTRL_ARCH_BASE + 0xA000000
57#define RX_A10_FPLL_BASEADDR AD9371_RX_JESD204_LINK_PLL_RECONFIG_BASE
58#define TX_A10_FPLL_BASEADDR AD9371_TX_JESD204_LINK_PLL_RECONFIG_BASE
59#define RX_OS_A10_FPLL_BASEADDR AD9371_RX_OS_JESD204_LINK_PLL_RECONFIG_BASE
61#define RX_JESD_BASEADDR AD9371_RX_JESD204_LINK_RECONFIG_BASE
62#define TX_JESD_BASEADDR AD9371_TX_JESD204_LINK_RECONFIG_BASE
63#define RX_OS_JESD_BASEADDR AD9371_RX_OS_JESD204_LINK_RECONFIG_BASE
65#define RX_XCVR_BASEADDR AD9371_RX_JESD204_LINK_MANAGEMENT_BASE
66#define TX_XCVR_BASEADDR AD9371_TX_JESD204_LINK_MANAGEMENT_BASE
67#define RX_OS_XCVR_BASEADDR AD9371_RX_OS_JESD204_LINK_MANAGEMENT_BASE
69#define RX_ADXCFG_0_BASEADDR AVL_ADXCFG_0_RCFG_S1_BASE
70#define RX_ADXCFG_1_BASEADDR AVL_ADXCFG_1_RCFG_S1_BASE
71#define TX_ADXCFG_0_BASEADDR AVL_ADXCFG_0_RCFG_S0_BASE
72#define TX_ADXCFG_1_BASEADDR AVL_ADXCFG_1_RCFG_S0_BASE
73#define TX_ADXCFG_2_BASEADDR AVL_ADXCFG_2_RCFG_S0_BASE
74#define TX_ADXCFG_3_BASEADDR AVL_ADXCFG_3_RCFG_S0_BASE
75#define RX_OS_ADXCFG_0_BASEADDR AVL_ADXCFG_2_RCFG_S1_BASE
76#define RX_OS_ADXCFG_1_BASEADDR AVL_ADXCFG_3_RCFG_S1_BASE
78#define TX_PLL_BASEADDR AD9371_TX_JESD204_LANE_PLL_RECONFIG_BASE
80#define RX_CORE_BASEADDR AXI_AD9371_BASE
81#define TX_CORE_BASEADDR AXI_AD9371_BASE + 0x4000
82#define RX_OS_CORE_BASEADDR AXI_AD9371_BASE + 0x8000
84#define RX_OBS_DMA_BASEADDR AXI_AD9371_RX_OS_DMA_BASE
85#define RX_DMA_BASEADDR AXI_AD9371_RX_DMA_BASE
86#define TX_DMA_BASEADDR AXI_AD9371_TX_DMA_BASE
88#ifdef _XPARAMETERS_PS_H_
89#ifdef XPS_BOARD_ZCU102
92#define GPIO_DEVICE_ID XPAR_PSU_GPIO_0_DEVICE_ID
93#define SPI_DEVICE_ID XPAR_PSU_SPI_0_DEVICE_ID
94#define UART_IRQ_ID XPAR_XUARTPS_0_INTR
98#define GPIO_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
99#define SPI_DEVICE_ID XPAR_PS7_SPI_0_DEVICE_ID
100#define UART_IRQ_ID XPAR_XUARTPS_1_INTR
103#define DDR_MEM_BASEADDR XPAR_DDR_MEM_BASEADDR
107#define GPIO_DEVICE_ID XPAR_GPIO_0_DEVICE_ID
108#define SPI_DEVICE_ID XPAR_SPI_0_DEVICE_ID
109#define UART_IRQ_ID XPAR_AXI_INTC_AXI_UART_INTERRUPT_INTR
111#define DDR_MEM_BASEADDR XPAR_AXI_DDR_CNTRL_BASEADDR
114#define RX_CLKGEN_BASEADDR XPAR_AXI_AD9371_RX_CLKGEN_BASEADDR
115#define TX_CLKGEN_BASEADDR XPAR_AXI_AD9371_TX_CLKGEN_BASEADDR
116#define RX_OS_CLKGEN_BASEADDR XPAR_AXI_AD9371_RX_OS_CLKGEN_BASEADDR
118#define RX_JESD_BASEADDR XPAR_AXI_AD9371_RX_JESD_RX_AXI_BASEADDR
119#define TX_JESD_BASEADDR XPAR_AXI_AD9371_TX_JESD_TX_AXI_BASEADDR
120#define RX_OS_JESD_BASEADDR XPAR_AXI_AD9371_RX_OS_JESD_RX_AXI_BASEADDR
122#define RX_XCVR_BASEADDR XPAR_AXI_AD9371_RX_XCVR_BASEADDR
123#define TX_XCVR_BASEADDR XPAR_AXI_AD9371_TX_XCVR_BASEADDR
124#define RX_OS_XCVR_BASEADDR XPAR_AXI_AD9371_RX_OS_XCVR_BASEADDR
126#ifdef XPAR_AXI_AD9371_CORE_BASEADDR
127#define RX_CORE_BASEADDR XPAR_AXI_AD9371_CORE_BASEADDR
128#define TX_CORE_BASEADDR XPAR_AXI_AD9371_CORE_BASEADDR + 0x4000
129#define RX_OS_CORE_BASEADDR XPAR_AXI_AD9371_CORE_BASEADDR + 0x8000
131#define RX_CORE_BASEADDR XPAR_RX_AD9371_TPL_CORE_ADC_TPL_CORE_BASEADDR
132#define TX_CORE_BASEADDR XPAR_TX_AD9371_TPL_CORE_DAC_TPL_CORE_BASEADDR
133#define RX_OS_CORE_BASEADDR XPAR_RX_OS_AD9371_TPL_CORE_ADC_TPL_CORE_BASEADDR
136#define RX_OBS_DMA_BASEADDR XPAR_AXI_AD9371_RX_OS_DMA_BASEADDR
137#define RX_DMA_BASEADDR XPAR_AXI_AD9371_RX_DMA_BASEADDR
138#define TX_DMA_BASEADDR XPAR_AXI_AD9371_TX_DMA_BASEADDR
141#if defined(DMA_EXAMPLE) || defined(IIO_SUPPORT)
142#define DAC_BUFFER_SAMPLES 4096
143#define ADC_BUFFER_SAMPLES 16384
144#define ADC_CHANNELS 4
147#ifdef _XPARAMETERS_PS_H_
148#define UART_DEVICE_ID XPAR_XUARTPS_0_DEVICE_ID
149#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
151#define UART_DEVICE_ID XPAR_AXI_UART_DEVICE_ID
152#define INTC_DEVICE_ID XPAR_INTC_SINGLE_DEVICE_ID
157#define DAC_GPIO_PLDDR_BYPASS GPIO_OFFSET + 60
158#define AD9528_RESET_B GPIO_OFFSET + 59
159#define AD9528_SYSREF_REQ GPIO_OFFSET + 58
160#define AD9371_RESET_B GPIO_OFFSET + 52