no-OS
adas1000.h
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1 /***************************************************************************/
36 #ifndef _ADAS1000_H_
37 #define _ADAS1000_H_
38 
39 /*****************************************************************************/
40 /***************************** Include Files *********************************/
41 /*****************************************************************************/
42 
43 #include <stdint.h>
44 #include <stdbool.h>
45 #include "no_os_spi.h"
46 
47 /******************************************************************************/
48 /* ADAS1000 SPI Registers Memory Map */
49 /******************************************************************************/
50 
51 #define ADAS1000_COMM_WRITE 0x80 /* SPI Write command */
52 #define ADAS1000_RDY_MASK 0x40 /* READY bit mask */
53 #define ADAS1000_ALL_CH_MASK 0x00 /* Word mask for activating all channels */
54 #define ADAS1000_WD_CNT_MASK 0x01 /* Word count mask */
55 
56 #define ADAS1000_NOP 0x00 /* NOP (No operation) */
57 #define ADAS1000_ECGCTL 0x01 /* ECG Setting Register */
58 #define ADAS1000_LOFFCTL 0x02 /* Leads off Control Register */
59 #define ADAS1000_RESPCTL 0x03 /* Respiration Control Register */
60 #define ADAS1000_PACECTL 0x04 /* Pace Detection Control Register */
61 #define ADAS1000_CMREFCTL 0x05 /* Common Mode Reference and Shield Drive Control Register */
62 #define ADAS1000_GPIOCTL 0x06 /* GPIO Control Register */
63 #define ADAS1000_PACEAMPTH 0x07 /* Pace Amplitude Threshold2 */
64 #define ADAS1000_TESTTONE 0x08 /* Test Tone */
65 #define ADAS1000_CALDAC 0x09 /* Calibration DAC */
66 #define ADAS1000_FRMCTL 0x0A /* Frame Control Register */
67 #define ADAS1000_FILTCTL 0x0B /* Filter Control Register */
68 #define ADAS1000_LOFFUTH 0x0C /* Leads off Upper Threshold */
69 #define ADAS1000_LOFFLTH 0x0D /* Leads off Lower Threshold */
70 #define ADAS1000_PACEEDGETH 0x0E /* Pace Edge Threshold */
71 #define ADAS1000_PACELVLTH 0x0F /* Pace Level Threshold */
72 #define ADAS1000_LADATA 0x11 /* LA or LEAD I Data */
73 #define ADAS1000_LLDATA 0x12 /* LL or LEAD II Data */
74 #define ADAS1000_RADATA 0x13 /* RA or LEAD III Data */
75 #define ADAS1000_V1DATA 0x14 /* V1 or V1 Data */
76 #define ADAS1000_V2DATA 0x15 /* V2 or V2 Data */
77 #define ADAS1000_PACEDATA 0x1A /* Read Pace Detection Data */
78 #define ADAS1000_RESPMAG 0x1B /* Read Respiration Data Magnitude */
79 #define ADAS1000_RESPPH 0x1C /* Read Respiration Data Phase */
80 #define ADAS1000_LOFF 0x1D /* Leads Off Status */
81 #define ADAS1000_DCLEADSOFF 0x1E /* DC Leads off Register */
82 #define ADAS1000_EXTENDSW 0x20 /* Extended Switch for respiration inputs */
83 #define ADAS1000_CALLA 0x21 /* User gain calibration LA */
84 #define ADAS1000_CALLL 0x22 /* User gain calibration LL */
85 #define ADAS1000_CALRA 0x23 /* User gain calibration RA */
86 #define ADAS1000_CALV1 0x24 /* User gain calibration V1 */
87 #define ADAS1000_CALV2 0x25 /* User gain calibration V2 */
88 #define ADAS1000_LOAMLA 0x31 /* Leads off Amplitude for LA */
89 #define ADAS1000_LOAMLL 0x32 /* Leads off Amplitude for LL */
90 #define ADAS1000_LOAMRA 0x33 /* Leads off Amplitude for RA */
91 #define ADAS1000_LOAMV1 0x34 /* Leads off Amplitude for V1 */
92 #define ADAS1000_LOAMV2 0x35 /* Leads off Amplitude for V2 */
93 #define ADAS1000_PACE1_DATA 0x3A /* Pace1 Width & Amplitude2 */
94 #define ADAS1000_PACE2_DATA 0x3B /* Pace2 Width & Amplitude2 */
95 #define ADAS1000_PACE3_DATA 0x3C /* Pace3 Width & Amplitude2 */
96 #define ADAS1000_FRAMES 0x40 /* Frame Header - Read Data Frames */
97 #define ADAS1000_CRC 0x41 /* Frame CRC */
98 
99 /******************************************************************************/
100 /* ECG Setting Register */
101 /******************************************************************************/
102 /* ECG Channel Enable, shuts down power to the channel, the input is
103  now HiZ : 1 = enabled, 0 = disabled */
104 #define ADAS1000_ECGCTL_LAEN (1ul << 23)
105 /* ECG Channel Enable, shuts down power to the channel, the input is
106  now HiZ : 1 = enabled, 0 = disabled */
107 #define ADAS1000_ECGCTL_LLEN (1ul << 22)
108 /* ECG Channel Enable, shuts down power to the channel, the input is
109  now HiZ : 1 = enabled, 0 = disabled */
110 #define ADAS1000_ECGCTL_RAEN (1ul << 21)
111 /* ECG Channel Enable, shuts down power to the channel, the input is
112  now HiZ : 1 = enabled, 0 = disabled */
113 #define ADAS1000_ECGCTL_V1EN (1ul << 20)
114 /* ECG Channel Enable, shuts down power to the channel, the input is
115  now HiZ : 1 = enabled, 0 = disabled */
116 #define ADAS1000_ECGCTL_V2EN (1ul << 19)
117 /* Setting this bit selects the differential AFE input:
118  0 = Single Ended Input Digital Lead Mode or Electrode Mode,
119  1 = Differential Input Analog Lead Mode */
120 #define ADAS1000_ECGCTL_CHCONFIG (1ul << 10)
121 /* Pre-Amp & Anti-Aliasing Filter Overall Gain:
122  00 = GAIN 0 = x1.4, 01 = GAIN 1 = x2.1,
123  10 = GAIN 2 = x2.8, 11 = GAIN 3 = x4.2 */
124 #define ADAS1000_ECGCTL_GAIN (1ul << 8)
125 /* VREF Buffer Enable: 0 = Disabled, 1 = Enabled (when using internal
126  VREF, the VREFBUF must be enabled) */
127 #define ADAS1000_ECGCTL_VREFBUF (1ul << 7)
128 /* Use external clock instead of crystal oscillator. The crystal oscillator
129  is automatically disabled if configured as SLAVE in Gang mode and the
130  Slave device should receive the CLK from the Master device:
131  0 = XTAL is CLK source, 1 = CLK_IO is CLK source. */
132 #define ADAS1000_ECGCTL_CLKEXT (1ul << 6)
133 /* In gang mode, this bit selects the master (SYNC_GANG pin is configured
134  as an output). When in Single Channel Mode (GANG = 0), this bit is ignored:
135  0 = Slave, 1 = Master */
136 #define ADAS1000_ECGCTL_MASTER (1ul << 5)
137 /* Enable gang mode. Setting this bit causes the CLK_IO and to be activated:
138  0 = Single Channel mode, 1 = Gang Mode */
139 #define ADAS1000_ECGCTL_GANG (1ul << 4)
140 /* Selects the noise/power performance, this bit controls the ADC sampling
141  frequency. See specifications for further details:
142  0 = 1MSPS - low power, 1 = 2 MSPS - High performance/low noise */
143 #define ADAS1000_ECGCTL_HP (1ul << 3)
144 /* Convert Enable - Setting this bit enables the ADC conversion and filters:
145  0 = Idle, 1 = Conversion Enable */
146 #define ADAS1000_ECGCTL_CNVEN (1ul << 2)
147 /* Power Enable - clearing this bit powers down the device. All analog blocks
148  are powered down and the external crystal is disabled:
149  0 = Power Down, 1 = Power Enable */
150 #define ADAS1000_ECGCTL_PWREN (1ul << 1)
151 /* Software Reset - setting this bit clears all registers to their reset value.
152  This bit automatically clears itself. The software reset requires a NOP
153  command to complete the reset: 0 = NOP, 1 = Reset */
154 
155 #define ADAS1000_ECGCTL_SWRST (1ul << 0)
156 /******************************************************************************/
157 /* Leads off Control Register */
158 /******************************************************************************/
159 /* AC Leads Off Phase: 0 = in phase, 1 = 180deg out of phase */
160 #define ADAS1000_LOFFCTL_LAPH (1ul << 23)
161 /* AC Leads Off Phase: 0 = in phase, 1 = 180deg out of phase */
162 #define ADAS1000_LOFFCTL_LLPH (1ul << 22)
163 /* AC Leads Off Phase: 0 = in phase, 1 = 180deg out of phase */
164 #define ADAS1000_LOFFCTL_RAPH (1ul << 21)
165 /* AC Leads Off Phase: 0 = in phase, 1 = 180deg out of phase */
166 #define ADAS1000_LOFFCTL_V1PH (1ul << 20)
167 /* AC Leads Off Phase: 0 = in phase, 1 = 180deg out of phase */
168 #define ADAS1000_LOFFCTL_V2PH (1ul << 19)
169 /* AC Leads Off Phase: 0 = in phase, 1 = 180deg out of phase */
170 #define ADAS1000_LOFFCTL_CEPH (1ul << 18)
171 /* Individual electrode AC Leads off enable. AC Leads off enables are
172  the OR of ACSEL and the individual AC Leads off Channel enables.
173  0 = AC Leads off disabled, 1 = AC Leads off enabled */
174 #define ADAS1000_LOFFCTL_LAACLOEN (1ul << 17)
175 /* Individual electrode AC Leads off enable. AC Leads off enables are
176  the OR of ACSEL and the individual AC Leads off Channel enables.
177  0 = AC Leads off disabled, 1 = AC Leads off enabled */
178 #define ADAS1000_LOFFCTL_LLACLOEN (1ul << 16)
179 /* Individual electrode AC Leads off enable. AC Leads off enables are
180  the OR of ACSEL and the individual AC Leads off Channel enables.
181  0 = AC Leads off disabled, 1 = AC Leads off enabled */
182 #define ADAS1000_LOFFCTL_RAACLOEN (1ul << 15)
183 /* Individual electrode AC Leads off enable. AC Leads off enables are
184  the OR of ACSEL and the individual AC Leads off Channel enables.
185  0 = AC Leads off disabled, 1 = AC Leads off enabled */
186 #define ADAS1000_LOFFCTL_V1ACLOEN (1ul << 14)
187 /* Individual electrode AC Leads off enable. AC Leads off enables are
188  the OR of ACSEL and the individual AC Leads off Channel enables.
189  0 = AC Leads off disabled, 1 = AC Leads off enabled */
190 #define ADAS1000_LOFFCTL_V2ACLOEN (1ul << 13)
191 /* Individual electrode AC Leads off enable. AC Leads off enables are
192  the OR of ACSEL and the individual AC Leads off Channel enables.
193  0 = AC Leads off disabled, 1 = AC Leads off enabled */
194 #define ADAS1000_LOFFCTL_CEACLOEN (1ul << 12)
195 /* Set Current level for AC leads off (only active for ACSEL = 1).
196  00 = 12.5nA rms, 01 = 25nA rms,
197  10 = 50nA rms, 11 = 100nA rms */
198 #define ADAS1000_LOFFCTL_ACCURREN (1ul << 7)
199 /* Set Current level for DC leads off (only active for ACSEL = 0)
200  000 = 0nA, 001 = 10nA, 010 = 20nA, 011 = 30nA,
201  100 = 40nA, 101 = 50nA, 110 = 60nA, 111 = 70nA */
202 #define ADAS1000_LOFFCTL_DCCURRENT (1ul << 2)
203 /* DC or AC (out of band) Leads Off Detection. If LOFFEN = 0, this bit
204  is don't care. If LOFFEN = 1, 0 = DC Leads Off Detection enabled.
205  (Individual AC leads off may be enabled through bits 12-17),
206  1 = DC Leads off Detection disabled. AC Leads Off Detection enabled
207  (all electrodes except CE electrode). */
208 #define ADAS1000_LOFFCTL_ACSEL (1ul << 1)
209 /* Enable Leads Off Detection:
210  0 = Leads Off Disabled, 1 = Leads Off Enabled */
211 #define ADAS1000_LOFFCTL_LOFFEN (1ul << 0)
212 
213 /******************************************************************************/
214 /* Respiration Control Register */
215 /******************************************************************************/
216 /* Set to one to enable the MSB of the respiration DAC to be driven
217  out onto the GPIO[3] pin. This 64kHz signal can be used to
218  synchronize an external generator to the respiration carrier.
219  0 = normal GPIO3 function, 1 = MSB of RESPDAC driven onto GPIO[3] */
220 #define ADAS1000_RESPCTL_RESPEXTSYNC (1ul << 15)
221 /* For use with external instrumentation amplifier with respiration
222  circuit. Bypasses the on chip amplifier stage and input directly
223  to the ADC. */
224 #define ADAS1000_RESPCTL_RESPEXTAMP (1ul << 14)
225 /* Selects external respiration drive output. RESPDAC_RA is
226  automatically selected when RESPCAP = 1, 0 = RESPDAC _LL, 1 = RESPDAC_LA */
227 #define ADAS1000_RESPCTL_RESPOUT (1ul << 13)
228 /* Selects source of Respiration Capacitors.
229  0 = Use internal capacitors, 1 = Use external capacitors */
230 #define ADAS1000_RESPCTL_RESPCAP (1ul << 12)
231 /* Respiration Inamp Gain (saturates at 10):
232  0000 = x1 gain, 0001 = x2 gain, 0010 = x3 gain,
233  ...
234  1000 = x9 gain, 1001 = x10 gain, 11xx = x10 gain */
235 #define ADAS1000_RESPCTL_RESPGAIN (1ul << 8)
236 /* Selects between EXT_RESP _LA or EXT_RESP_LL paths. Only applies
237  if External Respiration is selected in RESPSEL. EXT_RESP_RA
238  automatically gets enabled. 0 = EXT_RESP_LL, 1 = EXT_RESP _LA */
239 #define ADAS1000_RESPCTL_RESPEXTSEL (1ul << 7)
240 /* Set Leads for Respiration Measurement:
241  00 = Lead I, 01 = Lead II,
242  10 = Lead III, 11 = External Respiration path */
243 #define ADAS1000_RESPCTL_RESPSEL (1ul << 5)
244 /* Set the test tone amplitude for respiration:
245  00 = Amplitude/8, 01 = Amplitude/4,
246  10 = Amplitude/2, 11 = Amplitude */
247 #define ADAS1000_RESPCTL_RESPAMP (1ul << 3)
248 /* Set Frequency for Respiration:
249  00 = 56kHz, 01 = 54kHz, 10 = 52kHz, 11 = 50kHz */
250 #define ADAS1000_RESPCTL_RESPFREQ (1ul << 1)
251 /* Enable Respiration:
252  0 = Respiration Disabled, 1 = Respiration Enabled */
253 #define ADAS1000_RESPCTL_RESPEN (1ul << 0)
254 
255 #define ADAS1000_RESPCTL_RESPGAIN_MASK (0x0000000Ful << 8)
256 #define ADAS1000_RESPCTL_RESPSEL_MASK (0x00000003ul << 5)
257 
258 /******************************************************************************/
259 /* Pace Detection Control Register */
260 /******************************************************************************/
261 /* Pace width Filter:
262  0 = Filter Disabled, 1 = Filter Enabled */
263 #define ADAS1000_PACECTL_PACEFILTW (1ul << 11)
264 /* Pace validation filter 2:
265  0 = Filter Disabled, 1 = Filter Enabled */
266 #define ADAS1000_PACECTL_PACETFILT2 (1ul << 10)
267 /* Pace validation filter 1:
268  0 = Filter Disabled, 1 = Filter Enabled */
269 #define ADAS1000_PACECTL_PACETFILT1 (1ul << 9)
270 /* Set Lead for Pace Detection Measurement:
271  00 = Lead I, 01 = Lead II, 10 = Lead III, 11 = Lead aVF */
272 #define ADAS1000_PACECTL_PACE3SEL (1ul << 7)
273 /* Set Lead for Pace Detection Measurement:
274  00 = Lead I, 01 = Lead II, 10 = Lead III, 11 = Lead aVF */
275 #define ADAS1000_PACECTL_PACE2SEL (1ul << 5)
276 /* Set Lead for Pace Detection Measurement:
277  00 = Lead I, 01 = Lead II, 10 = Lead III, 11 = Lead aVF */
278 #define ADAS1000_PACECTL_PACE1SEL (1ul << 3)
279 /* Enable Pace Detection Algorithm:
280  0 = Pace Detection Disabled, 1 = Pace Detection Enabled */
281 #define ADAS1000_PACECTL_PACE3EN (1ul << 2)
282 /* Enable Pace Detection Algorithm:
283  0 = Pace Detection Disabled, 1 = Pace Detection Enabled */
284 #define ADAS1000_PACECTL_PACE2EN (1ul << 1)
285 /* Enable Pace Detection Algorithm:
286  0 = Pace Detection Disabled, 1 = Pace Detection Enabled */
287 #define ADAS1000_PACECTL_PACE1EN (1ul << 0)
288 #define ADAS1000_PACECTL_PACE3SEL_MASK (0x00000003ul << 7)
289 #define ADAS1000_PACECTL_PACE2SEL_MASK (0x00000003ul << 5)
290 #define ADAS1000_PACECTL_PACE1SEL_MASK (0x00000003ul << 3)
291 
292 /******************************************************************************/
293 /* Common Mode Reference and Shield Drive Control Register */
294 /******************************************************************************/
295 /* Common Mode Electrode Select */
296 #define ADAS1000_CMREFCTL_LACM (1ul << 23)
297 /* Any combination of the 5 input electrodes can be used to create the */
298 #define ADAS1000_CMREFCTL_LLCM (1ul << 22)
299 /* Common Mode signal, or the Common Mode signal can be driven from the */
300 #define ADAS1000_CMREFCTL_RACM (1ul << 21)
301 /* internal reference. Bits 23:19 are ignored when bit 2 is selected. */
302 #define ADAS1000_CMREFCTL_V1CM (1ul << 20)
303 /* The Common Mode is the average of the selected electrodes. When a */
304 /* single electrode is selected, the Common Mode is the signal level of */
305 /* that electrode alone. */
306 /* 0 = does not contribute to the common mode */
307 /* 1 = contributes to the common mode */
308 #define ADAS1000_CMREFCTL_V2CM (1ul << 19)
309 /* RLD Summing Junction
310  0 = does not contribute to RLD input
311  1 = contributes to RLD input */
312 #define ADAS1000_CMREFCTL_LARLD (1ul << 14)
313 /* RLD Summing Junction
314  0 = does not contribute to RLD input
315  1 = contributes to RLD input */
316 #define ADAS1000_CMREFCTL_LLRLD (1ul << 13)
317 /* RLD Summing Junction
318  0 = does not contribute to RLD input
319  1 = contributes to RLD input */
320 #define ADAS1000_CMREFCTL_RARLD (1ul << 12)
321 /* RLD Summing Junction
322  0 = does not contribute to RLD input
323  1 = contributes to RLD input */
324 #define ADAS1000_CMREFCTL_V1RLD (1ul << 11)
325 /* RLD Summing Junction
326  0 = does not contribute to RLD input
327  1 = contributes to RLD input */
328 #define ADAS1000_CMREFCTL_V2RLD (1ul << 10)
329 /* RLD Summing Junction
330  0 = does not contribute to RLD input
331  1 = contributes to RLD input */
332 #define ADAS1000_CMREFCTL_CERLD (1ul << 9)
333 /* Common Electrode Reference
334  0 = Common Electrode disabled
335  1 = Common Electrode enabled */
336 #define ADAS1000_CMREFCTL_CEREFEN (1ul << 8)
337 /* Select electrode for reference drive
338  0000 = RL, 0001 = LA, 0010 = LL,
339  0011 = RA, 0100 = V1, 0101 = V2,
340  0110 to 1111 = Reserved */
341 #define ADAS1000_CMREFCTL_RLDSEL (1ul << 4)
342 /* Common mode output - when set, the internally derived common mode
343  signal is driven out the common mode pin. This bit has no effect
344  if external common mode is selected.
345  0 = common mode is not driven out
346  1 = common mode is driven out the external common mode pin */
347 #define ADAS1000_CMREFCTL_DRVCM (1ul << 3)
348 /* Select the source of Common Mode
349  (use when operating multiple devices together)
350  0 = Internal Common Mode selected
351  1 = External Common Mode selected */
352 #define ADAS1000_CMREFCTL_EXTCM (1ul << 2)
353 /* Enable Right Leg Drive Reference Electrode
354  0 = Disabled
355  1 = Enabled */
356 #define ADAS1000_CMREFCTL_RLD_EN (1ul << 1)
357 /* Enable Shield Drive
358  0 = Shield Drive Disabled
359  1 = Shield Drive Enabled */
360 #define ADAS1000_CMREFCTL_SHLDEN (1ul << 0)
361 
362 #define ADAS1000_CMREFCTL_RLDSEL_MASK (0x0000000Ful << 4)
363 
364 /******************************************************************************/
365 /* GPIO Control Register */
366 /******************************************************************************/
367 /* Frame secondary SPI words with chip select
368  0 = MCS asserted for entire frame
369  1 = MCS asserted for individual word */
370 #define ADAS1000_GPIOCTL_SPIFW (1ul << 18)
371 /* Secondary SPI Enable (ADAS1000 and ADAS1000-2 only) (SPI interface
372  providing ECG data at 128kHz data rate for external digital pace
373  algorithm detection � uses GPIO0, GPIO1, GPIO2 pins)
374  0 = Disabled
375  1 = Enabled. The individual control bits for GPIO0, GPIO1,
376  GPIO2 are ignored. GPIO3 is not affected by SPIEN */
377 #define ADAS1000_GPIOCTL_SPIEN (1ul << 16)
378 /* State of GPIO<3>
379  00 = High Impedance, 01 = Input,
380  10 = Output, 11 = Open Drain */
381 #define ADAS1000_GPIOCTL_G3CTL (1ul << 14)
382 /* Output Value to be written to GPIO<3> when pad is configured as an
383  output or open drain
384  0 = Low Value
385  1 = High Value */
386 #define ADAS1000_GPIOCTL_G3OUT (1ul << 13)
387 /* (Read Only) Input Value read from GPIO<3> when pad is configured as an input
388  0 = Low Value
389  1 = High Value */
390 #define ADAS1000_GPIOCTL_G3IN (1ul << 12)
391 /* State of GPIO<2>
392  00 = High Impedance, 01 = Input,
393  10 = Output, 11 = Open Drain */
394 #define ADAS1000_GPIOCTL_G2CTL (1ul << 10)
395 /* Output Value to be written to GPIO<2> when pad is configured as an
396  output or open drain
397  0 = Low Value
398  1 = High Value */
399 #define ADAS1000_GPIOCTL_G2OUT (1ul << 9)
400 /* (Read Only) Input Value read from GPIO<2> when pad is configured as an input.
401  0 = Low Value
402  1 = High Value */
403 #define ADAS1000_GPIOCTL_G2IN (1ul << 8)
404 /* State of GPIO<1>
405  00 = High Impedance, 01 = Input,
406  10 = Output, 11 = Open Drain */
407 #define ADAS1000_GPIOCTL_G1CTL (1ul << 6)
408 /* Output Value to be written to GPIO<1> when pad is configured as an
409  output or open drain.
410  0 = Low Value
411  1 = High Value */
412 #define ADAS1000_GPIOCTL_G1OUT (1ul << 5)
413 /* (Read Only) Input Value read from GPIO<1> when pad is configured as an input.
414  0 = Low Value
415  1 = High Value */
416 #define ADAS1000_GPIOCTL_G1IN (1ul << 4)
417 /* State of GPIO<0>
418  00 = High Impedance, 01 = Input,
419  10 = Output, 11 = Open Drain */
420 #define ADAS1000_GPIOCTL_G0CTL (1ul << 2)
421 /* Output Value to be written to GPIO<0> when pad is configured as an
422  output or open drain.
423  0 = Low Value
424  1 = High Value */
425 #define ADAS1000_GPIOCTL_G0OUT (1ul << 1)
426 /* (Read Only) Input Value read from GPIO<0> when pad is configured
427  as an input
428  0 = Low Value
429  1 = High Value */
430 #define ADAS1000_GPIOCTL_G0IN (1ul << 0)
431 #define ADAS1000_GPIOCTL_G3CTL_MASK (0x00000003ul << 14)
432 #define ADAS1000_GPIOCTL_G2CTL_MASK (0x00000003ul << 10)
433 #define ADAS1000_GPIOCTL_G1CTL_MASK (0x00000003ul << 6)
434 #define ADAS1000_GPIOCTL_G0CTL_MASK (0x00000003ul << 2)
435 
436 /******************************************************************************/
437 /* Pace Amplitude Threshold2 Register */
438 /******************************************************************************/
439 /* Pace Amplitude Thresold */
440 #define ADAS1000_PACEAMPTH_PACE3AMPTH (1ul << 16)
441 /* Threshold = N - VREF/GAIN/216 */
442 #define ADAS1000_PACEAMPTH_PACE2AMPTH (1ul << 8)
443 #define ADAS1000_PACEAMPTH_PACE1AMPTH (1ul << 0)
444 
445 #define ADAS1000_PACEAMPTH_PACE3AMPTH_MASK (0x000000FFul << 16)
446 #define ADAS1000_PACEAMPTH_PACE2AMPTH_MASK (0x000000FFul << 8)
447 #define ADAS1000_PACEAMPTH_PACE1AMPTH_MASK (0x000000FFul << 0)
448 
449 /******************************************************************************/
450 /* Test Tone Register */
451 /******************************************************************************/
452 /* Tone Select */
453 #define ADAS1000_TESTTONE_TONLA (1ul << 23)
454 /* 0 = 1.3V VCM_REF */
455 #define ADAS1000_TESTTONE_TONLL (1ul << 22)
456 /* 1 = 1mV sinewave or squarewave for toneint, no connect for tonext */
457 #define ADAS1000_TESTTONE_TONRA (1ul << 21)
458 #define ADAS1000_TESTTONE_TONV1 (1ul << 20)
459 #define ADAS1000_TESTTONE_TONV2 (1ul << 19)
460 /* 00 = 10Hz Sine Wave
461  01 = 150Hz Sine Wave
462  1x = 1Hz 1mV Square Wave */
463 #define ADAS1000_TESTTONE_TONTYPE (1ul << 3)
464 /* Test Tone Internal or External
465  0 = External Test Tone
466  1 = Internal Test Tone */
467 #define ADAS1000_TESTTONE_TONINT (1ul << 2)
468 /* Test Tone out Enable
469  0 = disconnects test tone from CAL_DAC_IO during internal mode only
470  1 = Connects CAL_DAC_IO to test tone during internal mode. */
471 #define ADAS1000_TESTTONE_TONOUT (1ul << 1)
472 /* Enables an internal test tone to drive entire signal chain, from
473  pre-amp to SPI interface. This tone comes from the CAL DAC and goes
474  to the pre-amps through the internal mux. When TONEN (CALDAC) is
475  enabled, AC Leads off is disabled.
476  0 = Disable the test tone
477  1 = Enable the CALDAC 1mV SineWave test tone (Cal Mode has priority) */
478 #define ADAS1000_TESTTONE_TONEN (1ul << 0)
479 
480 #define ADAS1000_TESTTONE_TONTYPE_MASK (0x00000003ul << 3)
481 
482 /******************************************************************************/
483 /* Calibration DAC Register */
484 /******************************************************************************/
485 /* Calibration Chop Clock Enable. The CALDAC output can be chopped to
486  lower 1/f noise. Chopping is done at 256kHz.
487  0 = Disabled
488  1 = Enabled. */
489 #define ADAS1000_CALDAC_CALCHPEN (1ul << 13)
490 /* Calibration Mode Enable
491  0 = Disable Calibration mode
492  1 = Enable Calibration mode - connect CAL DAC_IO,
493  begin data acquisition on ECG channels. */
494 #define ADAS1000_CALDAC_CALMODEEN (1ul << 12)
495 /* Calibration Internal or External
496  0 = External Cal - calibration to be performed externally by
497  looping CAL_DAC_IO around into ECG channels.
498  1 = Internal Cal - disconnects external switches for all ECG
499  channels and connects CALDAC internally to all ECG channels. */
500 #define ADAS1000_CALDAC_CALINT (1ul << 11)
501 /* Enable 10-bit calibration DAC for cal mode or external use.
502  0 = Disable CALDAC
503  1 = Enable CALDAC, if a master device and not in calibration
504  mode then also connects CAL_DAC out to its_IO pin for
505  external use, if in Slave mode, the CALDAC will disable to
506  allow master to drive CAL_DAC_IO pin. When CALDAC is enabled,
507  AC Leads off is disabled. */
508 #define ADAS1000_CALDAC_CALDACEN (1ul << 10)
509 /* Set the CAL DAC value */
510 #define ADAS1000_CALDAC_CALDATA (1ul << 0)
511 
512 #define ADAS1000_CALDAC_CALDATA_MASK (0x000003FFul << 0)
513 
514 /******************************************************************************/
515 /* Frame Control Register */
516 /******************************************************************************/
517 /* Include/Exclude word from ECG data frame, if electrode/lead is
518  included in the data word and the electrode falls off, then the
519  data word will be undefined.
520  0 = Included in Frame
521  1 = Exclude from Frame */
522 #define ADAS1000_FRMCTL_LEAD_I_LADIS (1ul << 23)
523 #define ADAS1000_FRMCTL_LEAD_II_LLDIS (1ul << 22)
524 #define ADAS1000_FRMCTL_LEAD_III_RADIS (1ul << 21)
525 #define ADAS1000_FRMCTL_V1DIS (1ul << 20)
526 #define ADAS1000_FRMCTL_V2DIS (1ul << 19)
527 /* Include/Exclude word from ECG data frame
528  0 = Included in Frame
529  1 = Exclude from Frame */
530 #define ADAS1000_FRMCTL_PACEDIS (1ul << 14)
531 /* Respiration Magnitude
532  0 = Included in Frame
533  1 = Exclude from Frame */
534 #define ADAS1000_FRMCTL_RESPMDIS (1ul << 13)
535 /* Respiration Phase
536  0 = Included in Frame
537  1 = Exclude from Frame */
538 #define ADAS1000_FRMCTL_RESPPHDIS (1ul << 12)
539 /* Leads Off Status
540  0 = Included in Frame
541  1 = Exclude from Frame */
542 #define ADAS1000_FRMCTL_LOFFDIS (1ul << 11)
543 /* GPIO Word disable
544  0 = Included in Frame
545  1 = Exclude from Frame */
546 #define ADAS1000_FRMCTL_GPIODIS (1ul << 10)
547 /* CRC Word disable
548  0 = Included in Frame
549  1 = Exclude from Frame */
550 #define ADAS1000_FRMCTL_CRCDIS (1ul << 9)
551 /* In a master device configured for Lead Mode, the ECG data will
552  be signed. When in slave mode (electrode format), the ECG data
553  format is unsigned. Use this bit when using multiple devices to
554  make the slave device signed data.
555  0 = unsigned data (default)
556  1 = signed data */
557 #define ADAS1000_FRMCTL_SIGNEDEN (1ul << 8)
558 /* Automatically disable PACE, RESP, LOFF words if their flags are
559  not set in the header.
560  0 = fixed frame format
561  1 = auto disable words */
562 #define ADAS1000_FRMCTL_ADIS (1ul << 7)
563 /* Ready Repeat � if this bit is set and the frame header indicates
564  data is not ready, the frame header is continuously sent until
565  data is ready.
566  0 = always send entire frame
567  1 = repeat frame header until ready */
568 #define ADAS1000_FRMCTL_RDYRPT (1ul << 6)
569 /* Sets the Output Data Format
570  0 = Lead/Vector Format
571  (only available in 2kHz & 16kHz data rates)
572  1 = Electrode Format */
573 #define ADAS1000_FRMCTL_DATAFMT (1ul << 4)
574 /* Skip interval - this field provides a way to decimate the data
575  00 = output every frame
576  01 = output every other frame
577  1x = output every 4th frame */
578 #define ADAS1000_FRMCTL_SKIP (1ul << 2)
579 /* Sets the Output Data Rate to 2 kHz */
580 #define ADAS1000_FRMCTL_FRMRATE_2KHZ 0x00
581 /* Sets the Output Data Rate to 16 kHz */
582 #define ADAS1000_FRMCTL_FRMRATE_16KHZ 0x01
583 /* Sets the Output Data Rate to 128 kHz */
584 #define ADAS1000_FRMCTL_FRMRATE_128KHZ 0x10
585 /* Sets the Output Data Rate to 31.25 Hz */
586 #define ADAS1000_FRMCTL_FRMRATE_31_25HZ 0x11
587 
588 #define ADAS1000_FRMCTL_WORD_MASK (ADAS1000_FRMCTL_LEAD_I_LADIS | \
589  ADAS1000_FRMCTL_LEAD_II_LLDIS | \
590  ADAS1000_FRMCTL_LEAD_III_RADIS | \
591  ADAS1000_FRMCTL_V1DIS | \
592  ADAS1000_FRMCTL_V2DIS | \
593  ADAS1000_FRMCTL_PACEDIS | \
594  ADAS1000_FRMCTL_RESPMDIS | \
595  ADAS1000_FRMCTL_RESPPHDIS | \
596  ADAS1000_FRMCTL_LOFFDIS | \
597  ADAS1000_FRMCTL_GPIODIS | \
598  ADAS1000_FRMCTL_CRCDIS)
599 #define ADAS1000_FRMCTL_SKIP_MASK (0x00000003ul << 2)
600 #define ADAS1000_FRMCTL_FRMRATE_MASK (0x00000003ul << 0)
601 
602 /******************************************************************************/
603 /* Filter Control Register */
604 /******************************************************************************/
605 /* 2kHz notch bypass for SPI Master
606  0 = notch filter bypassed
607  1 = notch filter present */
608 #define ADAS1000_FILTCTL_MN2K (1ul << 5)
609 /* 2kHz notch bypass
610  0 = notch filter present
611  1 = notch filter bypassed */
612 #define ADAS1000_FILTCTL_N2KBP (1ul << 4)
613 /* 00 = 40Hz
614  01 = 150Hz
615  10 = 250 Hz
616  11 = 450Hz */
617 #define ADAS1000_FILTCTL_LPF (1ul << 2)
618 
619 #define ADAS1000_FILTCTL_LPF_MASK (0x00000003ul << 2)
620 
621 /******************************************************************************/
622 /* Leads off Upper Threshold Register */
623 /******************************************************************************/
624 /* ADC over range threshold. An ADC out-of-range error will be flagged
625  if the ADC output is greater than the over range threshold.
626  The over range threshold is offset from the maximum value.
627  Threshold = max_value � ADCOVER*2^6
628  0000 = max value (disabled)
629  0001 = max_value - 64
630  0010 = max_value - 128
631  ...
632  1111: max_value - 960 */
633 #define ADAS1000_LOFFUTH_ADCOVER (1ul << 16)
634 /* AC Leads off upper Threshold. Leads off will be detected if the DC
635  or AC output is = N * 2 * VREF/GAIN/2^16. 0 = 0V */
636 #define ADAS1000_LOFFUTH_LOFFUTH (1ul << 0)
637 
638 #define ADAS1000_LOFFUTH_ADCOVER_MASK (0x0000000Ful << 16)
639 #define ADAS1000_LOFFUTH_LOFFUTH_MASK (0x0000FFFFul << 0)
640 
641 /******************************************************************************/
642 /* Leads off Lower Threshold Register */
643 /******************************************************************************/
644 /* ADC under range threshold. An ADC out-of-range error will be flagged
645  if the ADC output is less than the under range threshold.
646  Threshold = min_value + ADCUNDR�2^6
647  0000 = min value (disabled)
648  0001 = min_value + 64
649  0010 = min _value + 128
650  ...
651  1111: min _value + 960 */
652 #define ADAS1000_LOFFLTH_ADCUNDR (1ul << 16)
653 /* AC Leads off lower Threshold. Leads off will be detected if the DC
654  or AC output is = N * 2 * VREF/GAIN/2^16. 0 = 0V */
655 #define ADAS1000_LOFFLTH_LOFFLTH (1ul << 0)
656 
657 #define ADAS1000_LOFFLTH_ADCUNDR_MASK (0x0000000Ful << 16)
658 #define ADAS1000_LOFFLTH_LOFFLTH_MASK (0x0000FFFFul << 0)
659 
660 /******************************************************************************/
661 /* Pace Edge Threshold Register */
662 /******************************************************************************/
663 /* Pace edge trigger threshold */
664 #define ADAS1000_PACEEDGETH_PACE3EDGTH (1ul << 16)
665 /* 0 = PACEAMPTH/2 */
666 #define ADAS1000_PACEEDGETH_PACE2EDGTH (1ul << 8)
667 /* 1 = VREF/GAIN/2^16 */
668 #define ADAS1000_PACEEDGETH_PACE1EDGTH (1ul << 0)
669 /* N = N * VREF/GAIN/2^16 */
670 
671 #define ADAS1000_PACEEDGETH_PACE3EDGTH_MASK (0x000000FFul << 16)
672 #define ADAS1000_PACEEDGETH_PACE2EDGTH_MASK (0x000000FFul << 8)
673 #define ADAS1000_PACEEDGETH_PACE1EDGTH_MASK (0x000000FFul << 0)
674 
675 /******************************************************************************/
676 /* Pace Level Threshold Register */
677 /******************************************************************************/
678 /* Pace level threshold. This is a signed value. */
679 #define ADAS1000_PACELVLTH_PACE3LVLTH (1ul << 16)
680 /* -1 = 0xFFF = -VREF/GAIN/2^16 */
681 #define ADAS1000_PACELVLTH_PACE2LVLTH (1ul << 8)
682 /* 0 = 0x0000 = 0V */
683 #define ADAS1000_PACELVLTH_PACE1LVLTH (1ul << 0)
684 /* +1 = 0x001 = +VREF/GAIN/2^16 */
685 /* N = N * VREF/GAIN/2^16 */
686 
687 #define ADAS1000_PACELVLTH_PACE3LVLTH_MASK (0x000000FFul << 16)
688 #define ADAS1000_PACELVLTH_PACE2LVLTH_MASK (0x000000FFul << 8)
689 #define ADAS1000_PACELVLTH_PACE1LVLTH_MASK (0x000000FFul << 0)
690 
691 /***********************************************************************************/
692 /* LA or LEAD I, LL or LEAD II, RA or LEAD III, V1 or V1�, V2 or V2� Data Register */
693 /***********************************************************************************/
694 /* 0x11 : LA or LEAD I
695  0x12 : LL or LEAD II
696  0x13 : RA or LEAD II
697  0x14 : V1 or V1
698  0x15 : V2 or V2 */
699 #define ADAS1000_LADATA_ADDRESS (1ul << 24)
700 /* Channel Data Value. Data left justified (MSB) irrespective of data
701  rate. In electrode format, the value is an unsigned integer.
702  In Vector format, the value is a signed 2�s complement integer format.
703  Vector format had 2x range compared to electrode format since it can
704  swing from +VREF to -VREF, therefore the LSB size is double.
705  Electrode Format:
706  Min value (000...) = 0V
707  Max value (1111...) = VREF/GAIN
708  LSB = (VREF/GAIN)/2N
709  Lead/Vector Format
710  Min value (1000...) = -(VREF/GAIN)
711  Max value (0111...) = +VREF/GAIN
712  LSB = 2^(VREF/GAIN)/2N
713  Where N = # of data bits, 16 for 128kHz data rate or 24 for
714  2kHz/16kHz data rate. */
715 
716 #define ADAS1000_LADATA_ECG_DATA (1ul << 0)
717 #define ADAS1000_LADATA_ADDRESS_MASK (0x000000FFul << 24)
718 #define ADAS1000_LADATA_ECG_DATA_MASK (0x00FFFFFFul << 0)
719 
720 /******************************************************************************/
721 /* Read Pace Detection Data Register */
722 /******************************************************************************/
723 /* 0001 1010 = Pace Detection */
724 #define ADAS1000_PACEDATA_ADDRESS (1ul << 24)
725 /* Pace 3 detected. This bit will be set once a pace pulse is
726  detected. This bit is set on the trailing edge of the pace pulse.
727  0 = Pace pulse not detected in current frame
728  1 = Pace pulse detected in this frame */
729 #define ADAS1000_PACEDATA_PACE3_DETECTED (1ul << 23)
730 /* This is the log2(height) of the pace pulse
731  N: height = 2^N * VREF / GAIN / 2^16 */
732 #define ADAS1000_PACEDATA_PACE_CH3_HEIGHT (1ul << 16)
733 /* This is log2(Width)-1 of the pace pulse.
734  N: Width = 2^(N+1) / 128kHz */
735 #define ADAS1000_PACEDATA_PACE_CH3_WIDTH (1ul << 20)
736 /* Pace 2 detected. This bit will be set once a pace pulse is
737  detected. This bit is set on the trailing edge of the pace pulse.
738  0 = Pace pulse not detected in current frame
739  1 = Pace pulse detected in this frame*/
740 #define ADAS1000_PACEDATA_PACE2_DETECTED (1ul << 15)
741 /* This is log2(Width)-1 of the pace pulse.
742  N: Width = 2^(N+1) / 128kHz */
743 #define ADAS1000_PACEDATA_PACE_CH2_WIDTH (1ul << 12)
744 /* This is the log2(height) of the pace pulse
745  N: height = 2^N * VREF / GAIN / 2^16 */
746 #define ADAS1000_PACEDATA_PACE_CH2_HEIGHT (1ul << 8)
747 /* Pace 1 detected. This bit will be set once a pace pulse is
748  detected. This bit is set on the trailing edge of the pace pulse.
749  0 = Pace pulse not detected in current frame
750  1 = Pace pulse detected in this frame */
751 #define ADAS1000_PACEDATA_PACE1_DETECTED (1ul << 7)
752 /* "This is log2(Width)-1 of the pace pulse.
753  N: Width = 2^(N+1) / 128kHz */
754 #define ADAS1000_PACEDATA_PACE_CH1_WIDTH (1ul << 4)
755 /* This is the log2(height) of the pace pulse
756  N: height = 2^N * VREF / GAIN / 2^16 */
757 #define ADAS1000_PACEDATA_CH1_HEIGHT (1ul << 0)
758 
759 #define ADAS1000_PACEDATA_ADDRESS_MASK (0x000000FFul << 24)
760 #define ADAS1000_PACEDATA_PACE_CH3_WIDTH_MASK (0x00000007ul << 20)
761 #define ADAS1000_PACEDATA_PACE_CH3_HEIGHT_MASK (0x0000000Ful << 16)
762 #define ADAS1000_PACEDATA_PACE_CH2_WIDTH_MASK (0x00000007ul << 12)
763 #define ADAS1000_PACEDATA_PACE_CH2_HEIGHT_MASK (0x0000000Ful << 8)
764 #define ADAS1000_PACEDATA_PACE_CH1_WIDTH_MASK (0x00000007ul << 4)
765 #define ADAS1000_PACEDATA_PACE_CH1_HEIGHT_MASK (0x0000000Ful << 0)
766 
767 /******************************************************************************/
768 /* Read Respiration Data Magnitude Register */
769 /******************************************************************************/
770 /* 0001 1011 = Respiration Magnitude */
771 #define ADAS1000_RESPMAG_ADDRESS (1ul << 24)
772 /* Magnitude of respiration signal. This is an unsigned value. */
773 #define ADAS1000_RESPMAG_MAGNITUDE (1ul << 0)
774 
775 #define ADAS1000_RESPMAG_ADDRESS_MASK (0x000000FFul << 24)
776 #define ADAS1000_RESPMAG_MAGNITUDE_MASK (0x00FFFFFFul << 0)
777 
778 /******************************************************************************/
779 /* Read Respiration Data Phase Register */
780 /******************************************************************************/
781 /* 0001 1100 = Respiration Phase */
782 #define ADAS1000_RESPPH_ADDRESS (1ul << 24)
783 /* Phase of respiration signal. Can be interpreted as either signed or
784  unsigned value. If unsigned, the range is from 0 to 2pi. If as a
785  signed value, the range is from �pi to +pi.
786  0x000000 = 0
787  0x000001 = 2pi / 2^24
788  0x400000 = pi/2
789  0x800000 = +pi = -pi
790  0xC00000 = +3pi/2 = -pi/2
791  0xFFFFFF = +2pi(1 - 2^(-24)) = -2p / 2^24 */
792 #define ADAS1000_RESPPH_PHASE (1ul << 0)
793 
794 #define ADAS1000_RESPPH_ADDRESS_MASK (0x000000FFul << 24)
795 #define ADAS1000_RESPPH_PHASE_MASK (0x00FFFFFFul << 0)
796 
797 /******************************************************************************/
798 /* Leads Off Status Register */
799 /******************************************************************************/
800 /* Address bits define the word data 0001 1101 = Leads Off */
801 #define ADAS1000_LOFF_ADDRESS (1ul << 24)
802 /* Electrode Connection Status. If either DC or AC leads off
803  If both DC and AC leads off are enabled, these bits reflect
804  only the AC leads off status. DC leads off is available in
805  the DCLEADSOFF register. The common electrodes only have DC
806  leads off detection. An AC leads off signal can be injected
807  into the common electrode, but there is no ADC input to measure
808  its amplitude. If the common electrode is off, it will affect
809  the AC leads off amplitude of the other electrodes. These bits
810  accumulate in the frame buffer and are cleared when the frame
811  buffer is loaded into the SPI buffer.
812  0 = Electrode is connected
813  1 = Electrode is disconnected*/
814 #define ADAS1000_LOFF_RL_LEADS_OFF_STATUS (1ul << 23)
815 #define ADAS1000_LOFF_LA_LEADS_OFF_STATUS (1ul << 22)
816 #define ADAS1000_LOFF_LL_LEADS_OFF_STATUS (1ul << 21)
817 #define ADAS1000_LOFF_RA_LEADS_OFF_STATUS (1ul << 20)
818 #define ADAS1000_LOFF_V1_LEADS_OFF_STATUS (1ul << 19)
819 #define ADAS1000_LOFF_V2_LEADS_OFF_STATUS (1ul << 18)
820 #define ADAS1000_LOFF_CELO (1ul << 13)
821 /* ADC out of range error.
822  These status bits indicate the resulting ADC code is out of
823  range. These bits accumulate in the frame buffer and are
824  cleared when the frame buffer is loaded into the SPI buffer. */
825 #define ADAS1000_LOFF_LAADCOR (1ul << 12)
826 #define ADAS1000_LOFF_LLADCOR (1ul << 11)
827 #define ADAS1000_LOFF_RAADCOR (1ul << 10)
828 #define ADAS1000_LOFF_V1ADCOR (1ul << 9)
829 #define ADAS1000_LOFF_V2ADCOR (1ul << 8)
830 
831 #define ADAS1000_LOFF_ADDRESS_MASK (0x000000FFul << 24)
832 
833 /******************************************************************************/
834 /* DC Leads off Register */
835 /******************************************************************************/
836 /* Address bits define the word data 0001 1110 = DC Leads Off */
837 #define ADAS1000_DCLEADSOFF_ADDRESS (1ul << 24)
838 /* The DC leads off detection is comparator based and compares
839  to a fixed level. Per electrode bits flag if the DC leads off
840  comparator threshold level has been exceeded.
841  0 = electrode < overrange threshold, 2.4 V
842  1 = electrode > overrange threshold, 2.4 V */
843 #define ADAS1000_DCLEADSOFF_RL_INPUT_OVERRANGE (1ul << 23)
844 #define ADAS1000_DCLEADSOFF_LA_INPUT_OVERRANGE (1ul << 22)
845 #define ADAS1000_DCLEADSOFF_LL_INPUT_OVERRANGE (1ul << 21)
846 #define ADAS1000_DCLEADSOFF_RA_INPUT_OVERRANGE (1ul << 20)
847 #define ADAS1000_DCLEADSOFF_CE_INPUT_OVERRANGE (1ul << 13)
848 
849 /* The DC leads off detection is comparator based and compares
850  to a fixed level. Per electrode bits flag if the DC leads off
851  comparator threshold level has been exceeded.
852  0 = electrode > underrange threshold, 0.2 V
853  1 = electrode < underrange threshold, 0.2 V */
854 #define ADAS1000_DCLEADSOFF_RL_INPUT_UNDERRANGE (1ul << 12)
855 #define ADAS1000_DCLEADSOFF_LA_INPUT_UNDERRANGE (1ul << 11)
856 #define ADAS1000_DCLEADSOFF_LL_INPUT_UNDERRANGE (1ul << 10)
857 #define ADAS1000_DCLEADSOFF_RA_INPUT_UNDERRANGE (1ul << 9)
858 #define ADAS1000_DCLEADSOFF_CE_INPUT_UNDERRANGE (1ul << 2)
859 
860 #define ADAS1000_DCLEADSOFF_ADDRESS_MASK (0x000000FFul << 24)
861 
862 /******************************************************************************/
863 /* Extended Switch for Respiration Inputs Register */
864 /******************************************************************************/
865 /* External Respiration electrode input switch to channel
866  electrode input.
867  0 = switch open
868  1 = switch closed */
869 #define ADAS1000_EXTENDSW_EXTRESP_RA_LA (1ul << 23)
870 #define ADAS1000_EXTENDSW_EXTRESP_RA_LL (1ul << 22)
871 #define ADAS1000_EXTENDSW_EXTRESP_RA_RA (1ul << 21)
872 #define ADAS1000_EXTENDSW_EXTRESP_RA_V1 (1ul << 20)
873 #define ADAS1000_EXTENDSW_EXTRESP_RA_V2 (1ul << 19)
874 #define ADAS1000_EXTENDSW_EXTRESP_LL_LA (1ul << 18)
875 #define ADAS1000_EXTENDSW_EXTRESP_LL_LL (1ul << 17)
876 #define ADAS1000_EXTENDSW_EXTRESP_LL_RA (1ul << 16)
877 #define ADAS1000_EXTENDSW_EXTRESP_LL_V1 (1ul << 15)
878 #define ADAS1000_EXTENDSW_EXTRESP_LL_V2 (1ul << 14)
879 #define ADAS1000_EXTENDSW_EXTRESP_LA_LA (1ul << 13)
880 #define ADAS1000_EXTENDSW_EXTRESP_LA_LL (1ul << 12)
881 #define ADAS1000_EXTENDSW_EXTRESP_LA_RA (1ul << 11)
882 #define ADAS1000_EXTENDSW_EXTRESP_LA_V1 (1ul << 10)
883 #define ADAS1000_EXTENDSW_EXTRESP_LA_V2 (1ul << 9)
884 
885 /* V1 and V2 electrodes may be used for measurement purposes
886  other than ECG. To achieve this, they need to be disconnected
887  from the patient VCM voltage provided from the internal common
888  mode buffer and instead connected to the internal VCM_REF level
889  of 1.3V. Set FREE_Vx bits high to connect negative input of V1
890  channel will be tied to internal VCM_REF level. This allows user
891  to make alternative measurements on V1 channel relative to the
892  VCM_REF level. If using Digital lead mode, uses these bits in
893  conjunction with NO_MATH_Vx bits [6:5]. */
894 #define ADAS1000_EXTENDSW_FREE_V1 (1ul << 8)
895 #define ADAS1000_EXTENDSW_FREE_V2 (1ul << 7)
896 /* In Digital Lead Mode, the digital core calculates the math on V1
897  and V2 with respect to WCT (LA+LL+RA)/3 providing V1 and V2.
898  Where V1 or V2 are used for measurement of something other than
899  ECG, then the math calculation needs to be disabled. These bits
900  are most likely used in conjunction with bits FREE_Vx [8:7].
901  Set NOMATH_Vx bits high to disable the math calculation in V1
902  and V2 respectively. */
903 #define ADAS1000_EXTENDSW_NOMATH_V1 (1ul << 6)
904 #define ADAS1000_EXTENDSW_NOMATH_V2 (1ul << 5)
905 
906 /******************************************************************************/
907 /* User gain calibration LA, LL, RA, V1, V2 Register */
908 /******************************************************************************/
909 /* 0x21 : CAL LA */
910 /* 0x22 : CAL LL */
911 /* 0x23 : CAL RA */
912 /* 0x24 : CAL V1 */
913 /* 0x25 : CAL V2 */
914 #define ADAS1000_CAL_ADDRESS (1ul << 24)
915 /* User can choose between:
916  0 = default calibration values
917  1 = user calibration values */
918 #define ADAS1000_CAL_USRCAL (1ul << 23)
919 /* Gain Calibration value.
920  Result = data * (1 + GAIN * 2^(-17))
921  The value read from this register is the current gain calibration value.
922  If the USRCAL bit is clear, this register returns the default value for
923  the current gain setting.
924  0x7FF (+2047) = *1.00000011111111111b
925  0x001 (+1) = *1.00000000000000001b
926  0x000 (0) = *1.00000000000000000b
927  0xFFF (-1) = *0.11111111111111111b
928  0x800 (-2048) = *0.11111100000000000b */
929 #define ADAS1000_CAL_CALVALUE (1ul << 0)
930 
931 #define ADAS1000_CAL_ADDRESS_MASK (0x000000FFul << 24)
932 #define ADAS1000_CAL_CALVALUE_MASK (0x00000FFFul << 0)
933 
934 /******************************************************************************/
935 /* Leads off Amplitude for LA, LL, RA, V1, V2 Register */
936 /******************************************************************************/
937 /* 0x31 : LA AC Leads off Magnitude
938  0x32 : LL AC Leads off Magnitude
939  0x33 : RA AC Leads off Magnitude
940  0x34 : V1 AC Leads off Magnitude
941  0x35 : V2 AC Leads off Magnitude */
942 #define ADAS1000_LOAM_ADDRESS (1ul << 24)
943 /* Measured Amplitude.
944  When AC leads off is selected, the data is the average of the rectified
945  2kHz bandpass filter with an update rate of 8Hz and cutoff frequency at
946  2Hz. The output is the amplitude of the 2kHz signal scaled by 2/pi
947  approximately = 0.6 (average of rectified sine wave). To convert to RMS,
948  scale the output by pi / (2*sqrt(2)).
949  Leads off (unsigned):
950  Min 0x0000 = 0V
951  LSB 0x0001= VREF / GAIN / 2^16
952  Max 0xFFFF = VREF / GAIN */
953 #define ADAS1000_LOAM_LOFFAM (1ul << 0)
954 
955 #define ADAS1000_LOAM_ADDRESS_MASK (0x000000FFul << 24)
956 #define ADAS1000_LOAM_LOFFAM_MASK (0x0000FFFFul << 0)
957 
958 /******************************************************************************/
959 /* Pace1, Pace2, Pace3 Width & Amplitude2 Register */
960 /******************************************************************************/
961 /* 0x3A : PACE1DATA
962  0x3B : PACE2DATA
963  0x3C : PACE3DATA */
964 #define ADAS1000_PACE_DATA_ADDRESS (1ul << 24)
965 /* Measured pace height in signed 2�s complement value
966  0 = 0
967  1 = VREF / GAIN / 2^16
968  N = N * VREF / GAIN / 2^16 */
969 #define ADAS1000_PACE_DATA_HEIGHT (1ul << 8)
970 /* Measured pace width in 128kHz samples
971  N: N / 128kHz = width
972  12: 12 / 128kHz = 93us
973  255: 255 / 128kHz = 2.0ms */
974 #define ADAS1000_PACE_DATA_WIDTH (1ul << 0)
975 
976 #define ADAS1000_PACE_DATA_ADDRESS_MASK (0x000000FFul << 24)
977 #define ADAS1000_PACE_DATA_HEIGHT_MASK (0x0000FFFFul << 8)
978 #define ADAS1000_PACE_DATA_WIDTH_MASK (0x000000FFul << 0)
979 
980 /******************************************************************************/
981 /* Frame Header - Read Data Frames Register */
982 /******************************************************************************/
983 /* Header marker, set to 1 for the header */
984 #define ADAS1000_FRAMES_MARKER (1ul << 31)
985 /* Ready bit indicates if ECG frame data is calculated and
986  ready for reading.
987  0 = Ready, data frame follows
988  1 = Busy */
989 #define ADAS1000_FRAMES_READY_BIT (1ul << 30)
990 /* Overflow bits indicate that since the last frame read,
991  a number of frames have been missed. This field saturates
992  at the maximum count. The data in the frame including
993  this header word is valid but old if the overflow bits
994  are > 0. When using Skip mode (FRMCTL register (0x0A)[3:2]),
995  the Overflow bit acts as a flag, where a non-zero value
996  indicates an overflow.
997  00 = 0 missed
998  01 = 1 frame missed
999  10 = 2 frames missed
1000  11 = 3 or more frames missed */
1001 #define ADAS1000_FRAMES_OVERFLOW (1ul << 28)
1002 /* Internal device error detected.
1003  0 = normal operation
1004  1 = error condition */
1005 #define ADAS1000_FRAMES_FAULT (1ul << 27)
1006 /* PACE 3 Indicates Pacing Artifact was qualified at most
1007  recent point.
1008  0 = No Pacing Artifact
1009  1 = Pacing Artifact Present */
1010 #define ADAS1000_FRAMES_PACE3_DETECTED (1ul << 26)
1011 /* PACE 2 Indicates Pacing Artifact was qualified at most
1012  recent point.
1013  0 = No Pacing Artifact
1014  1 = Pacing Artifact Present */
1015 #define ADAS1000_FRAMES_PACE2_DETECTED (1ul << 25)
1016 /* PACE 1 Indicates Pacing Artifact was qualified at most
1017  recent point.
1018  0 = No Pacing Artifact
1019  1 = Pacing Artifact Present */
1020 #define ADAS1000_FRAMES_PACE1_DETECTED (1ul << 24)
1021 /* 0 = no new respiration data
1022  1 = respiration data updated */
1023 #define ADAS1000_FRAMES_RESPIRATION (1ul << 23)
1024 /* If both DC & AC leads off are enabled, this bit is the
1025  OR of all the AC leads off detect flags. If only AC or
1026  DC leads off is enabled (but not both, this bit reflects
1027  the OR of all DC & AC leads off flags.
1028  0 = all leads connected
1029  1 = one or more leads off detected */
1030 #define ADAS1000_FRAMES_LEADS_OFF_DETECTED (1ul << 22)
1031 /* 0 = all leads connected
1032  1 = one or more leads off detected */
1033 #define ADAS1000_FRAMES_DC_LEADS_OFF_DETECTED (1ul << 21)
1034 /* 0 = ADC within range
1035  1 = ADC out of range */
1036 #define ADAS1000_FRAMES_ADC_OUT_OF_RANGE (1ul << 20)
1037 /******************************************************************************/
1038 /* Frame CRC Register */
1039 /******************************************************************************/
1040 /* Cyclic Redundancy Check */
1041 #define ADAS1000_CRC_MASK (0x00FFFFFF << 0)
1042 
1043 /******************************************************************************/
1044 /* ADAS1000 data rates, word sizes and frame size */
1045 /******************************************************************************/
1046 #define ADAS1000_31_25HZ_FRAME_RATE 3125
1047 #define ADAS1000_2KHZ_FRAME_RATE 2000
1048 #define ADAS1000_16KHZ_FRAME_RATE 16000
1049 #define ADAS1000_128KHZ_FRAME_RATE 128000
1050 
1051 #define ADAS1000_31_25HZ_WORD_SIZE 32
1052 #define ADAS1000_2KHZ_WORD_SIZE 32
1053 #define ADAS1000_16KHZ_WORD_SIZE 32
1054 #define ADAS1000_128KHZ_WORD_SIZE 16
1055 
1056 #define ADAS1000_31_25HZ_FRAME_SIZE 12
1057 #define ADAS1000_2KHZ_FRAME_SIZE 12
1058 #define ADAS1000_16KHZ_FRAME_SIZE 12
1059 #define ADAS1000_128KHZ_FRAME_SIZE 15
1060 
1061 /******************************************************************************/
1062 /* ADAS1000 CRC constants */
1063 /******************************************************************************/
1064 #define CRC_POLY_2KHZ_16KHZ 0x005D6DCBul
1065 #define CRC_CHECK_CONST_2KHZ_16KHZ 0x0015A0BAul
1066 
1067 #define CRC_POLY_128KHZ 0x00001021ul
1068 #define CRC_CHECK_CONST_128KHz 0x00001D0Ful
1069 
1070 struct adas1000_dev {
1072  struct no_os_spi_desc *spi_desc;
1074  uint32_t frame_size;
1076  uint32_t frame_rate;
1078  uint32_t inactive_words_no;
1079 };
1080 
1081 struct adas1000_init_param {
1083  struct no_os_spi_init_param spi_init;
1085  uint32_t frame_rate;
1086 };
1087 
1088 struct read_param {
1090  bool start_read;
1093  bool stop_read;
1096  bool wait_for_ready;
1099  bool ready_repeat;
1100 };
1101 
1102 
1103 /******************************************************************************/
1104 /* Functions Prototypes */
1105 /******************************************************************************/
1107 int32_t adas1000_compute_spi_freq(struct adas1000_init_param *init_param,
1108  uint32_t *spi_freq);
1109 
1110 /* Initializes the communication with ADAS1000 and checks if the device is present.*/
1111 int32_t adas1000_init(struct adas1000_dev **device,
1112  const struct adas1000_init_param *init_param);
1113 
1114 /* Reads the value of a ADAS1000 register */
1115 int32_t adas1000_read(struct adas1000_dev *device, uint8_t reg_addr,
1116  uint32_t *reg_data);
1117 
1118 /* Writes a value into a ADAS1000 register */
1119 int32_t adas1000_write(struct adas1000_dev *device, uint8_t reg_addr,
1120  uint32_t reg_data);
1121 
1122 /* Performs a software reset of the ADAS1000 */
1123 int32_t adas1000_soft_reset(struct adas1000_dev *device);
1124 
1125 /* Compute frame size. */
1126 int32_t adas1000_compute_frame_size(struct adas1000_dev *device);
1127 
1128 /* Selects which words are not included in a data frame */
1129 int32_t adas1000_set_inactive_framewords(struct adas1000_dev *device,
1130  uint32_t words_mask);
1131 
1132 /* Sets the frame rate */
1133 int32_t adas1000_set_frame_rate(struct adas1000_dev *device, uint32_t rate);
1134 
1135 /* Reads the specified number of frames */
1136 int32_t adas1000_read_data(struct adas1000_dev *device, uint8_t *data_buff,
1137  uint32_t frame_cnt, struct read_param *read_data_param);
1138 
1139 /* Computes the CRC for a frame */
1140 uint32_t adas1000_compute_frame_crc(struct adas1000_dev * device,
1141  uint8_t *buff);
1142 
1143 #endif /* _ADAS1000_H_ */
adas1000_init
int32_t adas1000_init(struct adas1000_dev **device, const struct adas1000_init_param *init_param)
Initializes the SPI communication with ADAS1000. The ADAS1000 is configured with the specified frame ...
Definition: adas1000.c:94
ADAS1000_31_25HZ_FRAME_SIZE
#define ADAS1000_31_25HZ_FRAME_SIZE
Definition: adas1000.h:1056
adas1000_read_data
int32_t adas1000_read_data(struct adas1000_dev *device, uint8_t *data_buff, uint32_t frame_cnt, struct read_param *read_data_param)
Reads the specified number of frames.
Definition: adas1000.c:325
adas1000_soft_reset
int32_t adas1000_soft_reset(struct adas1000_dev *device)
Software reset of the device.
Definition: adas1000.c:189
adas1000_dev::inactive_words_no
uint32_t inactive_words_no
Definition: adas1000.h:1078
ADAS1000_ALL_CH_MASK
#define ADAS1000_ALL_CH_MASK
Definition: adas1000.h:53
no_os_alloc.h
adas1000_write
int32_t adas1000_write(struct adas1000_dev *device, uint8_t reg_addr, uint32_t reg_data)
Write device register.
Definition: adas1000.c:170
ADAS1000_128KHZ_WORD_SIZE
#define ADAS1000_128KHZ_WORD_SIZE
Definition: adas1000.h:1054
no_os_spi_write_and_read
int32_t no_os_spi_write_and_read(struct no_os_spi_desc *desc, uint8_t *data, uint16_t bytes_number)
Write and read data to/from SPI.
Definition: no_os_spi.c:159
no_os_spi.h
Header file of SPI Interface.
CRC_POLY_128KHZ
#define CRC_POLY_128KHZ
Definition: adas1000.h:1067
ADAS1000_2KHZ_FRAME_RATE
#define ADAS1000_2KHZ_FRAME_RATE
Definition: adas1000.h:1047
ADAS1000_31_25HZ_FRAME_RATE
#define ADAS1000_31_25HZ_FRAME_RATE
Definition: adas1000.h:1046
adas1000_read_data
int32_t adas1000_read_data(struct adas1000_dev *device, uint8_t *data_buff, uint32_t frame_cnt, struct read_param *read_data_param)
Reads the specified number of frames.
Definition: adas1000.c:325
read_param::start_read
bool start_read
Definition: adas1000.h:1090
ADAS1000_NOP
#define ADAS1000_NOP
Definition: adas1000.h:56
no_os_crc24_populate_msb
void no_os_crc24_populate_msb(uint32_t *table, const uint32_t polynomial)
adas1000_init_param
Definition: adas1000.h:1081
ADAS1000_WD_CNT_MASK
#define ADAS1000_WD_CNT_MASK
Definition: adas1000.h:54
adas1000_init_param::frame_rate
uint32_t frame_rate
Definition: adas1000.h:1085
ADAS1000_128KHZ_FRAME_SIZE
#define ADAS1000_128KHZ_FRAME_SIZE
Definition: adas1000.h:1059
device
Definition: ad9361_util.h:69
ADAS1000_FRMCTL_FRMRATE_2KHZ
#define ADAS1000_FRMCTL_FRMRATE_2KHZ
Definition: adas1000.h:580
no_os_calloc
void * no_os_calloc(size_t nitems, size_t size)
Allocate memory and return a pointer to it, set memory to 0.
Definition: chibios_alloc.c:54
adas1000_init_param::spi_init
struct no_os_spi_init_param spi_init
Definition: adas1000.h:1083
ADAS1000_FRMCTL_FRMRATE_31_25HZ
#define ADAS1000_FRMCTL_FRMRATE_31_25HZ
Definition: adas1000.h:586
ADAS1000_FRMCTL_FRMRATE_MASK
#define ADAS1000_FRMCTL_FRMRATE_MASK
Definition: adas1000.h:600
ADAS1000_16KHZ_WORD_SIZE
#define ADAS1000_16KHZ_WORD_SIZE
Definition: adas1000.h:1053
ADAS1000_16KHZ_FRAME_SIZE
#define ADAS1000_16KHZ_FRAME_SIZE
Definition: adas1000.h:1058
ADAS1000_ECGCTL_SWRST
#define ADAS1000_ECGCTL_SWRST
Definition: adas1000.h:155
adas1000_dev::frame_size
uint32_t frame_size
Definition: adas1000.h:1074
no_os_error.h
Error codes definition.
adas1000_compute_frame_crc
uint32_t adas1000_compute_frame_crc(struct adas1000_dev *device, uint8_t *buff)
Computes the CRC for a frame.
Definition: adas1000.c:402
ADAS1000_FRMCTL_WORD_MASK
#define ADAS1000_FRMCTL_WORD_MASK
Definition: adas1000.h:588
adas1000_compute_frame_size
int32_t adas1000_compute_frame_size(struct adas1000_dev *device)
Compute frame size.
Definition: adas1000.c:206
ADAS1000_16KHZ_FRAME_RATE
#define ADAS1000_16KHZ_FRAME_RATE
Definition: adas1000.h:1048
read_param::ready_repeat
bool ready_repeat
Definition: adas1000.h:1099
adas1000_set_inactive_framewords
int32_t adas1000_set_inactive_framewords(struct adas1000_dev *device, uint32_t words_mask)
Selects which words are not included in a data frame.
Definition: adas1000.c:239
adas1000_compute_frame_size
int32_t adas1000_compute_frame_size(struct adas1000_dev *device)
Compute frame size.
Definition: adas1000.c:206
ADAS1000_ECGCTL
#define ADAS1000_ECGCTL
Definition: adas1000.h:57
read_param::stop_read
bool stop_read
Definition: adas1000.h:1093
ADAS1000_2KHZ_FRAME_SIZE
#define ADAS1000_2KHZ_FRAME_SIZE
Definition: adas1000.h:1057
ADAS1000_FRMCTL
#define ADAS1000_FRMCTL
Definition: adas1000.h:66
adas1000_set_frame_rate
int32_t adas1000_set_frame_rate(struct adas1000_dev *device, uint32_t rate)
Sets the frame rate.
Definition: adas1000.c:277
adas1000_read
int32_t adas1000_read(struct adas1000_dev *device, uint8_t reg_addr, uint32_t *reg_data)
Read device register.
Definition: adas1000.c:141
adas1000_set_frame_rate
int32_t adas1000_set_frame_rate(struct adas1000_dev *device, uint32_t rate)
Sets the frame rate.
Definition: adas1000.c:277
read_param::wait_for_ready
bool wait_for_ready
Definition: adas1000.h:1096
adas1000_init
int32_t adas1000_init(struct adas1000_dev **device, const struct adas1000_init_param *init_param)
Initializes the SPI communication with ADAS1000. The ADAS1000 is configured with the specified frame ...
Definition: adas1000.c:94
no_os_spi_desc
Structure holding SPI descriptor.
Definition: no_os_spi.h:192
adas1000_write
int32_t adas1000_write(struct adas1000_dev *device, uint8_t reg_addr, uint32_t reg_data)
Write device register.
Definition: adas1000.c:170
no_os_crc.h
Generic header file for all CRC computation algorithms.
ADAS1000_128KHZ_FRAME_RATE
#define ADAS1000_128KHZ_FRAME_RATE
Definition: adas1000.h:1049
ADAS1000_FRAMES
#define ADAS1000_FRAMES
Definition: adas1000.h:96
adas1000_dev
Definition: adas1000.h:1070
adas1000_set_inactive_framewords
int32_t adas1000_set_inactive_framewords(struct adas1000_dev *device, uint32_t words_mask)
Selects which words are not included in a data frame.
Definition: adas1000.c:239
adas1000_read
int32_t adas1000_read(struct adas1000_dev *device, uint8_t reg_addr, uint32_t *reg_data)
Read device register.
Definition: adas1000.c:141
no_os_crc24
uint32_t no_os_crc24(const uint32_t *table, const uint8_t *pdata, size_t nbytes, uint32_t crc)
no_os_crc16
uint16_t no_os_crc16(const uint16_t *table, const uint8_t *pdata, size_t nbytes, uint16_t crc)
no_os_free
void no_os_free(void *ptr)
Deallocate memory previously allocated by a call to no_os_calloc or no_os_malloc.
Definition: chibios_alloc.c:69
adas1000_dev::spi_desc
struct no_os_spi_desc * spi_desc
Definition: adas1000.h:1072
ADAS1000_FRMCTL_FRMRATE_16KHZ
#define ADAS1000_FRMCTL_FRMRATE_16KHZ
Definition: adas1000.h:582
ADAS1000_COMM_WRITE
#define ADAS1000_COMM_WRITE
Definition: adas1000.h:51
read_param
Definition: adas1000.h:1088
init_param
struct ad7616_init_param init_param
Definition: ad7616_sdz.c:113
NO_OS_DECLARE_CRC16_TABLE
#define NO_OS_DECLARE_CRC16_TABLE(_table)
Definition: no_os_crc16.h:41
adas1000_compute_frame_crc
uint32_t adas1000_compute_frame_crc(struct adas1000_dev *device, uint8_t *buff)
Computes the CRC for a frame.
Definition: adas1000.c:402
ADAS1000_31_25HZ_WORD_SIZE
#define ADAS1000_31_25HZ_WORD_SIZE
Definition: adas1000.h:1051
NO_OS_DECLARE_CRC24_TABLE
#define NO_OS_DECLARE_CRC24_TABLE(_table)
Definition: no_os_crc24.h:41
adas1000_compute_spi_freq
int32_t adas1000_compute_spi_freq(struct adas1000_init_param *init_param, uint32_t *spi_freq)
Preliminary function which computes the spi frequency based on the frame rate value passed input para...
Definition: adas1000.c:56
ADAS1000_RDY_MASK
#define ADAS1000_RDY_MASK
Definition: adas1000.h:52
no_os_spi_init
int32_t no_os_spi_init(struct no_os_spi_desc **desc, const struct no_os_spi_init_param *param)
Initialize the SPI communication peripheral.
Definition: no_os_spi.c:52
no_os_crc16_populate_msb
void no_os_crc16_populate_msb(uint16_t *table, const uint16_t polynomial)
adas1000.h
Header file of ADAS1000 Driver.
ADAS1000_2KHZ_WORD_SIZE
#define ADAS1000_2KHZ_WORD_SIZE
Definition: adas1000.h:1052
CRC_POLY_2KHZ_16KHZ
#define CRC_POLY_2KHZ_16KHZ
Definition: adas1000.h:1064
ADAS1000_FRMCTL_FRMRATE_128KHZ
#define ADAS1000_FRMCTL_FRMRATE_128KHZ
Definition: adas1000.h:584
adas1000_dev::frame_rate
uint32_t frame_rate
Definition: adas1000.h:1076
adas1000_compute_spi_freq
int32_t adas1000_compute_spi_freq(struct adas1000_init_param *init_param, uint32_t *spi_freq)
Preliminary function which computes the spi frequency based on the frame rate value passed input para...
Definition: adas1000.c:56
adas1000_soft_reset
int32_t adas1000_soft_reset(struct adas1000_dev *device)
Software reset of the device.
Definition: adas1000.c:189
no_os_spi_init_param
Structure holding the parameters for SPI initialization.
Definition: no_os_spi.h:140
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