Header file of ADE7978 Driver. More...

#include <stdbool.h>
#include <stdint.h>
#include <string.h>
#include "no_os_util.h"
#include "no_os_spi.h"
#include "no_os_gpio.h"
#include "no_os_print_log.h"

Include dependency graph for ade7978.h:

Classes
struct	ade7978_init_param
	ADE7978 Device initialization parameters. More...

struct	ade7978_dev
	ADE7978 Device structure. More...

Macros
#define	ADE7978_SPI_READ_CMD 0x01

#define	ADE7978_SPI_WRITE_CMD 0x00

#define	ENABLE 0x0001

#define	DISABLE 0x0000

#define	ADE7978_REG_AIGAIN 0x4380

#define	ADE7978_REG_AVGAIN 0x4381

#define	ADE7978_REG_AV2GAIN 0x4382

#define	ADE7978_REG_BIGAIN 0x4383

#define	ADE7978_REG_BVGAIN 0x4384

#define	ADE7978_REG_BV2GAIN 0x4385

#define	ADE7978_REG_CIGAIN 0x4386

#define	ADE7978_REG_CVGAIN 0x4387

#define	ADE7978_REG_CV2GAIN 0x4388

#define	ADE7978_REG_NIGAIN 0x4389

#define	ADE7978_REG_NVGAIN 0x438A

#define	ADE7978_REG_NV2GAIN 0x438B

#define	ADE7978_REG_AIRMSOS 0x438C

#define	ADE7978_REG_AVRMSOS 0x438D

#define	ADE7978_REG_AV2RMSOS 0x438E

#define	ADE7978_REG_BIRMSOS 0x438F

#define	ADE7978_REG_BVRMSOS 0x4390

#define	ADE7978_REG_BV2RMSOS 0x4391

#define	ADE7978_REG_CIRMSOS 0x4392

#define	ADE7978_REG_CVRMSOS 0x4393

#define	ADE7978_REG_CV2RMSOS 0x4394

#define	ADE7978_REG_NIRMSOS 0x4395

#define	ADE7978_REG_NVRMSOS 0x4396

#define	ADE7978_REG_NV2RMSOS 0x4397

#define	ADE7978_REG_ISUMLVL 0x4398

#define	ADE7978_REG_APGAIN 0x4399

#define	ADE7978_REG_BPGAIN 0x439A

#define	ADE7978_REG_CPGAIN 0x439B

#define	ADE7978_REG_AWATTOS 0x439C

#define	ADE7978_REG_BWATTOS 0x439D

#define	ADE7978_REG_CWATTOS 0x439E

#define	ADE7978_REG_AVAROS 0x439F

#define	ADE7978_REG_BVAROS 0x43A0

#define	ADE7978_REG_CVAROS 0x43A1

#define	ADE7978_REG_AFWATTOS 0x43A3

#define	ADE7978_REG_BFWATTOS 0x43A4

#define	ADE7978_REG_CFWATTOS 0x43A5

#define	ADE7978_REG_AFVAROS 0x43A6

#define	ADE7978_REG_BFVAROS 0x43A7

#define	ADE7978_REG_CFVAROS 0x43A8

#define	ADE7978_REG_AFIRMSOS 0x43A9

#define	ADE7978_REG_BFIRMSOS 0x43AA

#define	ADE7978_REG_CFIRMSOS 0x43AB

#define	ADE7978_REG_AFVRMSOS 0x43AC

#define	ADE7978_REG_BFVRMSOS 0x43AD

#define	ADE7978_REG_CFVRMSOS 0x43AE

#define	ADE7978_REG_TEMPCO 0x43AF

#define	ADE7978_REG_ATEMP0 0x43B0

#define	ADE7978_REG_BTEMP0 0x43B1

#define	ADE7978_REG_CTEMP0 0x43B2

#define	ADE7978_REG_NTEMPO 0x43B3

#define	ADE7978_REG_ATGAIN 0x43B4

#define	ADE7978_REG_BTGAIN 0x43B5

#define	ADE7978_REG_CTGAIN 0x43B6

#define	ADE7978_REG_NTGAIN 0x43B7

#define	ADE7978_REG_AIRMS 0x43C0

#define	ADE7978_REG_AVRMS 0x43C1

#define	ADE7978_REG_AV2RMS 0x43C2

#define	ADE7978_REG_BIRMS 0x43C3

#define	ADE7978_REG_BVRMS 0x43C4

#define	ADE7978_REG_BV2RMS 0x43C5

#define	ADE7978_REG_CIRMS 0x43C6

#define	ADE7978_REG_CVRMS 0x43C7

#define	ADE7978_REG_CV2RMS 0x43C8

#define	ADE7978_REG_NIRMS 0X43C9

#define	ADE7978_REG_ISUM 0X43CA

#define	ADE7978_REG_ATEMP 0X43CB

#define	ADE7978_REG_BTEMP 0X43CC

#define	ADE7978_REG_CTEMP 0X43CD

#define	ADE7978_REG_NTEMP 0X43CE

#define	ADE7978_REG_RUN 0xE228

#define	ADE7978_REG_AWATTHR 0xE400

#define	ADE7978_REG_BWATTHR 0xE401

#define	ADE7978_REG_CWATTHR 0xE402

#define	ADE7978_REG_AFWATTHR 0xE403

#define	ADE7978_REG_BFWATTHR 0xE404

#define	ADE7978_REG_CFWATTHR 0xE405

#define	ADE7978_REG_AVARHR 0xE406

#define	ADE7978_REG_BVARHR 0xE407

#define	ADE7978_REG_CVARHR 0xE408

#define	ADE7978_REG_AFVARHR 0xE409

#define	ADE7978_REG_BFVARHR 0xE40A

#define	ADE7978_REG_CFVARHR 0xE40B

#define	ADE7978_REG_AVAHR 0xE40C

#define	ADE7978_REG_BVAHR 0xE40D

#define	ADE7978_REG_CVAHR 0xE40E

#define	ADE7978_REG_IPEAK 0xE500

#define	ADE7978_REG_VPEAK 0xE501

#define	ADE7978_REG_STATUS0 0xE502

#define	ADE7978_REG_STATUS1 0xE503

#define	ADE7978_REG_OILVL 0xE507

#define	ADE7978_REG_OVLVL 0xE508

#define	ADE7978_REG_SAGLVL 0xE509

#define	ADE7978_REG_MASK0 0xE50A

#define	ADE7978_REG_MASK1 0xE50B

#define	ADE7978_REG_IAWV 0xE50C

#define	ADE7978_REG_IBWV 0xE50D

#define	ADE7978_REG_ICWV 0xE50E

#define	ADE7978_REG_INWV 0xE50F

#define	ADE7978_REG_VAWV 0xE510

#define	ADE7978_REG_VBWV 0xE511

#define	ADE7978_REG_VCWV 0xE512

#define	ADE7978_REG_VA2WV 0xE513

#define	ADE7978_REG_VB2WV 0xE514

#define	ADE7978_REG_VC2WV 0xE515

#define	ADE7978_REG_VNWV 0xE516

#define	ADE7978_REG_VN2WV 0xE517

#define	ADE7978_REG_AWATT 0xE518

#define	ADE7978_REG_BWATT 0xE519

#define	ADE7978_REG_CWATT 0xE51A

#define	ADE7978_REG_AVAR 0xE51B

#define	ADE7978_REG_BVAR 0xE51C

#define	ADE7978_REG_CVAR 0xE51D

#define	ADE7978_REG_AVA 0xE51E

#define	ADE7978_REG_BVA 0xE51F

#define	ADE7978_REG_CVA 0xE520

#define	ADE7978_REG_AVTHD 0xE521

#define	ADE7978_REG_AITHD 0xE522

#define	ADE7978_REG_BVTHD 0xE523

#define	ADE7978_REG_BITHD 0xE524

#define	ADE7978_REG_CVTHD 0xE525

#define	ADE7978_REG_CITHD 0xE526

#define	ADE7978_REG_NVRMS 0xE530

#define	ADE7978_REG_NV2RMS 0xE531

#define	ADE7978_REG_CHECKSUM 0xE532

#define	ADE7978_REG_VNOM 0xE533

#define	ADE7978_REG_AFIRMS 0xE537

#define	ADE7978_REG_AFVRMS 0xE538

#define	ADE7978_REG_BFIRMS 0xE539

#define	ADE7978_REG_BFVRMS 0xE53A

#define	ADE7978_REG_CFIRMS 0xE53B

#define	ADE7978_REG_CFVRMS 0xE53C

#define	ADE7978_REG_LAST_RWDATA32 0xE5FF

#define	ADE7978_REG_PHSTATUS 0xE600

#define	ADE7978_REG_ANGLE0 0xE601

#define	ADE7978_REG_ANGLE1 0xE602

#define	ADE7978_REG_ANGLE2 0xE603

#define	ADE7978_REG_PHNOLOAD 0xE608

#define	ADE7978_REG_LINECYC 0xE60C

#define	ADE7978_REG_ZXTOUT 0xE60D

#define	ADE7978_REG_COMPMODE 0xE60E

#define	ADE7978_REG_CFMODE 0xE610

#define	ADE7978_REG_CF1DEN 0xE611

#define	ADE7978_REG_CF2DEN 0xE612

#define	ADE7978_REG_CF3DEN 0xE613

#define	ADE7978_REG_APHCAL 0xE614

#define	ADE7978_REG_BPHCAL 0xE615

#define	ADE7978_REG_CPHCAL 0xE616

#define	ADE7978_REG_PHSIGN 0xE617

#define	ADE7978_REG_CONFIG 0xE618

#define	ADE7978_REG_MMODE 0xE700

#define	ADE7978_REG_ACCMODE 0xE701

#define	ADE7978_REG_LCYCMODE 0xE702

#define	ADE7978_REG_PEAKCYC 0xE703

#define	ADE7978_REG_SAGCYC 0xE704

#define	ADE7978_REG_CFCYC 0xE705

#define	ADE7978_REG_HSDC_CFG 0xE706

#define	ADE7978_REG_VERSION 0xE707

#define	ADE7978_REG_CONFIG3 0xE708

#define	ADE7978_REG_ATEMPOS 0xE709

#define	ADE7978_REG_BTEMPOS 0xE70A

#define	ADE7978_REG_CTEMPOS 0xE70B

#define	ADE7978_REG_NTEMPOS 0xE70C

#define	ADE7978_REG_LAST_RWDATA8 0xE7FD

#define	ADE7978_REG_APF 0xE902

#define	ADE7978_REG_BPF 0xE903

#define	ADE7978_REG_CPF 0xE904

#define	ADE7978_REG_APERIOD 0xE905

#define	ADE7978_REG_BPERIOD 0xE906

#define	ADE7978_REG_CPERIOD 0xE907

#define	ADE7978_REG_APNOLOAD 0xE908

#define	ADE7978_REG_VARNOLOAD 0xE909

#define	ADE7978_REG_VANOLOAD 0xE90A

#define	ADE7978_REG_LAST_ADD 0xE9FE

#define	ADE7978_REG_LAST_RWDATA16 0xE9FF

#define	ADE7978_REG_CONFIG2 0xEA00

#define	ADE7978_REG_LAST_OP 0xEA01

#define	ADE7978_REG_WTHR 0xEA02

#define	ADE7978_REG_VARTHR 0xEA03

#define	ADE7978_REG_VATHR 0xEA04

#define	ADE7978_IPPHASE2 NO_OS_BIT(26)

#define	ADE7978_IPPHASE1 NO_OS_BIT(25)

#define	ADE7978_IPPHASE0 NO_OS_BIT(24)

#define	ADE7978_IPEAKVAL NO_OS_GENMASK(23, 0)

#define	ADE7978_VPPHASE2 NO_OS_BIT(26)

#define	ADE7978_VPPHASE1 NO_OS_BIT(25)

#define	ADE7978_VPPHASE0 NO_OS_BIT(24)

#define	ADE7978_VPEAKVAL NO_OS_GENMASK(23, 0)

#define	ADE7978_STATUS0_REVPSUM3 NO_OS_BIT(18)

#define	ADE7978_STATUS0_DREADY NO_OS_BIT(17)

#define	ADE7978_STATUS0_CF3 NO_OS_BIT(16)

#define	ADE7978_STATUS0_CF2 NO_OS_BIT(15)

#define	ADE7978_STATUS0_CF1 NO_OS_BIT(14)

#define	ADE7978_STATUS0_REVPSUM2 NO_OS_BIT(13)

#define	ADE7978_STATUS0_REVRPC NO_OS_BIT(12)

#define	ADE7978_STATUS0_REVRPB NO_OS_BIT(11)

#define	ADE7978_STATUS0_REVRPA NO_OS_BIT(10)

#define	ADE7978_STATUS0_REVPSUM1 NO_OS_BIT(9)

#define	ADE7978_STATUS0_REVAPC NO_OS_BIT(8)

#define	ADE7978_STATUS0_REVAPB NO_OS_BIT(7)

#define	ADE7978_STATUS0_REVAPA NO_OS_BIT(6)

#define	ADE7978_STATUS0_LENERGY NO_OS_BIT(5)

#define	ADE7978_STATUS0_VAEHF NO_OS_BIT(4)

#define	ADE7978_STATUS0_FREHF NO_OS_BIT(3)

#define	ADE7978_STATUS0_FAEHF NO_OS_BIT(1)

#define	ADE7978_STATUS0_AEHF NO_OS_BIT(0)

#define	ADE7978_STATUS1_CRC NO_OS_BIT(25)

#define	ADE7978_STATUS1_PKV NO_OS_BIT(24)

#define	ADE7978_STATUS1_PKI NO_OS_BIT(23)

#define	ADE7978_STATUS1_MISMTCH NO_OS_BIT(20)

#define	ADE7978_STATUS1_SEQERR NO_OS_BIT(19)

#define	ADE7978_STATUS1_OV NO_OS_BIT(18)

#define	ADE7978_STATUS1_OI NO_OS_BIT(17)

#define	ADE7978_STATUS1_SAG NO_OS_BIT(16)

#define	ADE7978_STATUS1_RSTDONE NO_OS_BIT(15)

#define	ADE7978_STATUS1_ZXIC NO_OS_BIT(14)

#define	ADE7978_STATUS1_ZXIB NO_OS_BIT(13)

#define	ADE7978_STATUS1_ZXIA NO_OS_BIT(12)

#define	ADE7978_STATUS1_ZXVC NO_OS_BIT(11)

#define	ADE7978_STATUS1_ZXVB NO_OS_BIT(10)

#define	ADE7978_STATUS1_ZXVA NO_OS_BIT(9)

#define	ADE7978_STATUS1_ZXTOIC NO_OS_BIT(8)

#define	ADE7978_STATUS1_ZXTOIB NO_OS_BIT(7)

#define	ADE7978_STATUS1_ZXTOIA NO_OS_BIT(6)

#define	ADE7978_STATUS1_ZXTOVC NO_OS_BIT(5)

#define	ADE7978_STATUS1_ZXTOVB NO_OS_BIT(4)

#define	ADE7978_STATUS1_ZXTOVA NO_OS_BIT(3)

#define	ADE7978_STATUS1_VANLOAD NO_OS_BIT(2)

#define	ADE7978_STATUS1_FNLOAD NO_OS_BIT(1)

#define	ADE7978_STATUS1_NLOAD NO_OS_BIT(0)

#define	ADE7978_MASK0_HREADY NO_OS_BIT(19)

#define	ADE7978_MASK0_REVPSUM3 NO_OS_BIT(18)

#define	ADE7978_MASK0_DREADY NO_OS_BIT(17)

#define	ADE7978_MASK0_CF3 NO_OS_BIT(16)

#define	ADE7978_MASK0_CF2 NO_OS_BIT(15)

#define	ADE7978_MASK0_CF1 NO_OS_BIT(14)

#define	ADE7978_MASK0_REVPSUM2 NO_OS_BIT(13)

#define	ADE7978_MASK0_REVFRPC NO_OS_BIT(12)

#define	ADE7978_MASK0_REVFRPB NO_OS_BIT(11)

#define	ADE7978_MASK0_REVFRPA NO_OS_BIT(10)

#define	ADE7978_MASK0_REVPSUM1 NO_OS_BIT(9)

#define	ADE7978_MASK0_REVAPC NO_OS_BIT(8)

#define	ADE7978_MASK0_REVAPB NO_OS_BIT(7)

#define	ADE7978_MASK0_REVAPA NO_OS_BIT(6)

#define	ADE7978_MASK0_LENERGY NO_OS_BIT(5)

#define	ADE7978_MASK0_VAEHF NO_OS_BIT(4)

#define	ADE7978_MASK0_FREHF NO_OS_BIT(3)

#define	ADE7978_MASK0_REHF NO_OS_BIT(2)

#define	ADE7978_MASK0_FAEHF NO_OS_BIT(1)

#define	ADE7978_MASK0_AEHF NO_OS_BIT(0)

#define	ADE7978_MASK1_CRC NO_OS_BIT(25)

#define	ADE7978_MASK1_PKV NO_OS_BIT(24)

#define	ADE7978_MASK1_PKI NO_OS_BIT(23)

#define	ADE7978_MASK1_MISMTCH NO_OS_BIT(20)

#define	ADE7978_MASK1_SEQERR NO_OS_BIT(19)

#define	ADE7978_MASK1_OV NO_OS_BIT(18)

#define	ADE7978_MASK1_OI NO_OS_BIT(17)

#define	ADE7978_MASK1_SAG NO_OS_BIT(16)

#define	ADE7978_MASK1_RSTDONE NO_OS_BIT(15)

#define	ADE7978_MASK1_ZXIC NO_OS_BIT(14)

#define	ADE7978_MASK1_ZXIB NO_OS_BIT(13)

#define	ADE7978_MASK1_ZXIA NO_OS_BIT(12)

#define	ADE7978_MASK1_ZXVC NO_OS_BIT(11)

#define	ADE7978_MASK1_ZXVB NO_OS_BIT(10)

#define	ADE7978_MASK1_ZXVA NO_OS_BIT(9)

#define	ADE7978_MASK1_ZXTOIC NO_OS_BIT(8)

#define	ADE7978_MASK1_ZXTOIB NO_OS_BIT(7)

#define	ADE7978_MASK1_ZXTOIA NO_OS_BIT(6)

#define	ADE7978_MASK1_ZXTOVC NO_OS_BIT(5)

#define	ADE7978_MASK1_ZXTOVB NO_OS_BIT(4)

#define	ADE7978_MASK1_ZXTOVA NO_OS_BIT(3)

#define	ADE7978_MASK1_VANLOAD NO_OS_BIT(2)

#define	ADE7978_MASK1_FNLOAD NO_OS_BIT(1)

#define	ADE7978_MASK1_NLOAD NO_OS_BIT(0)

#define	ADE7978_VSPHASE2 NO_OS_BIT(14)

#define	ADE7978_VSPHASE1 NO_OS_BIT(13)

#define	ADE7978_VSPHASE0 NO_OS_BIT(12)

#define	ADE7978_OVPHASE2 NO_OS_BIT(11)

#define	ADE7978_OVPHASE1 NO_OS_BIT(10)

#define	ADE7978_OVPHASE0 NO_OS_BIT(9)

#define	ADE7978_OIPHASE2 NO_OS_BIT(5)

#define	ADE7978_OIPHASE1 NO_OS_BIT(4)

#define	ADE7978_OIPHASE0 NO_OS_BIT(3)

#define	ADE7978_VANLPHASE2 NO_OS_BIT(8)

#define	ADE7978_VANLPHASE1 NO_OS_BIT(7)

#define	ADE7978_VANLPHASE0 NO_OS_BIT(6)

#define	ADE7978_FNLPHASE2 NO_OS_BIT(5)

#define	ADE7978_FNLPHASE1 NO_OS_BIT(4)

#define	ADE7978_FNLPHASE0 NO_OS_BIT(3)

#define	ADE7978_NLPHASE2 NO_OS_BIT(2)

#define	ADE7978_NLPHASE1 NO_OS_BIT(1)

#define	ADE7978_NLPHASE0 NO_OS_BIT(0)

#define	ADE7978_SELFREQ NO_OS_BIT(14)

#define	ADE7978_VNOMCEN NO_OS_BIT(13)

#define	ADE7978_VNOMBEN NO_OS_BIT(12)

#define	ADE7978_VNOMAEN NO_OS_BIT(11)

#define	ADE7978_ANGLESEL NO_OS_GENMASK(10, 9)

#define	ADE7978_TERMSEL3_2 NO_OS_BIT(8)

#define	ADE7978_TERMSEL3_1 NO_OS_BIT(7)

#define	ADE7978_TERMSEL3_0 NO_OS_BIT(6)

#define	ADE7978_TERMSEL2_2 NO_OS_BIT(5)

#define	ADE7978_TERMSEL2_1 NO_OS_BIT(4)

#define	ADE7978_TERMSEL2_0 NO_OS_BIT(3)

#define	ADE7978_TERMSEL1_2 NO_OS_BIT(2)

#define	ADE7978_TERMSEL1_1 NO_OS_BIT(1)

#define	ADE7978_TERMSEL1_0 NO_OS_BIT(0)

#define	ADE7978_CF3LATCH NO_OS_BIT(14)

#define	ADE7978_CF2LATCH NO_OS_BIT(13)

#define	ADE7978_CF1LATCH NO_OS_BIT(12)

#define	ADE7978_CF3DIS NO_OS_BIT(11)

#define	ADE7978_CF2DIS NO_OS_BIT(10)

#define	ADE7978_CF1DIS NO_OS_BIT(9)

#define	ADE7978_CF3SEL NO_OS_GENMASK(8, 6)

#define	ADE7978_CF2SEL NO_OS_GENMASK(5, 3)

#define	ADE7978_CF1SEL NO_OS_GENMASK(2, 0)

#define	ADE7978_PHCALVAL NO_OS_GENMASK(9, 0)

#define	ADE7978_SUM3SIGN NO_OS_BIT(8)

#define	ADE7978_SUM2SIGN NO_OS_BIT(7)

#define	ADE7978_CVARSIGN NO_OS_BIT(6)

#define	ADE7978_BVARSIGN NO_OS_BIT(5)

#define	ADE7978_AVARSIGN NO_OS_BIT(4)

#define	ADE7978_SUM1SIGN NO_OS_BIT(3)

#define	ADE7978_CWSIGN NO_OS_BIT(2)

#define	ADE7978_BWSIGN NO_OS_BIT(1)

#define	ADE7978_AWSIGN NO_OS_BIT(0)

#define	ADE7978_INSEL NO_OS_BIT(14)

#define	ADE7978_VTOIC NO_OS_GENMASK(13, 12)

#define	ADE7978_VTOIB NO_OS_GENMASK(11, 10)

#define	ADE7978_VTOIA NO_OS_GENMASK(9, 8)

#define	ADE7978_SWRST NO_OS_BIT(7)

#define	ADE7978_HSDCEN NO_OS_BIT(6)

#define	ADE7978_LPFSEL NO_OS_BIT(5)

#define	ADE7978_HPFEN NO_OS_BIT(4)

#define	ADE7978_SWAP NO_OS_BIT(3)

#define	ADE7978_ZX_DREADY NO_OS_GENMASK(1, 0)

#define	ADE7978_PEAKSEL2 NO_OS_BIT(4)

#define	ADE7978_PEAKSEL1 NO_OS_BIT(3)

#define	ADE7978_PEAKSEL0 NO_OS_BIT(2)

#define	ADE7978_REVRPSEL NO_OS_BIT(1)

#define	ADE7978_REVAPSEL NO_OS_BIT(0)

#define	ADE7978_SAGCFG NO_OS_BIT(6)

#define	ADE7978_CONSEL NO_OS_GENMASK(5, 4)

#define	ADE7978_VARACC NO_OS_GENMASK(3, 2)

#define	ADE7978_WATTACC NO_OS_GENMASK(1, 0)

#define	ADE7978_PFMODE NO_OS_BIT(7)

#define	ADE7978_RSTREAD NO_OS_BIT(6)

#define	ADE7978_ZXSEL2 NO_OS_BIT(5)

#define	ADE7978_ZXSEL1 NO_OS_BIT(4)

#define	ADE7978_ZXSEL0 NO_OS_BIT(3)

#define	ADE7978_LVA NO_OS_BIT(2)

#define	ADE7978_LVAR NO_OS_BIT(1)

#define	ADE7978_LWATT NO_OS_BIT(0)

#define	ADE7978_HSAPOL NO_OS_BIT(5)

#define	ADE7978_HXFER NO_OS_GENMASK(4, 3)

#define	ADE7978_HGAP NO_OS_BIT(2)

#define	ADE7978_HSIZE NO_OS_BIT(1)

#define	ADE7978_HCLK NO_OS_BIT(0)

#define	ADE7978_ADE7933_SWRST NO_OS_BIT(7)

#define	ADE7978_CLKOUT_DIS NO_OS_BIT(6)

#define	ADE7978_VN2_EN NO_OS_BIT(3)

#define	ADE7978_VC2_EN NO_OS_BIT(2)

#define	ADE7978_VB2_EN NO_OS_BIT(1)

#define	ADE7978_VA2_EN NO_OS_BIT(0)

#define	ADE7978_I2C_LOCK NO_OS_BIT(0)

#define	IS_8BITS_REG(x)

#define	IS_16BITS_REG(x)

#define	ADE7978_CHIP_ID 0x0E88

#define	ADE7978_RESET_RECOVER 100

#define	ADE7978_SET_SPI_ADDR 0xEBFF

#define	ADE7978_DUMB_VAL 0x01

#define	ADE7978_RAM_PROTECTION1 0xE7FE

#define	ADE7978_RAM_PROTECTION2 0xE7E3

#define	ADE7978_RAM_PROT_VAL1 0xAD

#define	ADE7978_RAM_PROT_VAL2 0x80

#define	ADE7978_RUN_ON 0x0001

#define	ADE7978_WAVE_FS_CODES 5320000

#define	ADE7978_RMS_FS_CODES 3761808

#define	ADE7978_FS_VOLTAGE_RMS 3535

#define	ADE7978_FS_CURRENT_RMS 22094

#define	ADE7978_FS_CURRENT 31250

#define	ADE7978_FS_VOLTAGE 500

Enumerations
enum	ade7978_cfxsel_e { ADE7978_CFXSEL_0 , ADE7978_CFXSEL_1 , ADE7978_CFXSEL_2 , ADE7978_CFXSEL_3 , ADE7978_CFXSEL_4 }
	ADE7978 These bits indicate the value the CFx frequency is proportional to. More...

enum	ade7978_zx_dready_e { ADE7978_DREADY_EN , ADE7978_ZX_PHASE_A , ADE7978_ZX_PHASE_B , ADE7978_ZX_PHASE_C }
	ADE7978 These bits manage the output signal at the ZX/DREADY pin. More...

enum	ade7978_vtoia_e { ADE7978_VTOIA_A , ADE7978_VTOIA_B , ADE7978_VTOIA_C }
	ADE7978 These bits decide what phase voltage is considered together with Phase A current in the power path. More...

enum	ade7978_vtoib_e { ADE7978_VTOIB_B , ADE7978_VTOIB_C , ADE7978_VTOIB_A }
	ADE7978 These bits decide what phase voltage is considered together with Phase B current in the power path. More...

enum	ade7978_vtoic_e { ADE7978_VTOIC_C , ADE7978_VTOIC_A , ADE7978_VTOIC_B }
	ADE7978 These bits decide what phase voltage is considered together with Phase C current in the power path. More...

enum	ade7978_wattacc_e { ADE7978_WATTACC_SIGNED_ACC , ADE7978_WATTACC_POSITIVE_ACC , ADE7978_WATTACC_RESERVED , ADE7978_WATTACC_ABSOLUTE_ACC }
	ADE7978 These bits decide the accumulation mode of fundamental active powers. More...

enum	ade7978_varacc_e { ADE7978_VARACC_SIGNED_ACC , ADE7978_VARACC_RESERVED , ADE7978_VARACC_SIGN_WATTACC , ADE7978_VARACC_ABSOLUTE_ACC }
	ADE7978 These bits decide the accumulation mode of funamental reactive powers. More...

enum	ade7978_consel_e { ADE7978_CONSEL_3P_3W , ADE7978_CONSEL_3P_3W_DELTA , ADE7978_CONSEL_3P_4W_DELTA }
	ADE7978 These bits select the inputs to the energy accumulation registers. IA’, IB’, and IC’ are IA, IB, and IC shifted respectively by −90° More...

enum	ade7978_hxfer_e { ADE7978_HXFER_16 , ADE7978_HXFER_7 , ADE7978_HXFER_9 , ADE7978_HXFER_RESERVED }
	ADE7978 These bits select the data transmitted on HSDC. More...

enum	ade7978_freq_sel_e { ADE7978_SELFREQ_50 , ADE7978_SELFREQ_60 }
	ADE7978 Freq value. More...

enum	ade7978_phase { ADE7978_PHASE_A , ADE7978_PHASE_B , ADE7978_PHASE_C }
	ADE7978 available phases. More...

Functions
int	ade7978_read (struct ade7978_dev dev, uint16_t reg_addr, uint32_t reg_data)
	Read device register.

int	ade7978_write (struct ade7978_dev *dev, uint16_t reg_addr, uint32_t reg_data)
	Write device register.

int	ade7978_update_bits (struct ade7978_dev *dev, uint16_t reg_addr, uint32_t mask, uint32_t reg_data)
	Update specific register bits.

int	ade7978_read_data_ph (struct ade7978_dev *dev, enum ade7978_phase phase)
	Read the measurements for specific phase.

int	ade7978_init (struct ade7978_dev **device, struct ade7978_init_param init_param)
	Initialize the device.

int	ade7978_setup (struct ade7978_dev *dev)
	Setup the device.

int	ade7978_remove (struct ade7978_dev *dev)
	Remove the device and release resources.

int	ade7978_get_int_status0 (struct ade7978_dev dev, uint32_t msk, uint8_t status)
	Get interrupt indicator from STATUS0 register.

int	ade7978_get_int_status1 (struct ade7978_dev dev, uint32_t msk, uint8_t status)
	Get interrupt indicator from STATUS1 register.

Detailed Description

Header file of ADE7978 Driver.

Author: REtz (radu..nosp@m.etz@.nosp@m.analo.nosp@m.g.co.nosp@m.m)

SPDX-License-Identifier: BSD-3-Clause

Macro Definition Documentation

◆ ADE7978_ADE7933_SWRST

#define ADE7978_ADE7933_SWRST NO_OS_BIT(7)

◆ ADE7978_ANGLESEL

#define ADE7978_ANGLESEL NO_OS_GENMASK(10, 9)

◆ ADE7978_AVARSIGN

#define ADE7978_AVARSIGN NO_OS_BIT(4)

◆ ADE7978_AWSIGN

#define ADE7978_AWSIGN NO_OS_BIT(0)

◆ ADE7978_BVARSIGN

#define ADE7978_BVARSIGN NO_OS_BIT(5)

◆ ADE7978_BWSIGN

#define ADE7978_BWSIGN NO_OS_BIT(1)

◆ ADE7978_CF1DIS

#define ADE7978_CF1DIS NO_OS_BIT(9)

◆ ADE7978_CF1LATCH

#define ADE7978_CF1LATCH NO_OS_BIT(12)

◆ ADE7978_CF1SEL

#define ADE7978_CF1SEL NO_OS_GENMASK(2, 0)

◆ ADE7978_CF2DIS

#define ADE7978_CF2DIS NO_OS_BIT(10)

◆ ADE7978_CF2LATCH

#define ADE7978_CF2LATCH NO_OS_BIT(13)

◆ ADE7978_CF2SEL

#define ADE7978_CF2SEL NO_OS_GENMASK(5, 3)

◆ ADE7978_CF3DIS

#define ADE7978_CF3DIS NO_OS_BIT(11)

◆ ADE7978_CF3LATCH

#define ADE7978_CF3LATCH NO_OS_BIT(14)

◆ ADE7978_CF3SEL

#define ADE7978_CF3SEL NO_OS_GENMASK(8, 6)

◆ ADE7978_CHIP_ID

#define ADE7978_CHIP_ID 0x0E88

◆ ADE7978_CLKOUT_DIS

#define ADE7978_CLKOUT_DIS NO_OS_BIT(6)

◆ ADE7978_CONSEL

#define ADE7978_CONSEL NO_OS_GENMASK(5, 4)

◆ ADE7978_CVARSIGN

#define ADE7978_CVARSIGN NO_OS_BIT(6)

◆ ADE7978_CWSIGN

#define ADE7978_CWSIGN NO_OS_BIT(2)

◆ ADE7978_DUMB_VAL

#define ADE7978_DUMB_VAL 0x01

◆ ADE7978_FNLPHASE0

#define ADE7978_FNLPHASE0 NO_OS_BIT(3)

◆ ADE7978_FNLPHASE1

#define ADE7978_FNLPHASE1 NO_OS_BIT(4)

◆ ADE7978_FNLPHASE2

#define ADE7978_FNLPHASE2 NO_OS_BIT(5)

◆ ADE7978_FS_CURRENT

#define ADE7978_FS_CURRENT 31250

◆ ADE7978_FS_CURRENT_RMS

#define ADE7978_FS_CURRENT_RMS 22094

◆ ADE7978_FS_VOLTAGE

#define ADE7978_FS_VOLTAGE 500

◆ ADE7978_FS_VOLTAGE_RMS

#define ADE7978_FS_VOLTAGE_RMS 3535

◆ ADE7978_HCLK

#define ADE7978_HCLK NO_OS_BIT(0)

◆ ADE7978_HGAP

#define ADE7978_HGAP NO_OS_BIT(2)

◆ ADE7978_HPFEN

#define ADE7978_HPFEN NO_OS_BIT(4)

◆ ADE7978_HSAPOL

#define ADE7978_HSAPOL NO_OS_BIT(5)

◆ ADE7978_HSDCEN

#define ADE7978_HSDCEN NO_OS_BIT(6)

◆ ADE7978_HSIZE

#define ADE7978_HSIZE NO_OS_BIT(1)

◆ ADE7978_HXFER

#define ADE7978_HXFER NO_OS_GENMASK(4, 3)

◆ ADE7978_I2C_LOCK

#define ADE7978_I2C_LOCK NO_OS_BIT(0)

◆ ADE7978_INSEL

#define ADE7978_INSEL NO_OS_BIT(14)

◆ ADE7978_IPEAKVAL

#define ADE7978_IPEAKVAL NO_OS_GENMASK(23, 0)

◆ ADE7978_IPPHASE0

#define ADE7978_IPPHASE0 NO_OS_BIT(24)

◆ ADE7978_IPPHASE1

#define ADE7978_IPPHASE1 NO_OS_BIT(25)

◆ ADE7978_IPPHASE2

#define ADE7978_IPPHASE2 NO_OS_BIT(26)

◆ ADE7978_LPFSEL

#define ADE7978_LPFSEL NO_OS_BIT(5)

◆ ADE7978_LVA

#define ADE7978_LVA NO_OS_BIT(2)

◆ ADE7978_LVAR

#define ADE7978_LVAR NO_OS_BIT(1)

◆ ADE7978_LWATT

#define ADE7978_LWATT NO_OS_BIT(0)

◆ ADE7978_MASK0_AEHF

#define ADE7978_MASK0_AEHF NO_OS_BIT(0)

◆ ADE7978_MASK0_CF1

#define ADE7978_MASK0_CF1 NO_OS_BIT(14)

◆ ADE7978_MASK0_CF2

#define ADE7978_MASK0_CF2 NO_OS_BIT(15)

◆ ADE7978_MASK0_CF3

#define ADE7978_MASK0_CF3 NO_OS_BIT(16)

◆ ADE7978_MASK0_DREADY

#define ADE7978_MASK0_DREADY NO_OS_BIT(17)

◆ ADE7978_MASK0_FAEHF

#define ADE7978_MASK0_FAEHF NO_OS_BIT(1)

◆ ADE7978_MASK0_FREHF

#define ADE7978_MASK0_FREHF NO_OS_BIT(3)

◆ ADE7978_MASK0_HREADY

#define ADE7978_MASK0_HREADY NO_OS_BIT(19)

◆ ADE7978_MASK0_LENERGY

#define ADE7978_MASK0_LENERGY NO_OS_BIT(5)

◆ ADE7978_MASK0_REHF

#define ADE7978_MASK0_REHF NO_OS_BIT(2)

◆ ADE7978_MASK0_REVAPA

#define ADE7978_MASK0_REVAPA NO_OS_BIT(6)

◆ ADE7978_MASK0_REVAPB

#define ADE7978_MASK0_REVAPB NO_OS_BIT(7)

◆ ADE7978_MASK0_REVAPC

#define ADE7978_MASK0_REVAPC NO_OS_BIT(8)

◆ ADE7978_MASK0_REVFRPA

#define ADE7978_MASK0_REVFRPA NO_OS_BIT(10)

◆ ADE7978_MASK0_REVFRPB

#define ADE7978_MASK0_REVFRPB NO_OS_BIT(11)

◆ ADE7978_MASK0_REVFRPC

#define ADE7978_MASK0_REVFRPC NO_OS_BIT(12)

◆ ADE7978_MASK0_REVPSUM1

#define ADE7978_MASK0_REVPSUM1 NO_OS_BIT(9)

◆ ADE7978_MASK0_REVPSUM2

#define ADE7978_MASK0_REVPSUM2 NO_OS_BIT(13)

◆ ADE7978_MASK0_REVPSUM3

#define ADE7978_MASK0_REVPSUM3 NO_OS_BIT(18)

◆ ADE7978_MASK0_VAEHF

#define ADE7978_MASK0_VAEHF NO_OS_BIT(4)

◆ ADE7978_MASK1_CRC

#define ADE7978_MASK1_CRC NO_OS_BIT(25)

◆ ADE7978_MASK1_FNLOAD

#define ADE7978_MASK1_FNLOAD NO_OS_BIT(1)

◆ ADE7978_MASK1_MISMTCH

#define ADE7978_MASK1_MISMTCH NO_OS_BIT(20)

◆ ADE7978_MASK1_NLOAD

#define ADE7978_MASK1_NLOAD NO_OS_BIT(0)

◆ ADE7978_MASK1_OI

#define ADE7978_MASK1_OI NO_OS_BIT(17)

◆ ADE7978_MASK1_OV

#define ADE7978_MASK1_OV NO_OS_BIT(18)

◆ ADE7978_MASK1_PKI

#define ADE7978_MASK1_PKI NO_OS_BIT(23)

◆ ADE7978_MASK1_PKV

#define ADE7978_MASK1_PKV NO_OS_BIT(24)

◆ ADE7978_MASK1_RSTDONE

#define ADE7978_MASK1_RSTDONE NO_OS_BIT(15)

◆ ADE7978_MASK1_SAG

#define ADE7978_MASK1_SAG NO_OS_BIT(16)

◆ ADE7978_MASK1_SEQERR

#define ADE7978_MASK1_SEQERR NO_OS_BIT(19)

◆ ADE7978_MASK1_VANLOAD

#define ADE7978_MASK1_VANLOAD NO_OS_BIT(2)

◆ ADE7978_MASK1_ZXIA

#define ADE7978_MASK1_ZXIA NO_OS_BIT(12)

◆ ADE7978_MASK1_ZXIB

#define ADE7978_MASK1_ZXIB NO_OS_BIT(13)

◆ ADE7978_MASK1_ZXIC

#define ADE7978_MASK1_ZXIC NO_OS_BIT(14)

◆ ADE7978_MASK1_ZXTOIA

#define ADE7978_MASK1_ZXTOIA NO_OS_BIT(6)

◆ ADE7978_MASK1_ZXTOIB

#define ADE7978_MASK1_ZXTOIB NO_OS_BIT(7)

◆ ADE7978_MASK1_ZXTOIC

#define ADE7978_MASK1_ZXTOIC NO_OS_BIT(8)

◆ ADE7978_MASK1_ZXTOVA

#define ADE7978_MASK1_ZXTOVA NO_OS_BIT(3)

◆ ADE7978_MASK1_ZXTOVB

#define ADE7978_MASK1_ZXTOVB NO_OS_BIT(4)

◆ ADE7978_MASK1_ZXTOVC

#define ADE7978_MASK1_ZXTOVC NO_OS_BIT(5)

◆ ADE7978_MASK1_ZXVA

#define ADE7978_MASK1_ZXVA NO_OS_BIT(9)

◆ ADE7978_MASK1_ZXVB

#define ADE7978_MASK1_ZXVB NO_OS_BIT(10)

◆ ADE7978_MASK1_ZXVC

#define ADE7978_MASK1_ZXVC NO_OS_BIT(11)

◆ ADE7978_NLPHASE0

#define ADE7978_NLPHASE0 NO_OS_BIT(0)

◆ ADE7978_NLPHASE1

#define ADE7978_NLPHASE1 NO_OS_BIT(1)

◆ ADE7978_NLPHASE2

#define ADE7978_NLPHASE2 NO_OS_BIT(2)

◆ ADE7978_OIPHASE0

#define ADE7978_OIPHASE0 NO_OS_BIT(3)

◆ ADE7978_OIPHASE1

#define ADE7978_OIPHASE1 NO_OS_BIT(4)

◆ ADE7978_OIPHASE2

#define ADE7978_OIPHASE2 NO_OS_BIT(5)

◆ ADE7978_OVPHASE0

#define ADE7978_OVPHASE0 NO_OS_BIT(9)

◆ ADE7978_OVPHASE1

#define ADE7978_OVPHASE1 NO_OS_BIT(10)

◆ ADE7978_OVPHASE2

#define ADE7978_OVPHASE2 NO_OS_BIT(11)

◆ ADE7978_PEAKSEL0

#define ADE7978_PEAKSEL0 NO_OS_BIT(2)

◆ ADE7978_PEAKSEL1

#define ADE7978_PEAKSEL1 NO_OS_BIT(3)

◆ ADE7978_PEAKSEL2

#define ADE7978_PEAKSEL2 NO_OS_BIT(4)

◆ ADE7978_PFMODE

#define ADE7978_PFMODE NO_OS_BIT(7)

◆ ADE7978_PHCALVAL

#define ADE7978_PHCALVAL NO_OS_GENMASK(9, 0)

◆ ADE7978_RAM_PROT_VAL1

#define ADE7978_RAM_PROT_VAL1 0xAD

◆ ADE7978_RAM_PROT_VAL2

#define ADE7978_RAM_PROT_VAL2 0x80

◆ ADE7978_RAM_PROTECTION1

#define ADE7978_RAM_PROTECTION1 0xE7FE

◆ ADE7978_RAM_PROTECTION2

#define ADE7978_RAM_PROTECTION2 0xE7E3

◆ ADE7978_REG_ACCMODE

#define ADE7978_REG_ACCMODE 0xE701

◆ ADE7978_REG_AFIRMS

#define ADE7978_REG_AFIRMS 0xE537

◆ ADE7978_REG_AFIRMSOS

#define ADE7978_REG_AFIRMSOS 0x43A9

◆ ADE7978_REG_AFVARHR

#define ADE7978_REG_AFVARHR 0xE409

◆ ADE7978_REG_AFVAROS

#define ADE7978_REG_AFVAROS 0x43A6

◆ ADE7978_REG_AFVRMS

#define ADE7978_REG_AFVRMS 0xE538

◆ ADE7978_REG_AFVRMSOS

#define ADE7978_REG_AFVRMSOS 0x43AC

◆ ADE7978_REG_AFWATTHR

#define ADE7978_REG_AFWATTHR 0xE403

◆ ADE7978_REG_AFWATTOS

#define ADE7978_REG_AFWATTOS 0x43A3

◆ ADE7978_REG_AIGAIN

#define ADE7978_REG_AIGAIN 0x4380

◆ ADE7978_REG_AIRMS

#define ADE7978_REG_AIRMS 0x43C0

◆ ADE7978_REG_AIRMSOS

#define ADE7978_REG_AIRMSOS 0x438C

◆ ADE7978_REG_AITHD

#define ADE7978_REG_AITHD 0xE522

◆ ADE7978_REG_ANGLE0

#define ADE7978_REG_ANGLE0 0xE601

◆ ADE7978_REG_ANGLE1

#define ADE7978_REG_ANGLE1 0xE602

◆ ADE7978_REG_ANGLE2

#define ADE7978_REG_ANGLE2 0xE603

◆ ADE7978_REG_APERIOD

#define ADE7978_REG_APERIOD 0xE905

◆ ADE7978_REG_APF

#define ADE7978_REG_APF 0xE902

◆ ADE7978_REG_APGAIN

#define ADE7978_REG_APGAIN 0x4399

◆ ADE7978_REG_APHCAL

#define ADE7978_REG_APHCAL 0xE614

◆ ADE7978_REG_APNOLOAD

#define ADE7978_REG_APNOLOAD 0xE908

◆ ADE7978_REG_ATEMP

#define ADE7978_REG_ATEMP 0X43CB

◆ ADE7978_REG_ATEMP0

#define ADE7978_REG_ATEMP0 0x43B0

◆ ADE7978_REG_ATEMPOS

#define ADE7978_REG_ATEMPOS 0xE709

◆ ADE7978_REG_ATGAIN

#define ADE7978_REG_ATGAIN 0x43B4

◆ ADE7978_REG_AV2GAIN

#define ADE7978_REG_AV2GAIN 0x4382

◆ ADE7978_REG_AV2RMS

#define ADE7978_REG_AV2RMS 0x43C2

◆ ADE7978_REG_AV2RMSOS

#define ADE7978_REG_AV2RMSOS 0x438E

◆ ADE7978_REG_AVA

#define ADE7978_REG_AVA 0xE51E

◆ ADE7978_REG_AVAHR

#define ADE7978_REG_AVAHR 0xE40C

◆ ADE7978_REG_AVAR

#define ADE7978_REG_AVAR 0xE51B

◆ ADE7978_REG_AVARHR

#define ADE7978_REG_AVARHR 0xE406

◆ ADE7978_REG_AVAROS

#define ADE7978_REG_AVAROS 0x439F

◆ ADE7978_REG_AVGAIN

#define ADE7978_REG_AVGAIN 0x4381

◆ ADE7978_REG_AVRMS

#define ADE7978_REG_AVRMS 0x43C1

◆ ADE7978_REG_AVRMSOS

#define ADE7978_REG_AVRMSOS 0x438D

◆ ADE7978_REG_AVTHD

#define ADE7978_REG_AVTHD 0xE521

◆ ADE7978_REG_AWATT

#define ADE7978_REG_AWATT 0xE518

◆ ADE7978_REG_AWATTHR

#define ADE7978_REG_AWATTHR 0xE400

◆ ADE7978_REG_AWATTOS

#define ADE7978_REG_AWATTOS 0x439C

◆ ADE7978_REG_BFIRMS

#define ADE7978_REG_BFIRMS 0xE539

◆ ADE7978_REG_BFIRMSOS

#define ADE7978_REG_BFIRMSOS 0x43AA

◆ ADE7978_REG_BFVARHR

#define ADE7978_REG_BFVARHR 0xE40A

◆ ADE7978_REG_BFVAROS

#define ADE7978_REG_BFVAROS 0x43A7

◆ ADE7978_REG_BFVRMS

#define ADE7978_REG_BFVRMS 0xE53A

◆ ADE7978_REG_BFVRMSOS

#define ADE7978_REG_BFVRMSOS 0x43AD

◆ ADE7978_REG_BFWATTHR

#define ADE7978_REG_BFWATTHR 0xE404

◆ ADE7978_REG_BFWATTOS

#define ADE7978_REG_BFWATTOS 0x43A4

◆ ADE7978_REG_BIGAIN

#define ADE7978_REG_BIGAIN 0x4383

◆ ADE7978_REG_BIRMS

#define ADE7978_REG_BIRMS 0x43C3

◆ ADE7978_REG_BIRMSOS

#define ADE7978_REG_BIRMSOS 0x438F

◆ ADE7978_REG_BITHD

#define ADE7978_REG_BITHD 0xE524

◆ ADE7978_REG_BPERIOD

#define ADE7978_REG_BPERIOD 0xE906

◆ ADE7978_REG_BPF

#define ADE7978_REG_BPF 0xE903

◆ ADE7978_REG_BPGAIN

#define ADE7978_REG_BPGAIN 0x439A

◆ ADE7978_REG_BPHCAL

#define ADE7978_REG_BPHCAL 0xE615

◆ ADE7978_REG_BTEMP

#define ADE7978_REG_BTEMP 0X43CC

◆ ADE7978_REG_BTEMP0

#define ADE7978_REG_BTEMP0 0x43B1

◆ ADE7978_REG_BTEMPOS

#define ADE7978_REG_BTEMPOS 0xE70A

◆ ADE7978_REG_BTGAIN

#define ADE7978_REG_BTGAIN 0x43B5

◆ ADE7978_REG_BV2GAIN

#define ADE7978_REG_BV2GAIN 0x4385

◆ ADE7978_REG_BV2RMS

#define ADE7978_REG_BV2RMS 0x43C5

◆ ADE7978_REG_BV2RMSOS

#define ADE7978_REG_BV2RMSOS 0x4391

◆ ADE7978_REG_BVA

#define ADE7978_REG_BVA 0xE51F

◆ ADE7978_REG_BVAHR

#define ADE7978_REG_BVAHR 0xE40D

◆ ADE7978_REG_BVAR

#define ADE7978_REG_BVAR 0xE51C

◆ ADE7978_REG_BVARHR

#define ADE7978_REG_BVARHR 0xE407

◆ ADE7978_REG_BVAROS

#define ADE7978_REG_BVAROS 0x43A0

◆ ADE7978_REG_BVGAIN

#define ADE7978_REG_BVGAIN 0x4384

◆ ADE7978_REG_BVRMS

#define ADE7978_REG_BVRMS 0x43C4

◆ ADE7978_REG_BVRMSOS

#define ADE7978_REG_BVRMSOS 0x4390

◆ ADE7978_REG_BVTHD

#define ADE7978_REG_BVTHD 0xE523

◆ ADE7978_REG_BWATT

#define ADE7978_REG_BWATT 0xE519

◆ ADE7978_REG_BWATTHR

#define ADE7978_REG_BWATTHR 0xE401

◆ ADE7978_REG_BWATTOS

#define ADE7978_REG_BWATTOS 0x439D

◆ ADE7978_REG_CF1DEN

#define ADE7978_REG_CF1DEN 0xE611

◆ ADE7978_REG_CF2DEN

#define ADE7978_REG_CF2DEN 0xE612

◆ ADE7978_REG_CF3DEN

#define ADE7978_REG_CF3DEN 0xE613

◆ ADE7978_REG_CFCYC

#define ADE7978_REG_CFCYC 0xE705

◆ ADE7978_REG_CFIRMS

#define ADE7978_REG_CFIRMS 0xE53B

◆ ADE7978_REG_CFIRMSOS

#define ADE7978_REG_CFIRMSOS 0x43AB

◆ ADE7978_REG_CFMODE

#define ADE7978_REG_CFMODE 0xE610

◆ ADE7978_REG_CFVARHR

#define ADE7978_REG_CFVARHR 0xE40B

◆ ADE7978_REG_CFVAROS

#define ADE7978_REG_CFVAROS 0x43A8

◆ ADE7978_REG_CFVRMS

#define ADE7978_REG_CFVRMS 0xE53C

◆ ADE7978_REG_CFVRMSOS

#define ADE7978_REG_CFVRMSOS 0x43AE

◆ ADE7978_REG_CFWATTHR

#define ADE7978_REG_CFWATTHR 0xE405

◆ ADE7978_REG_CFWATTOS

#define ADE7978_REG_CFWATTOS 0x43A5

◆ ADE7978_REG_CHECKSUM

#define ADE7978_REG_CHECKSUM 0xE532

◆ ADE7978_REG_CIGAIN

#define ADE7978_REG_CIGAIN 0x4386

◆ ADE7978_REG_CIRMS

#define ADE7978_REG_CIRMS 0x43C6

◆ ADE7978_REG_CIRMSOS

#define ADE7978_REG_CIRMSOS 0x4392

◆ ADE7978_REG_CITHD

#define ADE7978_REG_CITHD 0xE526

◆ ADE7978_REG_COMPMODE

#define ADE7978_REG_COMPMODE 0xE60E

◆ ADE7978_REG_CONFIG

#define ADE7978_REG_CONFIG 0xE618

◆ ADE7978_REG_CONFIG2

#define ADE7978_REG_CONFIG2 0xEA00

◆ ADE7978_REG_CONFIG3

#define ADE7978_REG_CONFIG3 0xE708

◆ ADE7978_REG_CPERIOD

#define ADE7978_REG_CPERIOD 0xE907

◆ ADE7978_REG_CPF

#define ADE7978_REG_CPF 0xE904

◆ ADE7978_REG_CPGAIN

#define ADE7978_REG_CPGAIN 0x439B

◆ ADE7978_REG_CPHCAL

#define ADE7978_REG_CPHCAL 0xE616

◆ ADE7978_REG_CTEMP

#define ADE7978_REG_CTEMP 0X43CD

◆ ADE7978_REG_CTEMP0

#define ADE7978_REG_CTEMP0 0x43B2

◆ ADE7978_REG_CTEMPOS

#define ADE7978_REG_CTEMPOS 0xE70B

◆ ADE7978_REG_CTGAIN

#define ADE7978_REG_CTGAIN 0x43B6

◆ ADE7978_REG_CV2GAIN

#define ADE7978_REG_CV2GAIN 0x4388

◆ ADE7978_REG_CV2RMS

#define ADE7978_REG_CV2RMS 0x43C8

◆ ADE7978_REG_CV2RMSOS

#define ADE7978_REG_CV2RMSOS 0x4394

◆ ADE7978_REG_CVA

#define ADE7978_REG_CVA 0xE520

◆ ADE7978_REG_CVAHR

#define ADE7978_REG_CVAHR 0xE40E

◆ ADE7978_REG_CVAR

#define ADE7978_REG_CVAR 0xE51D

◆ ADE7978_REG_CVARHR

#define ADE7978_REG_CVARHR 0xE408

◆ ADE7978_REG_CVAROS

#define ADE7978_REG_CVAROS 0x43A1

◆ ADE7978_REG_CVGAIN

#define ADE7978_REG_CVGAIN 0x4387

◆ ADE7978_REG_CVRMS

#define ADE7978_REG_CVRMS 0x43C7

◆ ADE7978_REG_CVRMSOS

#define ADE7978_REG_CVRMSOS 0x4393

◆ ADE7978_REG_CVTHD

#define ADE7978_REG_CVTHD 0xE525

◆ ADE7978_REG_CWATT

#define ADE7978_REG_CWATT 0xE51A

◆ ADE7978_REG_CWATTHR

#define ADE7978_REG_CWATTHR 0xE402

◆ ADE7978_REG_CWATTOS

#define ADE7978_REG_CWATTOS 0x439E

◆ ADE7978_REG_HSDC_CFG

#define ADE7978_REG_HSDC_CFG 0xE706

◆ ADE7978_REG_IAWV

#define ADE7978_REG_IAWV 0xE50C

◆ ADE7978_REG_IBWV

#define ADE7978_REG_IBWV 0xE50D

◆ ADE7978_REG_ICWV

#define ADE7978_REG_ICWV 0xE50E

◆ ADE7978_REG_INWV

#define ADE7978_REG_INWV 0xE50F

◆ ADE7978_REG_IPEAK

#define ADE7978_REG_IPEAK 0xE500

◆ ADE7978_REG_ISUM

#define ADE7978_REG_ISUM 0X43CA

◆ ADE7978_REG_ISUMLVL

#define ADE7978_REG_ISUMLVL 0x4398

◆ ADE7978_REG_LAST_ADD

#define ADE7978_REG_LAST_ADD 0xE9FE

◆ ADE7978_REG_LAST_OP

#define ADE7978_REG_LAST_OP 0xEA01

◆ ADE7978_REG_LAST_RWDATA16

#define ADE7978_REG_LAST_RWDATA16 0xE9FF

◆ ADE7978_REG_LAST_RWDATA32

#define ADE7978_REG_LAST_RWDATA32 0xE5FF

◆ ADE7978_REG_LAST_RWDATA8

#define ADE7978_REG_LAST_RWDATA8 0xE7FD

◆ ADE7978_REG_LCYCMODE

#define ADE7978_REG_LCYCMODE 0xE702

◆ ADE7978_REG_LINECYC

#define ADE7978_REG_LINECYC 0xE60C

◆ ADE7978_REG_MASK0

#define ADE7978_REG_MASK0 0xE50A

◆ ADE7978_REG_MASK1

#define ADE7978_REG_MASK1 0xE50B

◆ ADE7978_REG_MMODE

#define ADE7978_REG_MMODE 0xE700

◆ ADE7978_REG_NIGAIN

#define ADE7978_REG_NIGAIN 0x4389

◆ ADE7978_REG_NIRMS

#define ADE7978_REG_NIRMS 0X43C9

◆ ADE7978_REG_NIRMSOS

#define ADE7978_REG_NIRMSOS 0x4395

◆ ADE7978_REG_NTEMP

#define ADE7978_REG_NTEMP 0X43CE

◆ ADE7978_REG_NTEMPO

#define ADE7978_REG_NTEMPO 0x43B3

◆ ADE7978_REG_NTEMPOS

#define ADE7978_REG_NTEMPOS 0xE70C

◆ ADE7978_REG_NTGAIN

#define ADE7978_REG_NTGAIN 0x43B7

◆ ADE7978_REG_NV2GAIN

#define ADE7978_REG_NV2GAIN 0x438B

◆ ADE7978_REG_NV2RMS

#define ADE7978_REG_NV2RMS 0xE531

◆ ADE7978_REG_NV2RMSOS

#define ADE7978_REG_NV2RMSOS 0x4397

◆ ADE7978_REG_NVGAIN

#define ADE7978_REG_NVGAIN 0x438A

◆ ADE7978_REG_NVRMS

#define ADE7978_REG_NVRMS 0xE530

◆ ADE7978_REG_NVRMSOS

#define ADE7978_REG_NVRMSOS 0x4396

◆ ADE7978_REG_OILVL

#define ADE7978_REG_OILVL 0xE507

◆ ADE7978_REG_OVLVL

#define ADE7978_REG_OVLVL 0xE508

◆ ADE7978_REG_PEAKCYC

#define ADE7978_REG_PEAKCYC 0xE703

◆ ADE7978_REG_PHNOLOAD

#define ADE7978_REG_PHNOLOAD 0xE608

◆ ADE7978_REG_PHSIGN

#define ADE7978_REG_PHSIGN 0xE617

◆ ADE7978_REG_PHSTATUS

#define ADE7978_REG_PHSTATUS 0xE600

◆ ADE7978_REG_RUN

#define ADE7978_REG_RUN 0xE228

◆ ADE7978_REG_SAGCYC

#define ADE7978_REG_SAGCYC 0xE704

◆ ADE7978_REG_SAGLVL

#define ADE7978_REG_SAGLVL 0xE509

◆ ADE7978_REG_STATUS0

#define ADE7978_REG_STATUS0 0xE502

◆ ADE7978_REG_STATUS1

#define ADE7978_REG_STATUS1 0xE503

◆ ADE7978_REG_TEMPCO

#define ADE7978_REG_TEMPCO 0x43AF

◆ ADE7978_REG_VA2WV

#define ADE7978_REG_VA2WV 0xE513

◆ ADE7978_REG_VANOLOAD

#define ADE7978_REG_VANOLOAD 0xE90A

◆ ADE7978_REG_VARNOLOAD

#define ADE7978_REG_VARNOLOAD 0xE909

◆ ADE7978_REG_VARTHR

#define ADE7978_REG_VARTHR 0xEA03

◆ ADE7978_REG_VATHR

#define ADE7978_REG_VATHR 0xEA04

◆ ADE7978_REG_VAWV

#define ADE7978_REG_VAWV 0xE510

◆ ADE7978_REG_VB2WV

#define ADE7978_REG_VB2WV 0xE514

◆ ADE7978_REG_VBWV

#define ADE7978_REG_VBWV 0xE511

◆ ADE7978_REG_VC2WV

#define ADE7978_REG_VC2WV 0xE515

◆ ADE7978_REG_VCWV

#define ADE7978_REG_VCWV 0xE512

◆ ADE7978_REG_VERSION

#define ADE7978_REG_VERSION 0xE707

◆ ADE7978_REG_VN2WV

#define ADE7978_REG_VN2WV 0xE517

◆ ADE7978_REG_VNOM

#define ADE7978_REG_VNOM 0xE533

◆ ADE7978_REG_VNWV

#define ADE7978_REG_VNWV 0xE516

◆ ADE7978_REG_VPEAK

#define ADE7978_REG_VPEAK 0xE501

◆ ADE7978_REG_WTHR

#define ADE7978_REG_WTHR 0xEA02

◆ ADE7978_REG_ZXTOUT

#define ADE7978_REG_ZXTOUT 0xE60D

◆ ADE7978_RESET_RECOVER

#define ADE7978_RESET_RECOVER 100

◆ ADE7978_REVAPSEL

#define ADE7978_REVAPSEL NO_OS_BIT(0)

◆ ADE7978_REVRPSEL

#define ADE7978_REVRPSEL NO_OS_BIT(1)

◆ ADE7978_RMS_FS_CODES

#define ADE7978_RMS_FS_CODES 3761808

◆ ADE7978_RSTREAD

#define ADE7978_RSTREAD NO_OS_BIT(6)

◆ ADE7978_RUN_ON

#define ADE7978_RUN_ON 0x0001

◆ ADE7978_SAGCFG

#define ADE7978_SAGCFG NO_OS_BIT(6)

◆ ADE7978_SELFREQ

#define ADE7978_SELFREQ NO_OS_BIT(14)

◆ ADE7978_SET_SPI_ADDR

#define ADE7978_SET_SPI_ADDR 0xEBFF

◆ ADE7978_SPI_READ_CMD

#define ADE7978_SPI_READ_CMD 0x01

◆ ADE7978_SPI_WRITE_CMD

#define ADE7978_SPI_WRITE_CMD 0x00

◆ ADE7978_STATUS0_AEHF

#define ADE7978_STATUS0_AEHF NO_OS_BIT(0)

◆ ADE7978_STATUS0_CF1

#define ADE7978_STATUS0_CF1 NO_OS_BIT(14)

◆ ADE7978_STATUS0_CF2

#define ADE7978_STATUS0_CF2 NO_OS_BIT(15)

◆ ADE7978_STATUS0_CF3

#define ADE7978_STATUS0_CF3 NO_OS_BIT(16)

◆ ADE7978_STATUS0_DREADY

#define ADE7978_STATUS0_DREADY NO_OS_BIT(17)

◆ ADE7978_STATUS0_FAEHF

#define ADE7978_STATUS0_FAEHF NO_OS_BIT(1)

◆ ADE7978_STATUS0_FREHF

#define ADE7978_STATUS0_FREHF NO_OS_BIT(3)

◆ ADE7978_STATUS0_LENERGY

#define ADE7978_STATUS0_LENERGY NO_OS_BIT(5)

◆ ADE7978_STATUS0_REVAPA

#define ADE7978_STATUS0_REVAPA NO_OS_BIT(6)

◆ ADE7978_STATUS0_REVAPB

#define ADE7978_STATUS0_REVAPB NO_OS_BIT(7)

◆ ADE7978_STATUS0_REVAPC

#define ADE7978_STATUS0_REVAPC NO_OS_BIT(8)

◆ ADE7978_STATUS0_REVPSUM1

#define ADE7978_STATUS0_REVPSUM1 NO_OS_BIT(9)

◆ ADE7978_STATUS0_REVPSUM2

#define ADE7978_STATUS0_REVPSUM2 NO_OS_BIT(13)

◆ ADE7978_STATUS0_REVPSUM3

#define ADE7978_STATUS0_REVPSUM3 NO_OS_BIT(18)

◆ ADE7978_STATUS0_REVRPA

#define ADE7978_STATUS0_REVRPA NO_OS_BIT(10)

◆ ADE7978_STATUS0_REVRPB

#define ADE7978_STATUS0_REVRPB NO_OS_BIT(11)

◆ ADE7978_STATUS0_REVRPC

#define ADE7978_STATUS0_REVRPC NO_OS_BIT(12)

◆ ADE7978_STATUS0_VAEHF

#define ADE7978_STATUS0_VAEHF NO_OS_BIT(4)

◆ ADE7978_STATUS1_CRC

#define ADE7978_STATUS1_CRC NO_OS_BIT(25)

◆ ADE7978_STATUS1_FNLOAD

#define ADE7978_STATUS1_FNLOAD NO_OS_BIT(1)

◆ ADE7978_STATUS1_MISMTCH

#define ADE7978_STATUS1_MISMTCH NO_OS_BIT(20)

◆ ADE7978_STATUS1_NLOAD

#define ADE7978_STATUS1_NLOAD NO_OS_BIT(0)

◆ ADE7978_STATUS1_OI

#define ADE7978_STATUS1_OI NO_OS_BIT(17)

◆ ADE7978_STATUS1_OV

#define ADE7978_STATUS1_OV NO_OS_BIT(18)

◆ ADE7978_STATUS1_PKI

#define ADE7978_STATUS1_PKI NO_OS_BIT(23)

◆ ADE7978_STATUS1_PKV

#define ADE7978_STATUS1_PKV NO_OS_BIT(24)

◆ ADE7978_STATUS1_RSTDONE

#define ADE7978_STATUS1_RSTDONE NO_OS_BIT(15)

◆ ADE7978_STATUS1_SAG

#define ADE7978_STATUS1_SAG NO_OS_BIT(16)

◆ ADE7978_STATUS1_SEQERR

#define ADE7978_STATUS1_SEQERR NO_OS_BIT(19)

◆ ADE7978_STATUS1_VANLOAD

#define ADE7978_STATUS1_VANLOAD NO_OS_BIT(2)

◆ ADE7978_STATUS1_ZXIA

#define ADE7978_STATUS1_ZXIA NO_OS_BIT(12)

◆ ADE7978_STATUS1_ZXIB

#define ADE7978_STATUS1_ZXIB NO_OS_BIT(13)

◆ ADE7978_STATUS1_ZXIC

#define ADE7978_STATUS1_ZXIC NO_OS_BIT(14)

◆ ADE7978_STATUS1_ZXTOIA

#define ADE7978_STATUS1_ZXTOIA NO_OS_BIT(6)

◆ ADE7978_STATUS1_ZXTOIB

#define ADE7978_STATUS1_ZXTOIB NO_OS_BIT(7)

◆ ADE7978_STATUS1_ZXTOIC

#define ADE7978_STATUS1_ZXTOIC NO_OS_BIT(8)

◆ ADE7978_STATUS1_ZXTOVA

#define ADE7978_STATUS1_ZXTOVA NO_OS_BIT(3)

◆ ADE7978_STATUS1_ZXTOVB

#define ADE7978_STATUS1_ZXTOVB NO_OS_BIT(4)

◆ ADE7978_STATUS1_ZXTOVC

#define ADE7978_STATUS1_ZXTOVC NO_OS_BIT(5)

◆ ADE7978_STATUS1_ZXVA

#define ADE7978_STATUS1_ZXVA NO_OS_BIT(9)

◆ ADE7978_STATUS1_ZXVB

#define ADE7978_STATUS1_ZXVB NO_OS_BIT(10)

◆ ADE7978_STATUS1_ZXVC

#define ADE7978_STATUS1_ZXVC NO_OS_BIT(11)

◆ ADE7978_SUM1SIGN

#define ADE7978_SUM1SIGN NO_OS_BIT(3)

◆ ADE7978_SUM2SIGN

#define ADE7978_SUM2SIGN NO_OS_BIT(7)

◆ ADE7978_SUM3SIGN

#define ADE7978_SUM3SIGN NO_OS_BIT(8)

◆ ADE7978_SWAP

#define ADE7978_SWAP NO_OS_BIT(3)

◆ ADE7978_SWRST

#define ADE7978_SWRST NO_OS_BIT(7)

◆ ADE7978_TERMSEL1_0

#define ADE7978_TERMSEL1_0 NO_OS_BIT(0)

◆ ADE7978_TERMSEL1_1

#define ADE7978_TERMSEL1_1 NO_OS_BIT(1)

◆ ADE7978_TERMSEL1_2

#define ADE7978_TERMSEL1_2 NO_OS_BIT(2)

◆ ADE7978_TERMSEL2_0

#define ADE7978_TERMSEL2_0 NO_OS_BIT(3)

◆ ADE7978_TERMSEL2_1

#define ADE7978_TERMSEL2_1 NO_OS_BIT(4)

◆ ADE7978_TERMSEL2_2

#define ADE7978_TERMSEL2_2 NO_OS_BIT(5)

◆ ADE7978_TERMSEL3_0

#define ADE7978_TERMSEL3_0 NO_OS_BIT(6)

◆ ADE7978_TERMSEL3_1

#define ADE7978_TERMSEL3_1 NO_OS_BIT(7)

◆ ADE7978_TERMSEL3_2

#define ADE7978_TERMSEL3_2 NO_OS_BIT(8)

◆ ADE7978_VA2_EN

#define ADE7978_VA2_EN NO_OS_BIT(0)

◆ ADE7978_VANLPHASE0

#define ADE7978_VANLPHASE0 NO_OS_BIT(6)

◆ ADE7978_VANLPHASE1

#define ADE7978_VANLPHASE1 NO_OS_BIT(7)

◆ ADE7978_VANLPHASE2

#define ADE7978_VANLPHASE2 NO_OS_BIT(8)

◆ ADE7978_VARACC

#define ADE7978_VARACC NO_OS_GENMASK(3, 2)

◆ ADE7978_VB2_EN

#define ADE7978_VB2_EN NO_OS_BIT(1)

◆ ADE7978_VC2_EN

#define ADE7978_VC2_EN NO_OS_BIT(2)

◆ ADE7978_VN2_EN

#define ADE7978_VN2_EN NO_OS_BIT(3)

◆ ADE7978_VNOMAEN

#define ADE7978_VNOMAEN NO_OS_BIT(11)

◆ ADE7978_VNOMBEN

#define ADE7978_VNOMBEN NO_OS_BIT(12)

◆ ADE7978_VNOMCEN

#define ADE7978_VNOMCEN NO_OS_BIT(13)

◆ ADE7978_VPEAKVAL

#define ADE7978_VPEAKVAL NO_OS_GENMASK(23, 0)

◆ ADE7978_VPPHASE0

#define ADE7978_VPPHASE0 NO_OS_BIT(24)

◆ ADE7978_VPPHASE1

#define ADE7978_VPPHASE1 NO_OS_BIT(25)

◆ ADE7978_VPPHASE2

#define ADE7978_VPPHASE2 NO_OS_BIT(26)

◆ ADE7978_VSPHASE0

#define ADE7978_VSPHASE0 NO_OS_BIT(12)

◆ ADE7978_VSPHASE1

#define ADE7978_VSPHASE1 NO_OS_BIT(13)

◆ ADE7978_VSPHASE2

#define ADE7978_VSPHASE2 NO_OS_BIT(14)

◆ ADE7978_VTOIA

#define ADE7978_VTOIA NO_OS_GENMASK(9, 8)

◆ ADE7978_VTOIB

#define ADE7978_VTOIB NO_OS_GENMASK(11, 10)

◆ ADE7978_VTOIC

#define ADE7978_VTOIC NO_OS_GENMASK(13, 12)

◆ ADE7978_WATTACC

#define ADE7978_WATTACC NO_OS_GENMASK(1, 0)

◆ ADE7978_WAVE_FS_CODES

#define ADE7978_WAVE_FS_CODES 5320000

◆ ADE7978_ZX_DREADY

#define ADE7978_ZX_DREADY NO_OS_GENMASK(1, 0)

◆ ADE7978_ZXSEL0

#define ADE7978_ZXSEL0 NO_OS_BIT(3)

◆ ADE7978_ZXSEL1

#define ADE7978_ZXSEL1 NO_OS_BIT(4)

◆ ADE7978_ZXSEL2

#define ADE7978_ZXSEL2 NO_OS_BIT(5)

◆ DISABLE

#define DISABLE 0x0000

◆ ENABLE

#define ENABLE 0x0001

◆ IS_16BITS_REG

#define IS_16BITS_REG ( x )

Value:

        ((x >= ADE7978_REG_PHSTATUS && x <= ADE7978_REG_CONFIG) \
        || (x >= ADE7978_REG_APF && x <= ADE7978_REG_LAST_RWDATA16) \
        || (x == ADE7978_REG_RUN))

◆ IS_8BITS_REG

#define IS_8BITS_REG ( x )

Value:

((x >= ADE7978_REG_MMODE && x <= ADE7978_REG_LAST_RWDATA8) \

|| (x >= ADE7978_REG_CONFIG2 && x <= ADE7978_SET_SPI_ADDR))

ADE7978_REG_CONFIG2

#define ADE7978_REG_CONFIG2

Definition ade7978.h:210

ADE7978_REG_MMODE

#define ADE7978_REG_MMODE

Definition ade7978.h:185

ADE7978_SET_SPI_ADDR

#define ADE7978_SET_SPI_ADDR

Definition ade7978.h:447

ADE7978_REG_LAST_RWDATA8

#define ADE7978_REG_LAST_RWDATA8

Definition ade7978.h:198

Enumeration Type Documentation

◆ ade7978_cfxsel_e

enum ade7978_cfxsel_e

ADE7978 These bits indicate the value the CFx frequency is proportional to.

Enumerator
ADE7978_CFXSEL_0
ADE7978_CFXSEL_1
ADE7978_CFXSEL_2
ADE7978_CFXSEL_3
ADE7978_CFXSEL_4

◆ ade7978_consel_e

enum ade7978_consel_e

ADE7978 These bits select the inputs to the energy accumulation registers. IA’, IB’, and IC’ are IA, IB, and IC shifted respectively by −90°

Enumerator
ADE7978_CONSEL_3P_3W
ADE7978_CONSEL_3P_3W_DELTA
ADE7978_CONSEL_3P_4W_DELTA

◆ ade7978_freq_sel_e

enum ade7978_freq_sel_e

ADE7978 Freq value.

Enumerator
ADE7978_SELFREQ_50
ADE7978_SELFREQ_60

◆ ade7978_hxfer_e

enum ade7978_hxfer_e

ADE7978 These bits select the data transmitted on HSDC.

Enumerator
ADE7978_HXFER_16
ADE7978_HXFER_7
ADE7978_HXFER_9
ADE7978_HXFER_RESERVED

◆ ade7978_phase

enum ade7978_phase

ADE7978 available phases.

Enumerator
ADE7978_PHASE_A
ADE7978_PHASE_B
ADE7978_PHASE_C

◆ ade7978_varacc_e

enum ade7978_varacc_e

ADE7978 These bits decide the accumulation mode of funamental reactive powers.

Enumerator
ADE7978_VARACC_SIGNED_ACC
ADE7978_VARACC_RESERVED
ADE7978_VARACC_SIGN_WATTACC
ADE7978_VARACC_ABSOLUTE_ACC

◆ ade7978_vtoia_e

enum ade7978_vtoia_e

ADE7978 These bits decide what phase voltage is considered together with Phase A current in the power path.

Enumerator
ADE7978_VTOIA_A
ADE7978_VTOIA_B
ADE7978_VTOIA_C

◆ ade7978_vtoib_e

enum ade7978_vtoib_e

ADE7978 These bits decide what phase voltage is considered together with Phase B current in the power path.

Enumerator
ADE7978_VTOIB_B
ADE7978_VTOIB_C
ADE7978_VTOIB_A

◆ ade7978_vtoic_e

enum ade7978_vtoic_e

ADE7978 These bits decide what phase voltage is considered together with Phase C current in the power path.

Enumerator
ADE7978_VTOIC_C
ADE7978_VTOIC_A
ADE7978_VTOIC_B

◆ ade7978_wattacc_e

enum ade7978_wattacc_e

ADE7978 These bits decide the accumulation mode of fundamental active powers.

Enumerator
ADE7978_WATTACC_SIGNED_ACC
ADE7978_WATTACC_POSITIVE_ACC
ADE7978_WATTACC_RESERVED
ADE7978_WATTACC_ABSOLUTE_ACC

◆ ade7978_zx_dready_e

enum ade7978_zx_dready_e

ADE7978 These bits manage the output signal at the ZX/DREADY pin.

Enumerator
ADE7978_DREADY_EN
ADE7978_ZX_PHASE_A
ADE7978_ZX_PHASE_B
ADE7978_ZX_PHASE_C

Function Documentation

◆ ade7978_get_int_status0()

int ade7978_get_int_status0	(	struct ade7978_dev *	dev,
		uint32_t	msk,
		uint8_t *	status )

Get interrupt indicator from STATUS0 register.

Parameters

dev	- The device structure.
msk	- Interrupt mask.
status	- Status indicator.

Returns: 0 in case of success, negative error code otherwise.

◆ ade7978_get_int_status1()

int ade7978_get_int_status1	(	struct ade7978_dev *	dev,
		uint32_t	msk,
		uint8_t *	status )

Get interrupt indicator from STATUS1 register.

Parameters

dev	- The device structure.
msk	- Interrupt mask.
status	- Status indicator.

Returns: 0 in case of success, negative error code otherwise.

◆ ade7978_init()

int ade7978_init	(	struct ade7978_dev **	device,
		struct ade7978_init_param	init_param )

Initialize the device.

Parameters

device	- The device structure.
init_param	- The structure that contains the device initial parameters.

Returns: 0 in case of success, negative error code otherwise.

◆ ade7978_read()

int ade7978_read	(	struct ade7978_dev *	dev,
		uint16_t	reg_addr,
		uint32_t *	reg_data )

Read device register.

Parameters

dev	- The device structure.
reg_addr	- The register address.
reg_data	- The data read from the register.

Returns: 0 in case of success, negative error code otherwise.

◆ ade7978_read_data_ph()

int ade7978_read_data_ph	(	struct ade7978_dev *	dev,
		enum ade7978_phase	phase )

Read the measurements for specific phase.

Parameters

dev	- The device structure.
phase	- ADE7978 Phase.

Returns: 0 in case of success, negative error code otherwise.

◆ ade7978_remove()

int ade7978_remove ( struct ade7978_dev * dev )

Remove the device and release resources.

Parameters

dev	- The device structure.

Returns: 0 in case of success, negative error code otherwise.

◆ ade7978_setup()

int ade7978_setup ( struct ade7978_dev * dev )

Setup the device.

Parameters

dev	- The device structure.

Returns: 0 in case of success, negative error code otherwise.

◆ ade7978_update_bits()

int ade7978_update_bits	(	struct ade7978_dev *	dev,
		uint16_t	reg_addr,
		uint32_t	mask,
		uint32_t	reg_data )

Update specific register bits.

Parameters

dev	- The device structure.
reg_addr	- The register address.
mask	- Specific bits mask.
reg_data	- The data to be written.

Returns: 0 in case of success, negative error code otherwise.

◆ ade7978_write()

int ade7978_write	(	struct ade7978_dev *	dev,
		uint16_t	reg_addr,
		uint32_t	reg_data )

Write device register.

Parameters

dev-	The device structure.
reg_addr	- The register address.
reg_data	- The data to be written.

Returns: 0 in case of success, negative error code otherwise.

Classes

Macros

Enumerations

Functions

Detailed Description

Macro Definition Documentation

◆ ADE7978_ADE7933_SWRST

◆ ADE7978_ANGLESEL

◆ ADE7978_AVARSIGN

◆ ADE7978_AWSIGN

◆ ADE7978_BVARSIGN

◆ ADE7978_BWSIGN

◆ ADE7978_CF1DIS

◆ ADE7978_CF1LATCH

◆ ADE7978_CF1SEL

◆ ADE7978_CF2DIS

◆ ADE7978_CF2LATCH

◆ ADE7978_CF2SEL

◆ ADE7978_CF3DIS

◆ ADE7978_CF3LATCH

◆ ADE7978_CF3SEL

◆ ADE7978_CHIP_ID

◆ ADE7978_CLKOUT_DIS

◆ ADE7978_CONSEL

◆ ADE7978_CVARSIGN

◆ ADE7978_CWSIGN

◆ ADE7978_DUMB_VAL

◆ ADE7978_FNLPHASE0

◆ ADE7978_FNLPHASE1

◆ ADE7978_FNLPHASE2

◆ ADE7978_FS_CURRENT

◆ ADE7978_FS_CURRENT_RMS

◆ ADE7978_FS_VOLTAGE

◆ ADE7978_FS_VOLTAGE_RMS

◆ ADE7978_HCLK

◆ ADE7978_HGAP

◆ ADE7978_HPFEN

◆ ADE7978_HSAPOL

◆ ADE7978_HSDCEN

◆ ADE7978_HSIZE

◆ ADE7978_HXFER

◆ ADE7978_I2C_LOCK

◆ ADE7978_INSEL

◆ ADE7978_IPEAKVAL

◆ ADE7978_IPPHASE0

◆ ADE7978_IPPHASE1

◆ ADE7978_IPPHASE2

◆ ADE7978_LPFSEL

◆ ADE7978_LVA

◆ ADE7978_LVAR

◆ ADE7978_LWATT

◆ ADE7978_MASK0_AEHF

◆ ADE7978_MASK0_CF1

◆ ADE7978_MASK0_CF2

◆ ADE7978_MASK0_CF3

◆ ADE7978_MASK0_DREADY

◆ ADE7978_MASK0_FAEHF

◆ ADE7978_MASK0_FREHF

◆ ADE7978_MASK0_HREADY

◆ ADE7978_MASK0_LENERGY

◆ ADE7978_MASK0_REHF

◆ ADE7978_MASK0_REVAPA

◆ ADE7978_MASK0_REVAPB

◆ ADE7978_MASK0_REVAPC

◆ ADE7978_MASK0_REVFRPA

◆ ADE7978_MASK0_REVFRPB

◆ ADE7978_MASK0_REVFRPC

◆ ADE7978_MASK0_REVPSUM1

◆ ADE7978_MASK0_REVPSUM2

◆ ADE7978_MASK0_REVPSUM3

◆ ADE7978_MASK0_VAEHF

◆ ADE7978_MASK1_CRC

◆ ADE7978_MASK1_FNLOAD

◆ ADE7978_MASK1_MISMTCH

◆ ADE7978_MASK1_NLOAD

◆ ADE7978_MASK1_OI

◆ ADE7978_MASK1_OV

◆ ADE7978_MASK1_PKI

◆ ADE7978_MASK1_PKV

◆ ADE7978_MASK1_RSTDONE