no-OS
Classes | Macros | Enumerations | Functions
ade9000.h File Reference

Header file of ADE9000 Driver. More...

#include <stdbool.h>
#include <stdint.h>
#include <string.h>
#include "no_os_util.h"
#include "no_os_spi.h"
Include dependency graph for ade9000.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct  ade9000_init_param
 ADE9000 Device initialization parameters. More...
 
struct  ade9000_dev
 ADE9000 Device structure. More...
 

Macros

#define ADE9000_SPI_READ   NO_OS_BIT(3)
 
#define ENABLE   0x0001
 
#define DISABLE   0x0000
 
#define ADE9000_REG_AIGAIN   0x0000
 
#define ADE9000_REG_AIGAIN0   0x0001
 
#define ADE9000_REG_AIGAIN1   0x0002
 
#define ADE9000_REG_AIGAIN2   0x0003
 
#define ADE9000_REG_AIGAIN3   0x0004
 
#define ADE9000_REG_AIGAIN4   0x0005
 
#define ADE9000_REG_APHCAL0   0x0006
 
#define ADE9000_REG_APHCAL1   0x0007
 
#define ADE9000_REG_APHCAL2   0x0008
 
#define ADE9000_REG_APHCAL3   0x0009
 
#define ADE9000_REG_APHCAL4   0x000A
 
#define ADE9000_REG_AVGAIN   0x000B
 
#define ADE9000_REG_AIRMSOS   0x000C
 
#define ADE9000_REG_AVRMSOS   0x000D
 
#define ADE9000_REG_APGAIN   0x000E
 
#define ADE9000_REG_AWATTOS   0x000F
 
#define ADE9000_REG_AVAROS   0x0010
 
#define ADE9000_REG_AFWATTOS   0x0011
 
#define ADE9000_REG_AFVAROS   0x0012
 
#define ADE9000_REG_AIFRMSOS   0x0013
 
#define ADE9000_REG_AVFRMSOS   0x0014
 
#define ADE9000_REG_AVRMSONEOS   0x0015
 
#define ADE9000_REG_AIRMSONEOS   0x0016
 
#define ADE9000_REG_AVRMS1012OS   0x0017
 
#define ADE9000_REG_AIRMS1012OS   0x0018
 
#define ADE9000_REG_BIGAIN   0x0020
 
#define ADE9000_REG_BIGAIN0   0x0021
 
#define ADE9000_REG_BIGAIN1   0x0022
 
#define ADE9000_REG_BIGAIN2   0x0023
 
#define ADE9000_REG_BIGAIN3   0x0024
 
#define ADE9000_REG_BIGAIN4   0x0025
 
#define ADE9000_REG_BPHCAL0   0x0026
 
#define ADE9000_REG_BPHCAL1   0x0027
 
#define ADE9000_REG_BPHCAL2   0x0028
 
#define ADE9000_REG_BPHCAL3   0x0029
 
#define ADE9000_REG_BPHCAL4   0x002A
 
#define ADE9000_REG_BVGAIN   0x002B
 
#define ADE9000_REG_BIRMSOS   0x002C
 
#define ADE9000_REG_BVRMSOS   0x002D
 
#define ADE9000_REG_BPGAIN   0x002E
 
#define ADE9000_REG_BWATTOS   0x002F
 
#define ADE9000_REG_BVAROS   0x0030
 
#define ADE9000_REG_BFWATTOS   0x0031
 
#define ADE9000_REG_BFVAROS   0x0032
 
#define ADE9000_REG_BIFRMSOS   0x0033
 
#define ADE9000_REG_BVFRMSOS   0x0034
 
#define ADE9000_REG_BVRMSONEOS   0x0035
 
#define ADE9000_REG_BIRMSONEOS   0x0036
 
#define ADE9000_REG_BVRMS1012OS   0x0037
 
#define ADE9000_REG_BIRMS1012OS   0x0038
 
#define ADE9000_REG_CIGAIN   0x0040
 
#define ADE9000_REG_CIGAIN0   0x0041
 
#define ADE9000_REG_CIGAIN1   0x0042
 
#define ADE9000_REG_CIGAIN2   0x0043
 
#define ADE9000_REG_CIGAIN3   0x0044
 
#define ADE9000_REG_CIGAIN4   0x0045
 
#define ADE9000_REG_CPHCAL0   0x0046
 
#define ADE9000_REG_CPHCAL1   0x0047
 
#define ADE9000_REG_CPHCAL2   0x0048
 
#define ADE9000_REG_CPHCAL3   0x0049
 
#define ADE9000_REG_CPHCAL4   0x004A
 
#define ADE9000_REG_CVGAIN   0x004B
 
#define ADE9000_REG_CIRMSOS   0x004C
 
#define ADE9000_REG_CVRMSOS   0x004D
 
#define ADE9000_REG_CPGAIN   0x004E
 
#define ADE9000_REG_CWATTOS   0x004F
 
#define ADE9000_REG_CVAROS   0x0050
 
#define ADE9000_REG_CFWATTOS   0x0051
 
#define ADE9000_REG_CFVAROS   0x0052
 
#define ADE9000_REG_CIFRMSOS   0x0053
 
#define ADE9000_REG_CVFRMSOS   0x0054
 
#define ADE9000_REG_CVRMSONEOS   0x0055
 
#define ADE9000_REG_CIRMSONEOS   0x0056
 
#define ADE9000_REG_CVRMS1012OS   0x0057
 
#define ADE9000_REG_CIRMS1012OS   0x0058
 
#define ADE9000_REG_CONFIG0   0x0060
 
#define ADE9000_REG_MTTHR_L0   0x0061
 
#define ADE9000_REG_MTTHR_L1   0x0062
 
#define ADE9000_REG_MTTHR_L2   0x0063
 
#define ADE9000_REG_MTTHR_L3   0x0064
 
#define ADE9000_REG_MTTHR_L4   0x0065
 
#define ADE9000_REG_MTTHR_H0   0x0066
 
#define ADE9000_REG_MTTHR_H1   0x0067
 
#define ADE9000_REG_MTTHR_H2   0x0068
 
#define ADE9000_REG_MTTHR_H3   0x0069
 
#define ADE9000_REG_MTTHR_H4   0x006A
 
#define ADE9000_REG_NIRMSOS   0x006B
 
#define ADE9000_REG_ISUMRMSOS   0x006C
 
#define ADE9000_REG_NIGAIN   0x006D
 
#define ADE9000_REG_NPHCAL   0x006E
 
#define ADE9000_REG_NIRMSONEOS   0x006F
 
#define ADE9000_REG_NIRMS1012OS   0x0070
 
#define ADE9000_REG_VNOM   0x0071
 
#define ADE9000_REG_DICOEFF   0x0072
 
#define ADE9000_REG_ISUMLVL   0x0073
 
#define ADE9000_REG_AI_PCF   0x020A
 
#define ADE9000_REG_AV_PCF   0x020B
 
#define ADE9000_REG_AIRMS   0x020C
 
#define ADE9000_REG_AVRMS   0x020D
 
#define ADE9000_REG_AIFRMS   0x020E
 
#define ADE9000_REG_AVFRMS   0x020F
 
#define ADE9000_REG_AWATT   0x0210
 
#define ADE9000_REG_AVAR   0x0211
 
#define ADE9000_REG_AVA   0x0212
 
#define ADE9000_REG_AFWATT   0x0213
 
#define ADE9000_REG_AFVAR   0x0214
 
#define ADE9000_REG_AFVA   0x0215
 
#define ADE9000_REG_APF   0x0216
 
#define ADE9000_REG_AVTHD   0x0217
 
#define ADE9000_REG_AITHD   0x0218
 
#define ADE9000_REG_AIRMSONE   0x0219
 
#define ADE9000_REG_AVRMSONE   0x021A
 
#define ADE9000_REG_AIRMS1012   0x021B
 
#define ADE9000_REG_AVRMS1012   0x021C
 
#define ADE9000_REG_AMTREGION   0x021D
 
#define ADE9000_REG_BI_PCF   0x022A
 
#define ADE9000_REG_BV_PCF   0x022B
 
#define ADE9000_REG_BIRMS   0x022C
 
#define ADE9000_REG_BVRMS   0x022D
 
#define ADE9000_REG_BIFRMS   0x022E
 
#define ADE9000_REG_BVFRMS   0x022F
 
#define ADE9000_REG_BWATT   0x0230
 
#define ADE9000_REG_BVAR   0x0231
 
#define ADE9000_REG_BVA   0x0232
 
#define ADE9000_REG_BFWATT   0x0233
 
#define ADE9000_REG_BFVAR   0x0234
 
#define ADE9000_REG_BFVA   0x0235
 
#define ADE9000_REG_BPF   0x0236
 
#define ADE9000_REG_BVTHD   0x0237
 
#define ADE9000_REG_BITHD   0x0238
 
#define ADE9000_REG_BIRMSONE   0x0239
 
#define ADE9000_REG_BVRMSONE   0x023A
 
#define ADE9000_REG_BIRMS1012   0x023B
 
#define ADE9000_REG_BVRMS1012   0x023C
 
#define ADE9000_REG_BMTREGION   0x023D
 
#define ADE9000_REG_CI_PCF   0x024A
 
#define ADE9000_REG_CV_PCF   0x024B
 
#define ADE9000_REG_CIRMS   0x024C
 
#define ADE9000_REG_CVRMS   0x024D
 
#define ADE9000_REG_CIFRMS   0x024E
 
#define ADE9000_REG_CVFRMS   0x024F
 
#define ADE9000_REG_CWATT   0x0250
 
#define ADE9000_REG_CVAR   0x0251
 
#define ADE9000_REG_CVA   0x0252
 
#define ADE9000_REG_CFWATT   0x0253
 
#define ADE9000_REG_CFVAR   0x0254
 
#define ADE9000_REG_CFVA   0x0255
 
#define ADE9000_REG_CPF   0x0256
 
#define ADE9000_REG_CVTHD   0x0257
 
#define ADE9000_REG_CITHD   0x0258
 
#define ADE9000_REG_CIRMSONE   0x0259
 
#define ADE9000_REG_CVRMSONE   0x025A
 
#define ADE9000_REG_CIRMS1012   0x025B
 
#define ADE9000_REG_CVRMS1012   0x025C
 
#define ADE9000_REG_CMTREGION   0x025D
 
#define ADE9000_REG_NI_PCF   0x0265
 
#define ADE9000_REG_NIRMS   0x0266
 
#define ADE9000_REG_NIRMSONE   0x0267
 
#define ADE9000_REG_NIRMS1012   0x0268
 
#define ADE9000_REG_ISUMRMS   0x0269
 
#define ADE9000_REG_VERSION2   0x026A
 
#define ADE9000_REG_AWATT_ACC   0x02E5
 
#define ADE9000_REG_AWATTHR_LO   0x02E6
 
#define ADE9000_REG_AWATTHR_HI   0x02E7
 
#define ADE9000_REG_AVAR_ACC   0x02EF
 
#define ADE9000_REG_AVARHR_LO   0x02F0
 
#define ADE9000_REG_AVARHR_HI   0x02F1
 
#define ADE9000_REG_AVA_ACC   0x02F9
 
#define ADE9000_REG_AVAHR_LO   0x02FA
 
#define ADE9000_REG_AVAHR_HI   0x02FB
 
#define ADE9000_REG_AFWATT_ACC   0x0303
 
#define ADE9000_REG_AFWATTHR_LO   0x0304
 
#define ADE9000_REG_AFWATTHR_HI   0x0305
 
#define ADE9000_REG_AFVAR_ACC   0x030D
 
#define ADE9000_REG_AFVARHR_LO   0x030E
 
#define ADE9000_REG_AFVARHR_HI   0x030F
 
#define ADE9000_REG_AFVA_ACC   0x0317
 
#define ADE9000_REG_AFVAHR_LO   0x0318
 
#define ADE9000_REG_AFVAHR_HI   0x0319
 
#define ADE9000_REG_BWATT_ACC   0x0321
 
#define ADE9000_REG_BWATTHR_LO   0x0322
 
#define ADE9000_REG_BWATTHR_HI   0x0323
 
#define ADE9000_REG_BVAR_ACC   0x032B
 
#define ADE9000_REG_BVARHR_LO   0x032C
 
#define ADE9000_REG_BVARHR_HI   0x032D
 
#define ADE9000_REG_BVA_ACC   0x0335
 
#define ADE9000_REG_BVAHR_LO   0x0336
 
#define ADE9000_REG_BVAHR_HI   0x0337
 
#define ADE9000_REG_BFWATT_ACC   0x033F
 
#define ADE9000_REG_BFWATTHR_LO   0x0340
 
#define ADE9000_REG_BFWATTHR_HI   0x0341
 
#define ADE9000_REG_BFVAR_ACC   0x0349
 
#define ADE9000_REG_BFVARHR_LO   0x034A
 
#define ADE9000_REG_BFVARHR_HI   0x034B
 
#define ADE9000_REG_BFVA_ACC   0x0353
 
#define ADE9000_REG_BFVAHR_LO   0x0354
 
#define ADE9000_REG_BFVAHR_HI   0x0355
 
#define ADE9000_REG_CWATT_ACC   0x035D
 
#define ADE9000_REG_CWATTHR_LO   0x035E
 
#define ADE9000_REG_CWATTHR_HI   0x035F
 
#define ADE9000_REG_CVAR_ACC   0x0367
 
#define ADE9000_REG_CVARHR_LO   0x0368
 
#define ADE9000_REG_CVARHR_HI   0x0369
 
#define ADE9000_REG_CVA_ACC   0x0371
 
#define ADE9000_REG_CVAHR_LO   0x0372
 
#define ADE9000_REG_CVAHR_HI   0x0373
 
#define ADE9000_REG_CFWATT_ACC   0x037B
 
#define ADE9000_REG_CFWATTHR_LO   0x037C
 
#define ADE9000_REG_CFWATTHR_HI   0x037D
 
#define ADE9000_REG_CFVAR_ACC   0x0385
 
#define ADE9000_REG_CFVARHR_LO   0x0386
 
#define ADE9000_REG_CFVARHR_HI   0x0387
 
#define ADE9000_REG_CFVA_ACC   0x038F
 
#define ADE9000_REG_CFVAHR_LO   0x0390
 
#define ADE9000_REG_CFVAHR_HI   0x0391
 
#define ADE9000_REG_PWATT_ACC   0x0397
 
#define ADE9000_REG_NWATT_ACC   0x039B
 
#define ADE9000_REG_PVAR_ACC   0x039F
 
#define ADE9000_REG_NVAR_ACC   0x03A3
 
#define ADE9000_REG_IPEAK   0x0400
 
#define ADE9000_REG_VPEAK   0x0401
 
#define ADE9000_REG_STATUS0   0x0402
 
#define ADE9000_REG_STATUS1   0x0403
 
#define ADE9000_REG_EVENT_STATUS   0x0404
 
#define ADE9000_REG_MASK0   0x0405
 
#define ADE9000_REG_MASK1   0x0406
 
#define ADE9000_REG_EVENT_MASK   0x0407
 
#define ADE9000_REG_OILVL   0x0409
 
#define ADE9000_REG_OIA   0x040A
 
#define ADE9000_REG_OIB   0x040B
 
#define ADE9000_REG_OIC   0x040C
 
#define ADE9000_REG_OIN   0x040D
 
#define ADE9000_REG_USER_PERIOD   0x040E
 
#define ADE9000_REG_VLEVEL   0x040F
 
#define ADE9000_REG_DIP_LVL   0x410
 
#define ADE9000_REG_DIPA   0x411
 
#define ADE9000_REG_DIPB   0x412
 
#define ADE9000_REG_DIPC   0x413
 
#define ADE9000_REG_SWELL_LVL   0x414
 
#define ADE9000_REG_SWELLA   0x415
 
#define ADE9000_REG_SWELLB   0x416
 
#define ADE9000_REG_SWELLC   0x417
 
#define ADE9000_REG_APERIOD   0x0418
 
#define ADE9000_REG_BPERIOD   0x0419
 
#define ADE9000_REG_CPERIOD   0x041A
 
#define ADE9000_REG_COM_PERIOD   0x041B
 
#define ADE9000_REG_ACT_NL_LVL   0x041C
 
#define ADE9000_REG_REACT_NL_LVL   0x041D
 
#define ADE9000_REG_APP_NL_LVL   0x041E
 
#define ADE9000_REG_PHNOLOAD   0x041F
 
#define ADE9000_REG_WTHR   0x0420
 
#define ADE9000_REG_VARTHR   0x0421
 
#define ADE9000_REG_VATHR   0x0422
 
#define ADE9000_REG_LAST_DATA_32   0x0423
 
#define ADE9000_REG_ADC_REDIRECT   0x0424
 
#define ADE9000_REG_CF_LCFG   0x0425
 
#define ADE9000_REG_PART_ID   0x0472
 
#define ADE9000_REG_TEMP_TRIM   0x0474
 
#define ADE9000_REG_RUN   0x0480
 
#define ADE9000_REG_CONFIG1   0x0481
 
#define ADE9000_REG_ANGL_VA_VB   0x0482
 
#define ADE9000_REG_ANGL_VB_VC   0x0483
 
#define ADE9000_REG_ANGL_VA_VC   0x0484
 
#define ADE9000_REG_ANGL_VB_IA   0x0485
 
#define ADE9000_REG_ANGL_VB_IB   0x0486
 
#define ADE9000_REG_ANGL_VC_IC   0x0487
 
#define ADE9000_REG_ANGL_IA_IB   0x0488
 
#define ADE9000_REG_ANGL_IB_IC   0x0489
 
#define ADE9000_REG_ANGL_IA_IC   0x048A
 
#define ADE9000_REG_DIP_CYC   0x048B
 
#define ADE9000_REG_SWELL_CYC   0x048C
 
#define ADE9000_REG_OISTATUS   0x048F
 
#define ADE9000_REG_CFMODE   0x0490
 
#define ADE9000_REG_COMPMODE   0x0491
 
#define ADE9000_REG_ACCMODE   0x0492
 
#define ADE9000_REG_CONFIG3   0x0493
 
#define ADE9000_REG_CF1DEN   0x0494
 
#define ADE9000_REG_CF2DEN   0x0495
 
#define ADE9000_REG_CF3DEN   0x0496
 
#define ADE9000_REG_CF4DEN   0x0497
 
#define ADE9000_REG_ZXTOUT   0x0498
 
#define ADE9000_REG_ZXTHRSH   0x0499
 
#define ADE9000_REG_ZX_LP_SEL   0x049A
 
#define ADE9000_REG_SEQ_CYC   0x049C
 
#define ADE9000_REG_PHSIGN   0x049D
 
#define ADE9000_REG_WFB_CFG   0x04A0
 
#define ADE9000_REG_WFB_PG_IRQEN   0x04A1
 
#define ADE9000_REG_WFB_TRG_CFG   0x04A2
 
#define ADE9000_REG_WFB_TRG_STAT   0x04A3
 
#define ADE9000_REG_CONFIG5   0x04A4
 
#define ADE9000_REG_CRC_RSLT   0x04A8
 
#define ADE9000_REG_CRC_SPI   0x04A9
 
#define ADE9000_REG_LAST_DATA_16   0x04AC
 
#define ADE9000_REG_LAST_CMD   0x04AE
 
#define ADE9000_REG_CONFIG2   0x04AF
 
#define ADE9000_REG_EP_CFG   0x04B0
 
#define ADE9000_REG_PWR_TIME   0x04B1
 
#define ADE9000_REG_EGY_TIME   0x04B2
 
#define ADE9000_REG_CRC_FORCE   0x04B4
 
#define ADE9000_REG_CRC_OPTEN   0x04B5
 
#define ADE9000_REG_TEMP_CFG   0x04B6
 
#define ADE9000_REG_TEMP_RSLT   0x04B7
 
#define ADE9000_REG_PGA_GAIN   0x04B9
 
#define ADE9000_REG_CHNL_DIS   0x04BA
 
#define ADE9000_REG_WR_LOCK   0x04BF
 
#define ADE9000_REG_VAR_DIS   0x04E0
 
#define ADE9000_REG_RESERVED1   0x04F0
 
#define ADE9000_REG_VERSION   0x04FE
 
#define ADE9000_REG_AI_SINC_DAT   0x0500
 
#define ADE9000_REG_AV_SINC_DAT   0x0501
 
#define ADE9000_REG_BI_SINC_DAT   0x0502
 
#define ADE9000_REG_BV_SINC_DAT   0x0503
 
#define ADE9000_REG_CI_SINC_DAT   0x0504
 
#define ADE9000_REG_CV_SINC_DAT   0x0505
 
#define ADE9000_REG_NI_SINC_DAT   0x0506
 
#define ADE9000_REG_AI_LPF_DAT   0x0510
 
#define ADE9000_REG_AV_LPF_DAT   0x0511
 
#define ADE9000_REG_BI_LPF_DAT   0x0512
 
#define ADE9000_REG_BV_LPF_DAT   0x0513
 
#define ADE9000_REG_CI_LPF_DAT   0x0514
 
#define ADE9000_REG_CV_LPF_DAT   0x0515
 
#define ADE9000_REG_NI_LPF_DAT   0x0516
 
#define ADE9000_REG_AV_PCF_1   0x0600
 
#define ADE9000_REG_BV_PCF_1   0x0601
 
#define ADE9000_REG_CV_PCF_1   0x0602
 
#define ADE9000_REG_NI_PCF_1   0x0603
 
#define ADE9000_REG_AI_PCF_1   0x0604
 
#define ADE9000_REG_BI_PCF_1   0x0605
 
#define ADE9000_REG_CI_PCF_1   0x0606
 
#define ADE9000_REG_AIRMS_1   0x0607
 
#define ADE9000_REG_BIRMS_1   0x0608
 
#define ADE9000_REG_CIRMS_1   0x0609
 
#define ADE9000_REG_AVRMS_1   0x060A
 
#define ADE9000_REG_BVRMS_1   0x060B
 
#define ADE9000_REG_CVRMS_1   0x060C
 
#define ADE9000_REG_NIRMS_1   0x060D
 
#define ADE9000_REG_AWATT_1   0x060E
 
#define ADE9000_REG_BWATT_1   0x060F
 
#define ADE9000_REG_CWATT_1   0x0610
 
#define ADE9000_REG_AVA_1   0x0611
 
#define ADE9000_REG_BVA_1   0x0612
 
#define ADE9000_REG_CVA_1   0x0613
 
#define ADE9000_REG_AVAR_1   0x0614
 
#define ADE9000_REG_BVAR_1   0x0615
 
#define ADE9000_REG_CVAR_1   0x0616
 
#define ADE9000_REG_AFVAR_1   0x0617
 
#define ADE9000_REG_BFVAR_1   0x0618
 
#define ADE9000_REG_CFVAR_1   0x0619
 
#define ADE9000_REG_APF_1   0x061A
 
#define ADE9000_REG_BPF_1   0x061B
 
#define ADE9000_REG_CPF_1   0x061C
 
#define ADE9000_REG_AVTHD_1   0x061D
 
#define ADE9000_REG_BVTHD_1   0x061E
 
#define ADE9000_REG_CVTHD_1   0x061F
 
#define ADE9000_REG_AITHD_1   0x0620
 
#define ADE9000_REG_BITHD_1   0x0621
 
#define ADE9000_REG_CITHD_1   0x0622
 
#define ADE9000_REG_AFWATT_1   0x0623
 
#define ADE9000_REG_BFWATT_1   0x0624
 
#define ADE9000_REG_CFWATT_1   0x0625
 
#define ADE9000_REG_AFVA_1   0x0626
 
#define ADE9000_REG_BFVA_1   0x0627
 
#define ADE9000_REG_CFVA_1   0x0628
 
#define ADE9000_REG_AFIRMS_1   0x0629
 
#define ADE9000_REG_BFIRMS_1   0x062A
 
#define ADE9000_REG_CFIRMS_1   0x062B
 
#define ADE9000_REG_AFVRMS_1   0x062C
 
#define ADE9000_REG_BFVRMS_1   0x062D
 
#define ADE9000_REG_CFVRMS_1   0x062E
 
#define ADE9000_REG_AIRMSONE_1   0x062F
 
#define ADE9000_REG_BIRMSONE_1   0x0630
 
#define ADE9000_REG_CIRMSONE_1   0x0631
 
#define ADE9000_REG_AVRMSONE_1   0x0622
 
#define ADE9000_REG_BVRMSONE_1   0x0633
 
#define ADE9000_REG_CVRMSONE_1   0x0634
 
#define ADE9000_REG_NIRSONE_1   0x0635
 
#define ADE9000_REG_AIRMS1012_1   0x0636
 
#define ADE9000_REG_BIRMS1012_1   0x0637
 
#define ADE9000_REG_CIRMS1012_1   0x0638
 
#define ADE9000_REG_AVRMS1012_1   0x0639
 
#define ADE9000_REG_BVRMS1012_1   0x063A
 
#define ADE9000_REG_CVRMS1012_1   0x063B
 
#define ADE9000_REG_NIRMS1012_1   0x063C
 
#define ADE9000_REG_AV_PCF_2   0x0680
 
#define ADE9000_REG_AI_PCF_2   0x0681
 
#define ADE9000_REG_AIRMS_2   0x0682
 
#define ADE9000_REG_AVRMS_2   0x0683
 
#define ADE9000_REG_AWATT_2   0x0684
 
#define ADE9000_REG_AVA_2   0x0685
 
#define ADE9000_REG_AVAR_2   0x0686
 
#define ADE9000_REG_AFVAR_2   0x0687
 
#define ADE9000_REG_APF_2   0x0688
 
#define ADE9000_REG_AVTHD_2   0x0689
 
#define ADE9000_REG_AITHD_2   0x068A
 
#define ADE9000_REG_AFWATT_2   0x068B
 
#define ADE9000_REG_AFVA_2   0x068C
 
#define ADE9000_REG_AFIRMS_2   0x068D
 
#define ADE9000_REG_AFVRMS_2   0x068E
 
#define ADE9000_REG_AIRMSONE_2   0x068F
 
#define ADE9000_REG_AVRMSONE_2   0x0690
 
#define ADE9000_REG_AIRMS1012_2   0x0691
 
#define ADE9000_REG_AVRMS1012_2   0x0692
 
#define ADE9000_REG_BV_PCF_2   0x0693
 
#define ADE9000_REG_BI_PCF_2   0x0694
 
#define ADE9000_REG_BIRMS_2   0x0695
 
#define ADE9000_REG_BVRMS_2   0x0696
 
#define ADE9000_REG_BWATT_2   0x0697
 
#define ADE9000_REG_BVA_2   0x0698
 
#define ADE9000_REG_BVAR_2   0x0699
 
#define ADE9000_REG_BFVAR_2   0x069A
 
#define ADE9000_REG_BPF_2   0x069B
 
#define ADE9000_REG_BVTHD_2   0x069C
 
#define ADE9000_REG_BITHD_2   0x069D
 
#define ADE9000_REG_BFWATT_2   0x069E
 
#define ADE9000_REG_BFVA_2   0x069F
 
#define ADE9000_REG_BFIRMS_2   0x06A0
 
#define ADE9000_REG_BFVRMS_2   0x06A1
 
#define ADE9000_REG_BIRMSONE_2   0x06A2
 
#define ADE9000_REG_BVRMSONE_2   0x06A3
 
#define ADE9000_REG_BIRMS1012_2   0x06A4
 
#define ADE9000_REG_BVRMS1012_2   0x06A5
 
#define ADE9000_REG_CV_PCF_2   0x06A6
 
#define ADE9000_REG_CI_PCF_2   0x06A7
 
#define ADE9000_REG_CIRMS_2   0x06A8
 
#define ADE9000_REG_CVRMS_2   0x06A9
 
#define ADE9000_REG_CWATT_2   0x06AA
 
#define ADE9000_REG_CVA_2   0x06AB
 
#define ADE9000_REG_CVAR_2   0x06AC
 
#define ADE9000_REG_CFVAR_2   0x06AD
 
#define ADE9000_REG_CPF_2   0x06AE
 
#define ADE9000_REG_CVTHD_2   0x06AF
 
#define ADE9000_REG_CITHD_2   0x06B0
 
#define ADE9000_REG_CFWATT_2   0x06B1
 
#define ADE9000_REG_CFVA_2   0x06B2
 
#define ADE9000_REG_CFIRMS_2   0x06B3
 
#define ADE9000_REG_CFVRMS_2   0x06B4
 
#define ADE9000_REG_CIRMSONE_2   0x06B5
 
#define ADE9000_REG_CVRMSONE_2   0x06B6
 
#define ADE9000_REG_CIRMS1012_2   0x06B7
 
#define ADE9000_REG_CVRMS1012_2   0x06B8
 
#define ADE9000_REG_NI_PCF_2   0x06B9
 
#define ADE9000_REG_NIRMS_2   0x06BA
 
#define ADE9000_REG_NIRMSONE_2   0x06BB
 
#define ADE9000_REG_NIRMS1012_2   0x06BC
 
#define ADE9000_DISRPLPF   NO_OS_BIT(13)
 
#define ADE9000_DISAPLPF   NO_OS_BIT(12)
 
#define ADE9000_ININTEN   NO_OS_BIT(11)
 
#define ADE9000_VNOMC_EN   NO_OS_BIT(10)
 
#define ADE9000_VNOMB_EN   NO_OS_BIT(9)
 
#define ADE9000_VNOMA_EN   NO_OS_BIT(8)
 
#define ADE9000_RMS_SRC_SEL   NO_OS_BIT(7)
 
#define ADE9000_ZX_SRC_SEL   NO_OS_BIT(6)
 
#define ADE9000_INTEN   NO_OS_BIT(5)
 
#define ADE9000_MTEN   NO_OS_BIT(4)
 
#define ADE9000_HPFDIS   NO_OS_BIT(3)
 
#define ADE9000_ISUM_CFG   NO_OS_GENMASK(1, 0)
 
#define ADE9000_AREGION   NO_OS_GENMASK(3, 0)
 
#define ADE9000_BREGION   NO_OS_GENMASK(3, 0)
 
#define ADE9000_CREGION   NO_OS_GENMASK(3, 0)
 
#define ADE9000_IPPHASE   NO_OS_GENMASK(26, 24)
 
#define ADE9000_IPEAKVAL   NO_OS_GENMASK(23, 0)
 
#define ADE9000_VPPHASE   NO_OS_GENMASK(26, 24)
 
#define ADE9000_VPEAKVAL   NO_OS_GENMASK(23, 0)
 
#define ADE9000_STATUS0_TEMP_RDY   NO_OS_BIT(25)
 
#define ADE9000_STATUS0_MISMTCH   NO_OS_BIT(24)
 
#define ADE9000_STATUS0_COH_PAGE_RDY   NO_OS_BIT(23)
 
#define ADE9000_STATUS0_WFB_TRIG   NO_OS_BIT(22)
 
#define ADE9000_STATUS0_THD_PF_RDY   NO_OS_BIT(21)
 
#define ADE9000_STATUS0_RMS1012RDY   NO_OS_BIT(20)
 
#define ADE9000_STATUS0_RMSONERDY   NO_OS_BIT(19)
 
#define ADE9000_STATUS0_PWRRDY   NO_OS_BIT(18)
 
#define ADE9000_STATUS0_PAGE_FULL   NO_OS_BIT(17)
 
#define ADE9000_STATUS0_WFB_TRIG_IRQ   NO_OS_BIT(16)
 
#define ADE9000_STATUS0_DREADY   NO_OS_BIT(15)
 
#define ADE9000_STATUS0_CF4   NO_OS_BIT(14)
 
#define ADE9000_STATUS0_CF3   NO_OS_BIT(13)
 
#define ADE9000_STATUS0_CF2   NO_OS_BIT(12)
 
#define ADE9000_STATUS0_CF1   NO_OS_BIT(11)
 
#define ADE9000_STATUS0_REVPSUM4   NO_OS_BIT(10)
 
#define ADE9000_STATUS0_REVPSUM3   NO_OS_BIT(9)
 
#define ADE9000_STATUS0_REVPSUM2   NO_OS_BIT(8)
 
#define ADE9000_STATUS0_REVPSUM1   NO_OS_BIT(7)
 
#define ADE9000_STATUS0_REVRPC   NO_OS_BIT(6)
 
#define ADE9000_STATUS0_REVRPB   NO_OS_BIT(5)
 
#define ADE9000_STATUS0_REVRPA   NO_OS_BIT(4)
 
#define ADE9000_STATUS0_REVAPC   NO_OS_BIT(3)
 
#define ADE9000_STATUS0_REVAPB   NO_OS_BIT(2)
 
#define ADE9000_STATUS0_REVAPA   NO_OS_BIT(1)
 
#define ADE9000_STATUS0_EGYRDY   NO_OS_BIT(0)
 
#define ADE9000_STATUS1_ERROR3   NO_OS_BIT(31)
 
#define ADE9000_STATUS1_ERROR2   NO_OS_BIT(30)
 
#define ADE9000_STATUS1_ERROR1   NO_OS_BIT(29)
 
#define ADE9000_STATUS1_ERROR0   NO_OS_BIT(28)
 
#define ADE9000_STATUS1_CRC_DONE   NO_OS_BIT(27)
 
#define ADE9000_STATUS1_CRC_CHG   NO_OS_BIT(26)
 
#define ADE9000_STATUS1_DIPC   NO_OS_BIT(25)
 
#define ADE9000_STATUS1_DIPB   NO_OS_BIT(24)
 
#define ADE9000_STATUS1_DIPA   NO_OS_BIT(23)
 
#define ADE9000_STATUS1_SWELLC   NO_OS_BIT(22)
 
#define ADE9000_STATUS1_SWELLB   NO_OS_BIT(21)
 
#define ADE9000_STATUS1_SWELLA   NO_OS_BIT(20)
 
#define ADE9000_STATUS1_SEQERR   NO_OS_BIT(18)
 
#define ADE9000_STATUS1_OI   NO_OS_BIT(17)
 
#define ADE9000_STATUS1_RSTDONE   NO_OS_BIT(16)
 
#define ADE9000_STATUS1_ZXIC   NO_OS_BIT(15)
 
#define ADE9000_STATUS1_ZXIB   NO_OS_BIT(14)
 
#define ADE9000_STATUS1_ZXIA   NO_OS_BIT(13)
 
#define ADE9000_STATUS1_ZXCOMB   NO_OS_BIT(12)
 
#define ADE9000_STATUS1_ZXVC   NO_OS_BIT(11)
 
#define ADE9000_STATUS1_ZXVB   NO_OS_BIT(10)
 
#define ADE9000_STATUS1_ZXVA   NO_OS_BIT(9)
 
#define ADE9000_STATUS1_ZXTOVC   NO_OS_BIT(8)
 
#define ADE9000_STATUS1_ZXTOVB   NO_OS_BIT(7)
 
#define ADE9000_STATUS1_ZXTOVA   NO_OS_BIT(6)
 
#define ADE9000_STATUS1_VAFNOLOAD   NO_OS_BIT(5)
 
#define ADE9000_STATUS1_RFNOLOAD   NO_OS_BIT(4)
 
#define ADE9000_STATUS1_AFNOLOAD   NO_OS_BIT(3)
 
#define ADE9000_STATUS1_VANLOAD   NO_OS_BIT(2)
 
#define ADE9000_STATUS1_RNLOAD   NO_OS_BIT(1)
 
#define ADE9000_STATUS1_ANLOAD   NO_OS_BIT(0)
 
#define ADE9000_EVENT_DREADY   NO_OS_BIT(16)
 
#define ADE9000_EVENT_VAFNOLOAD   NO_OS_BIT(15)
 
#define ADE9000_EVENT_RFNOLOAD   NO_OS_BIT(14)
 
#define ADE9000_EVENT_AFNOLOAD   NO_OS_BIT(13)
 
#define ADE9000_EVENT_VANLOAD   NO_OS_BIT(12)
 
#define ADE9000_EVENT_RNLOAD   NO_OS_BIT(11)
 
#define ADE9000_EVENT_ANLOAD   NO_OS_BIT(10)
 
#define ADE9000_EVENT_REVPSUM4   NO_OS_BIT(9)
 
#define ADE9000_EVENT_REVPSUM3   NO_OS_BIT(8)
 
#define ADE9000_EVENT_REVPSUM2   NO_OS_BIT(7)
 
#define ADE9000_EVENT_REVPSUM1   NO_OS_BIT(6)
 
#define ADE9000_EVENT_SWELLC   NO_OS_BIT(5)
 
#define ADE9000_EVENT_SWELLB   NO_OS_BIT(4)
 
#define ADE9000_EVENT_SWELLA   NO_OS_BIT(3)
 
#define ADE9000_EVENT_DIPC   NO_OS_BIT(2)
 
#define ADE9000_EVENT_DIPB   NO_OS_BIT(1)
 
#define ADE9000_EVENT_DIPA   NO_OS_BIT(0)
 
#define ADE9000_MASK0_TEMP_RDY   NO_OS_BIT(25)
 
#define ADE9000_MASK0_MISMTCH   NO_OS_BIT(24)
 
#define ADE9000_MASK0_COH_WFB_FULL   NO_OS_BIT(23)
 
#define ADE9000_MASK0_WFB_TRIG   NO_OS_BIT(22)
 
#define ADE9000_MASK0_THD_PF_RDY   NO_OS_BIT(21)
 
#define ADE9000_MASK0_RMS1012RDY   NO_OS_BIT(20)
 
#define ADE9000_MASK0_RMSONERDY   NO_OS_BIT(19)
 
#define ADE9000_MASK0_PWRRDY   NO_OS_BIT(18)
 
#define ADE9000_MASK0_PAGE_FULL   NO_OS_BIT(17)
 
#define ADE9000_MASK0_WFB_TRIG_IRQ   NO_OS_BIT(16)
 
#define ADE9000_MASK0_DREADY   NO_OS_BIT(15)
 
#define ADE9000_MASK0_CF4   NO_OS_BIT(14)
 
#define ADE9000_MASK0_CF3   NO_OS_BIT(13)
 
#define ADE9000_MASK0_CF2   NO_OS_BIT(12)
 
#define ADE9000_MASK0_CF1   NO_OS_BIT(11)
 
#define ADE9000_MASK0_REVPSUM4   NO_OS_BIT(10)
 
#define ADE9000_MASK0_REVPSUM3   NO_OS_BIT(9)
 
#define ADE9000_MASK0_REVPSUM2   NO_OS_BIT(8)
 
#define ADE9000_MASK0_REVPSUM1   NO_OS_BIT(7)
 
#define ADE9000_MASK0_REVRPC   NO_OS_BIT(6)
 
#define ADE9000_MASK0_REVRPB   NO_OS_BIT(5)
 
#define ADE9000_MASK0_REVRPA   NO_OS_BIT(4)
 
#define ADE9000_MASK0_REVAPC   NO_OS_BIT(3)
 
#define ADE9000_MASK0_REVAPB   NO_OS_BIT(2)
 
#define ADE9000_MASK0_REVAPA   NO_OS_BIT(1)
 
#define ADE9000_MASK0_EGYRDY   NO_OS_BIT(0)
 
#define ADE9000_MASK1_ERROR3   NO_OS_BIT(31)
 
#define ADE9000_MASK1_ERROR2   NO_OS_BIT(30)
 
#define ADE9000_MASK1_ERROR1   NO_OS_BIT(29)
 
#define ADE9000_MASK1_ERROR0   NO_OS_BIT(28)
 
#define ADE9000_MASK1_CRC_DONE   NO_OS_BIT(27)
 
#define ADE9000_MASK1_CRC_CHG   NO_OS_BIT(26)
 
#define ADE9000_MASK1_DIPC   NO_OS_BIT(25)
 
#define ADE9000_MASK1_DIPB   NO_OS_BIT(24)
 
#define ADE9000_MASK1_DIPA   NO_OS_BIT(23)
 
#define ADE9000_MASK1_SWELLC   NO_OS_BIT(22)
 
#define ADE9000_MASK1_SWELLB   NO_OS_BIT(21)
 
#define ADE9000_MASK1_SWELLA   NO_OS_BIT(20)
 
#define ADE9000_MASK1_SEQERR   NO_OS_BIT(18)
 
#define ADE9000_MASK1_OI   NO_OS_BIT(17)
 
#define ADE9000_MASK1_ZXIC   NO_OS_BIT(15)
 
#define ADE9000_MASK1_ZXIB   NO_OS_BIT(14)
 
#define ADE9000_MASK1_ZXIA   NO_OS_BIT(13)
 
#define ADE9000_MASK1_ZXCOMB   NO_OS_BIT(12)
 
#define ADE9000_MASK1_ZXVC   NO_OS_BIT(11)
 
#define ADE9000_MASK1_ZXVB   NO_OS_BIT(10)
 
#define ADE9000_MASK1_ZXVA   NO_OS_BIT(9)
 
#define ADE9000_MASK1_ZXTOVC   NO_OS_BIT(8)
 
#define ADE9000_MASK1_ZXTOVB   NO_OS_BIT(7)
 
#define ADE9000_MASK1_ZXTOVA   NO_OS_BIT(6)
 
#define ADE9000_MASK1_VAFNOLOAD   NO_OS_BIT(5)
 
#define ADE9000_MASK1_RFNOLOAD   NO_OS_BIT(4)
 
#define ADE9000_MASK1_AFNOLOAD   NO_OS_BIT(3)
 
#define ADE9000_MASK1_VANLOAD   NO_OS_BIT(2)
 
#define ADE9000_MASK1_RNLOAD   NO_OS_BIT(1)
 
#define ADE9000_MASK1_ANLOAD   NO_OS_BIT(0)
 
#define ADE9000_EVENT_READY_MSK   NO_OS_BIT(16)
 
#define ADE9000_EVENT_VAFNOLOAD_MSK   NO_OS_BIT(15)
 
#define ADE9000_EVENT_RFNOLOAD_MSK   NO_OS_BIT(14)
 
#define ADE9000_EVENT_AFNOLOAD_MSK   NO_OS_BIT(13)
 
#define ADE9000_EVENT_VANLOAD_MSK   NO_OS_BIT(12)
 
#define ADE9000_EVENT_RNLOAD_MSK   NO_OS_BIT(11)
 
#define ADE9000_EVENT_ANLOAD_MSK   NO_OS_BIT(10)
 
#define ADE9000_EVENT_REVPSUM4_MSK   NO_OS_BIT(9)
 
#define ADE9000_EVENT_REVPSUM3_MSK   NO_OS_BIT(8)
 
#define ADE9000_EVENT_REVPSUM2_MSK   NO_OS_BIT(7)
 
#define ADE9000_EVENT_REVPSUM1_MSK   NO_OS_BIT(6)
 
#define ADE9000_EVENT_SWELLCEN   NO_OS_BIT(5)
 
#define ADE9000_EVENT_SWELLBEN   NO_OS_BIT(4)
 
#define ADE9000_EVENT_SWELLAEN   NO_OS_BIT(3)
 
#define ADE9000_EVENT_DIPCEN   NO_OS_BIT(2)
 
#define ADE9000_EVENT_DIPBEN   NO_OS_BIT(1)
 
#define ADE9000_EVENT_DIPAEN   NO_OS_BIT(0)
 
#define ADE9000_OILVL_VAL   NO_OS_GENMASK(23, 0)
 
#define ADE9000_OI_VAL   NO_OS_GENMASK(23, 0)
 
#define ADE9000_OIB_VAL   NO_OS_GENMASK(23, 0)
 
#define ADE9000_OIC_VAL   NO_OS_GENMASK(23, 0)
 
#define ADE9000_OIN_VAL   NO_OS_GENMASK(23, 0)
 
#define ADE9000_VLEVEL_VAL   NO_OS_GENMASK(23, 0)
 
#define ADE9000_DIPLVL   NO_OS_GENMASK(23, 0)
 
#define ADE9000_DIPA_VAL   NO_OS_GENMASK(23, 0)
 
#define ADE9000_DIPB_VAL   NO_OS_GENMASK(23, 0)
 
#define ADE9000_DIPC_VAL   NO_OS_GENMASK(23, 0)
 
#define ADE9000_SWELLLVL   NO_OS_GENMASK(23, 0)
 
#define ADE9000_SWELLA_VAL   NO_OS_GENMASK(23, 0)
 
#define ADE9000_SWELLB_VAL   NO_OS_GENMASK(23, 0)
 
#define ADE9000_SWELLC_VAL   NO_OS_GENMASK(23, 0)
 
#define ADE9000_CFVANL   NO_OS_BIT(17)
 
#define ADE9000_CFVARNL   NO_OS_BIT(16)
 
#define ADE9000_CFWATTNL   NO_OS_BIT(15)
 
#define ADE9000_CVANL   NO_OS_BIT(14)
 
#define ADE9000_CVARNL   NO_OS_BIT(13)
 
#define ADE9000_CWATTNL   NO_OS_BIT(12)
 
#define ADE9000_BFVANL   NO_OS_BIT(11)
 
#define ADE9000_BFVARNL   NO_OS_BIT(10)
 
#define ADE9000_BFWATTNL   NO_OS_BIT(9)
 
#define ADE9000_BVANL   NO_OS_BIT(8)
 
#define ADE9000_BVARNL   NO_OS_BIT(7)
 
#define ADE9000_BWATTNL   NO_OS_BIT(6)
 
#define ADE9000_AFVANL   NO_OS_BIT(5)
 
#define ADE9000_AFVARNL   NO_OS_BIT(4)
 
#define ADE9000_AFWATTNL   NO_OS_BIT(3)
 
#define ADE9000_AVANL   NO_OS_BIT(2)
 
#define ADE9000_AVARNL   NO_OS_BIT(1)
 
#define ADE9000_AWATTNL   NO_OS_BIT(0)
 
#define ADE9000_VC_DIN   NO_OS_GENMASK(20, 18)
 
#define ADE9000_VB_DIN   NO_OS_GENMASK(17, 15)
 
#define ADE9000_VA_DIN   NO_OS_GENMASK(14, 12)
 
#define ADE9000_IN_DIN   NO_OS_GENMASK(11, 9)
 
#define ADE9000_IC_DIN   NO_OS_GENMASK(8, 6)
 
#define ADE9000_IB_DIN   NO_OS_GENMASK(5, 3)
 
#define ADE9000_IA_DIN   NO_OS_GENMASK(2, 0)
 
#define ADE9000_CF4_LT   NO_OS_BIT(22)
 
#define ADE9000_CF3_LT   NO_OS_BIT(21)
 
#define ADE9000_CF2_LT   NO_OS_BIT(20)
 
#define ADE9000_CF1_LT   NO_OS_BIT(19)
 
#define ADE9000_CF_LTMR   NO_OS_GENMASK(18, 0)
 
#define ADE9000_ADE9000_ID   NO_OS_BIT(20)
 
#define ADE9000_TEMP_OFFSET   NO_OS_GENMASK(31, 16)
 
#define ADE9000_TEMP_GAIN   NO_OS_GENMASK(15, 0)
 
#define ADE9000_EXT_REF   NO_OS_BIT(15)
 
#define ADE9000_IRQ0_ON_IRQ1   NO_OS_BIT(12)
 
#define ADE9000_BURST_EN   NO_OS_BIT(11)
 
#define ADE9000_DIP_SWELL_IRQ_MODE   NO_OS_BIT(10)
 
#define ADE9000_PWR_SETTLE   NO_OS_GENMASK(9, 8)
 
#define ADE9000_CF_ACC_CLR   NO_OS_BIT(5)
 
#define ADE9000_CF4_CFG   NO_OS_GENMASK(3, 2)
 
#define ADE9000_CF3_CFG   NO_OS_BIT(1)
 
#define ADE9000_SWRST   NO_OS_BIT(0)
 
#define ADE9000_OIPHASE   NO_OS_GENMASK(3, 0)
 
#define ADE9000_CF4DIS   NO_OS_BIT(15)
 
#define ADE9000_CF3DIS   NO_OS_BIT(14)
 
#define ADE9000_CF2DIS   NO_OS_BIT(13)
 
#define ADE9000_CF1DIS   NO_OS_BIT(12)
 
#define ADE9000_CF4SEL   NO_OS_GENMASK(11, 9)
 
#define ADE9000_CF3SEL   NO_OS_GENMASK(8, 6)
 
#define ADE9000_CF2SEL   NO_OS_GENMASK(5, 3)
 
#define ADE9000_CF1SEL   NO_OS_GENMASK(2, 0)
 
#define ADE9000_TERMSEL4   NO_OS_GENMASK(11, 9)
 
#define ADE9000_TERMSEL3   NO_OS_GENMASK(8, 6)
 
#define ADE9000_TERMSEL2   NO_OS_GENMASK(5, 3)
 
#define ADE9000_TERMSEL1   NO_OS_GENMASK(2, 0)
 
#define ADE9000_SELFREQ   NO_OS_BIT(8)
 
#define ADE9000_ICONSEL   NO_OS_BIT(7)
 
#define ADE9000_VCONSEL   NO_OS_GENMASK(6, 4)
 
#define ADE9000_VARACC   NO_OS_GENMASK(3, 2)
 
#define ADE9000_WATTACC   NO_OS_GENMASK(1, 0)
 
#define ADE9000_OC_EN   NO_OS_GENMASK(15, 12)
 
#define ADE9000_PEAKSEL   NO_OS_GENMASK(4, 2)
 
#define ADE9000_LP_SEL   NO_OS_GENMASK(4, 3)
 
#define ADE9000_ZX_SEL   NO_OS_GENMASK(2, 1)
 
#define ADE9000_SUM4SIGN   NO_OS_BIT(9)
 
#define ADE9000_SUM3SIGN   NO_OS_BIT(8)
 
#define ADE9000_SUM2SIGN   NO_OS_BIT(7)
 
#define ADE9000_SUM1SIGN   NO_OS_BIT(6)
 
#define ADE9000_CVARSIGN   NO_OS_BIT(5)
 
#define ADE9000_CWSIGN   NO_OS_BIT(4)
 
#define ADE9000_BVARSIGN   NO_OS_BIT(3)
 
#define ADE9000_BWSIGN   NO_OS_BIT(2)
 
#define ADE9000_AVARSIGN   NO_OS_BIT(1)
 
#define ADE9000_AWSIGN   NO_OS_BIT(0)
 
#define ADE9000_WF_IN_EN   NO_OS_BIT(12)
 
#define ADE9000_WF_SRC   NO_OS_GENMASK(9, 8)
 
#define ADE9000_WF_MODE   NO_OS_BIT(7, 6)
 
#define ADE9000_WF_CAP_SEL   NO_OS_BIT(5)
 
#define ADE9000_WF_CAP_EN   NO_OS_BIT(4)
 
#define ADE9000_BURST_CHAN   NO_OS_GENMASK(3, 0)
 
#define ADE9000_TRIG_FORCE   NO_OS_BIT(10)
 
#define ADE9000_ZXCOMB   NO_OS_BIT(9)
 
#define ADE9000_ZXVC   NO_OS_BIT(8)
 
#define ADE9000_ZXVB   NO_OS_BIT(7)
 
#define ADE9000_ZXVA   NO_OS_BIT(6)
 
#define ADE9000_ZXIC   NO_OS_BIT(5)
 
#define ADE9000_ZXIB   NO_OS_BIT(4)
 
#define ADE9000_ZXIA   NO_OS_BIT(3)
 
#define ADE9000_OI   NO_OS_BIT(2)
 
#define ADE9000_SWELL   NO_OS_BIT(1)
 
#define ADE9000_DIP   NO_OS_BIT(0)
 
#define ADE9000_WFB_LAST_PAGE   NO_OS_GENMASK(15, 12)
 
#define ADE9000_WFB_TRIG_ADDR   NO_OS_GENMASK(10, 0)
 
#define ADE9000_UPERIOD_SEL   NO_OS_BIT(12)
 
#define ADE9000_HPF_CRN   NO_OS_GENMASK(11, 9)
 
#define ADE9000_NOLOAD_TMR   NO_OS_GENMASK(15, 13)
 
#define ADE9000_PWR_SIGN_SEL_1   NO_OS_BIT(7)
 
#define ADE9000_PWR_SIGN_SEL_0   NO_OS_BIT(6)
 
#define ADE9000_RD_RST_EN   NO_OS_BIT(5)
 
#define ADE9000_EGY_LD_ACCUM   NO_OS_BIT(4)
 
#define ADE9000_EGY_TMR_MODE   NO_OS_BIT(1)
 
#define ADE9000_EGY_PWR_EN   NO_OS_BIT(0)
 
#define ADE9000_FORCE_CRC_UPDATE   NO_OS_BIT(0)
 
#define ADE9000_CRC_WFB_TRG_CFG_EN   NO_OS_BIT(15)
 
#define ADE9000_CRC_WFB_PG_IRQEN   NO_OS_BIT(14)
 
#define ADE9000_CRC_WFB_CFG_EN   NO_OS_BIT(13)
 
#define ADE9000_CRC_SEQ_CYC_EN   NO_OS_BIT(12)
 
#define ADE9000_CRC_ZXLPSEL_EN   NO_OS_BIT(11)
 
#define ADE9000_CRC_ZXTOUT_EN   NO_OS_BIT(10)
 
#define ADE9000_CRC_APP_NL_LVL_EN   NO_OS_BIT(9)
 
#define ADE9000_CRC_REACT_NL_LVL_EN   NO_OS_BIT(8)
 
#define ADE9000_CRC_ACT_NL_LVL_EN   NO_OS_BIT(7)
 
#define ADE9000_CRC_SWELL_CYC_EN   NO_OS_BIT(6)
 
#define ADE9000_CRC_SWELL_LVL_EN   NO_OS_BIT(5)
 
#define ADE9000_CRC_DIP_CYC_EN   NO_OS_BIT(4)
 
#define ADE9000_CRC_DIP_LVL_EN   NO_OS_BIT(3)
 
#define ADE9000_CRC_EVENT_MASK_EN   NO_OS_BIT(2)
 
#define ADE9000_CRC_MASK1_EN   NO_OS_BIT(1)
 
#define ADE9000_CRC_MASK0_EN   NO_OS_BIT(0)
 
#define ADE9000_TEMP_START   NO_OS_BIT(3)
 
#define ADE9000_TEMP_EN   NO_OS_BIT(2)
 
#define ADE9000_TEMP_TIME   NO_OS_GENMASK(1, 0)
 
#define ADE9000_TEMP_RESULT   NO_OS_GENMASK(11, 0)
 
#define ADE9000_VC_GAIN   NO_OS_GENMASK(13, 12)
 
#define ADE9000_VB_GAIN   NO_OS_GENMASK(11, 10)
 
#define ADE9000_VA_GAIN   NO_OS_GENMASK(9, 8)
 
#define ADE9000_IN_GAIN   NO_OS_GENMASK(7, 6)
 
#define ADE9000_IC_GAIN   NO_OS_GENMASK(5, 4)
 
#define ADE9000_IB_GAIN   NO_OS_GENMASK(3, 2)
 
#define ADE9000_IA_GAIN   NO_OS_GENMASK(1, 0)
 
#define ADE9000_VC_DISADC   NO_OS_BIT(6)
 
#define ADE9000_VB_DISADC   NO_OS_BIT(5)
 
#define ADE9000_VA_DISADC   NO_OS_BIT(4)
 
#define ADE9000_IN_DISADC   NO_OS_BIT(3)
 
#define ADE9000_IC_DISADC   NO_OS_BIT(2)
 
#define ADE9000_IB_DISADC   NO_OS_BIT(1)
 
#define ADE9000_IA_DISADC   NO_OS_BIT(0)
 
#define ADE9000_VARDIS   NO_OS_BIT(0)
 
#define ADE9000_CHIP_ID   0x63
 
#define ADE9000_PGA_GAIN   0x0000
 
#define ADE9000_CONFIG0   0x00000000
 
#define ADE9000_CONFIG1   0x0002
 
#define ADE9000_CONFIG2   0x0C00
 
#define ADE9000_CONFIG3   0x0000
 
#define ADE9000_ACCMODE   0x0000
 
#define ADE9000_TEMP_CFG   0x000C
 
#define ADE9000_ZX_LP_SEL   0x001E
 
#define ADE9000_MASK0   0x00000001
 
#define ADE9000_MASK1   0x00000000
 
#define ADE9000_EVENT_MASK   0x00000000
 
#define ADE9000_VLEVEL   0x0022EA28
 
#define ADE9000_DICOEFF   0x00000000
 
#define ADE9000_RUN_ON   0x0001
 
#define ADE9000_EP_CFG   0x0011
 
#define ADE9000_EGY_TIME   0x1F3F
 
#define ADE9000_WFB_CFG   0x1000
 
#define WFB_ELEMENT_ARRAY_SIZE   512
 
#define ADE9000_RMS_FS_CODES   52702092
 
#define ADE9000_WATT_FS_CODES   20694066
 
#define ADE9000_RESAMPLED_FS_CODES   18196
 
#define ADE9000_PCF_FS_CODES   74532013
 
#define ADE9000_BURDEN_RES   10
 
#define ADE9000_CURRENT_TR_RATIO   3000
 
#define ADE9000_CURRENT_TR_FCN   (ADE9000_CURRENT_TR_RATIO / ADE9000_BURDEN_RES)
 
#define ADE9000_UP_RES   800000
 
#define ADE9000_DOWN_RES   1000
 
#define ADE9000_VOLTAGE_TR_FCN   ((ADE9000_DOWN_RES + ADE9000_UP_RES) / ADE9000_DOWN_RES)
 
#define ADE9000_FS_VOLTAGE   707
 

Enumerations

enum  ade9000_isum_cfg_e {
  ADE9000_ISUM_APROX_N,
  ADE9000_ISUM_DET_MISM_POS,
  ADE9000_ISUM_DET_MISM_NEG,
  ADE9000_ISUM_APROX_N_RMS
}
 ADE9000 isum calculation configuration. More...
 
enum  ade9000_aregion_sel_e {
  ADE9000_AIGAIN_APHCAL_0,
  ADE9000_AIGAIN_APHCAL_1,
  ADE9000_AIGAIN_APHCAL_2,
  ADE9000_AIGAIN_APHCAL_3,
  ADE9000_AIGAIN_APHCAL_4,
  ADE9000_AIGAIN_APHCAL_DISABLE = 15
}
 ADE9000 These bits indicate which AIGAINx and APHCALx is currently being used. More...
 
enum  ade9000_bregion_sel_e {
  ADE9000_BIGAIN_BPHCAL_0,
  ADE9000_BIGAIN_BPHCAL_1,
  ADE9000_BIGAIN_BPHCAL_2,
  ADE9000_BIGAIN_BPHCAL_3,
  ADE9000_BIGAIN_BPHCAL_4,
  ADE9000_BIGAIN_BPHCAL_DISABLE = 15
}
 ADE9000 These bits indicate which BIGAINx and BPHCALx is currently being used. More...
 
enum  ade9000_cregion_sel_e {
  ADE9000_CIGAIN_CPHCAL_0,
  ADE9000_CIGAIN_CPHCAL_1,
  ADE9000_CIGAIN_CPHCAL_2,
  ADE9000_CIGAIN_CPHCAL_3,
  ADE9000_CIGAIN_CPHCAL_4,
  ADE9000_CIGAIN_CPHCAL_DISABLE = 15
}
 ADE9000 These bits indicate which CIGAINx and CPHCALx is currently being used. More...
 
enum  ade9000_cf4_pin_out_cfg_e {
  ADE9000_CF4_D_F_CONV,
  ADE9000_CF4_D_F_CONV2,
  ADE9000_CF4_EVENT,
  ADE9000_CF4_DREADY
}
 ADE9000 These bits indicate which function to output on CF4 pin. More...
 
enum  ade9000_cf3_pin_out_cfg_e {
  ADE9000_CF3_D_F_CONV,
  ADE9000_CF3_ZX
}
 ADE9000 These bits indicate which function to output on CF3 pin. More...
 
enum  ade9000_cf4_sel_e {
  ADE9000_CF4_SEL_ACTIV_P,
  ADE9000_CF4_SEL_REACTIV_P,
  ADE9000_CF4_SEL_APPARENT_P,
  ADE9000_CF4_SEL_FUN_ACTIVE_P,
  ADE9000_CF4_SEL_FUN_REACTIVE_P,
  ADE9000_CF4_SEL_FUN_APPARENT_P,
  ADE9000_CF4_SEL_TOTAL_ACTIVE_P,
  ADE9000_CF4_SEL_TOTAL_ACTIVE_P_2
}
 ADE9000 Type of energy output on the CF4 pin. Configure TERMSEL4 in the COMPMODE register to select which phases are included. More...
 
enum  ade9000_freq_sel_e {
  ADE9000_SELFREQ_50,
  ADE9000_SELFREQ_60
}
 ADE9000 Freq value. More...
 
enum  ade9000_vconsel_e {
  ADE9000_4WIRE_WYE,
  ADE9000_3WIRE_DELTA,
  ADE9000_4WIRE_WYE_VA_VC,
  ADE9000_4WIRE_WYE_VA,
  ADE9000_3WIRE_DELTA_2
}
 ADE9000 3-wire and 4-wire hardware configuration selection. More...
 
enum  ade9000_var_acc_mode_e {
  ADE9000_ACC_SIGNED,
  ADE9000_ACC_ABSOLUTE,
  ADE9000_ACC_POSITIVE,
  ADE9000_ACC_NEGATIVE
}
 ADE9000 Total and fundamental reactive power accumulation mode for energy registers and CFx pulses. More...
 
enum  ade9000_line_period_sel_e {
  ADE9000_APERIOD,
  ADE9000_BPERIOD,
  ADE9000_CPERIOD,
  ADE9000_COM_PERIOD
}
 Selects line period measurement used for VRMS½ cycle, 10 cycle rms/12 cycle rms, and resampling. More...
 
enum  ade9000_zx_select_e {
  ADE9000_ZXVA_SEL,
  ADE9000_ZXVB_SEL,
  ADE9000_ZXVC_SEL,
  ADE9000_ZXCOMB_SEL
}
 Selects the zero-crossing signal, which can be routed to the CF3/ZX output pin and used for line cycle energy accumulation. More...
 
enum  ade9000_wf_src_e {
  ADE9000_SRC_SINC4,
  ADE9000_SRC_SINC4_IIR = 2,
  ADE9000_SRC_DSP
}
 Waveform buffer source and DREADY (data ready update rate) selection. More...
 
enum  ade9000_wf_mode_e {
  ADE9000_MODE_STOP_FULL,
  ADE9000_MODE_TRIG_EN_EVENTS,
  ADE9000_MODE_CENTER_CAPTURE,
  ADE9000_MODE_SAVE_EVENT_ADDR
}
 Fixed data rate waveforms filling and trigger based modes. More...
 
enum  ade9000_burst_ch_e {
  ADE9000_BURST_ALL_CH,
  ADE9000_BURST_IA_VA,
  ADE9000_BURST_IB_VB,
  ADE9000_BURST_IC_VC,
  ADE9000_BURST_IA = 8,
  ADE9000_BURST_VA,
  ADE9000_BURST_IB,
  ADE9000_BURST_VB,
  ADE9000_BURST_IC,
  ADE9000_BURST_VC,
  ADE9000_BURST_IN,
  ADE9000_BURST_DISABLED
}
 Selects which data to read out of the waveform buffer through SPI. More...
 
enum  ade9000_hpf_freq_e {
  ADE9000_HPF_77_39,
  ADE9000_HPF_39_275,
  ADE9000_HPF_19_79,
  ADE9000_HPF_9_935,
  ADE9000_HPF_4_98,
  ADE9000_HPF_2_495,
  ADE9000_HPF_1_25,
  ADE9000_HPF_0_625
}
 High-pass filter corner (f3dB) enabled when the HPFDIS bit in the CONFIG0 register is equal to zero. More...
 
enum  ade9000_no_load_tmr_e {
  ADE9000_NOLOAD_SAMPLES_64,
  ADE9000_NOLOAD_SAMPLES_128,
  ADE9000_NOLOAD_SAMPLES_256,
  ADE9000_NOLOAD_SAMPLES_512,
  ADE9000_NOLOAD_SAMPLES_1024,
  ADE9000_NOLOAD_SAMPLES_2048,
  ADE9000_NOLOAD_SAMPLES_4096,
  ADE9000_NOLOAD_SAMPLES_DISABLE
}
 This register configures how many 8 kSPS samples to evaluate the no load condition over. More...
 
enum  ade9000_temp_time_e {
  ADE9000_TEMP_TIME_1,
  ADE9000_TEMP_TIME_256,
  ADE9000_TEMP_TIME_512,
  ADE9000_TEMP_TIME_1024
}
 Select the number of temperature readings to average. More...
 
enum  ade9000_pga_gain_e {
  ADE9000_PGA_GAIN_1,
  ADE9000_PGA_GAIN_2,
  ADE9000_PGA_GAIN_3,
  ADE9000_PGA_GAIN_4
}
 PGA gain. More...
 
enum  ade9000_phase {
  ADE9000_PHASE_A,
  ADE9000_PHASE_B,
  ADE9000_PHASE_C
}
 ADE9000 available phases. More...
 
enum  ade9000_egy_model {
  ADE9000_EGY_WITH_RESET,
  ADE9000_EGY_HALF_LINE_CYCLES,
  ADE9000_EGY_NR_SAMPLES
}
 ADE9000 available user energy use models. More...
 

Functions

int ade9000_read (struct ade9000_dev *dev, uint16_t reg_addr, uint32_t *reg_data)
 Read device register. More...
 
int ade9000_write (struct ade9000_dev *dev, uint16_t reg_addr, uint32_t reg_data)
 Write device register. More...
 
int ade9000_update_bits (struct ade9000_dev *dev, uint16_t reg_addr, uint32_t mask, uint32_t reg_data)
 Update specific register bits. More...
 
int ade9000_read_temp (struct ade9000_dev *dev)
 Read the temperature. More...
 
int ade9000_read_data_ph (struct ade9000_dev *dev, enum ade9000_phase phase)
 Read the power/energy for specific phase. More...
 
int ade9000_set_egy_model (struct ade9000_dev *dev, enum ade9000_egy_model model, uint16_t value)
 Set User Energy use model. More...
 
int ade9000_init (struct ade9000_dev **device, struct ade9000_init_param init_param)
 Initialize the device. More...
 
int ade9000_setup (struct ade9000_dev *dev)
 Setup the device. More...
 
int ade9000_remove (struct ade9000_dev *dev)
 Remove the device and release resources. More...
 
int ade9000_get_int_status0 (struct ade9000_dev *dev, uint32_t msk, uint8_t *status)
 Get interrupt indicator from STATUS0 register. More...
 

Detailed Description

Header file of ADE9000 Driver.

Author
REtz (radu..nosp@m.etz@.nosp@m.analo.nosp@m.g.co.nosp@m.m)

Copyright 2024(c) Analog Devices, Inc.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

  1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
  2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
  3. Neither the name of Analog Devices, Inc. nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Macro Definition Documentation

◆ ADE9000_ACCMODE

#define ADE9000_ACCMODE   0x0000

◆ ADE9000_ADE9000_ID

#define ADE9000_ADE9000_ID   NO_OS_BIT(20)

◆ ADE9000_AFVANL

#define ADE9000_AFVANL   NO_OS_BIT(5)

◆ ADE9000_AFVARNL

#define ADE9000_AFVARNL   NO_OS_BIT(4)

◆ ADE9000_AFWATTNL

#define ADE9000_AFWATTNL   NO_OS_BIT(3)

◆ ADE9000_AREGION

#define ADE9000_AREGION   NO_OS_GENMASK(3, 0)

◆ ADE9000_AVANL

#define ADE9000_AVANL   NO_OS_BIT(2)

◆ ADE9000_AVARNL

#define ADE9000_AVARNL   NO_OS_BIT(1)

◆ ADE9000_AVARSIGN

#define ADE9000_AVARSIGN   NO_OS_BIT(1)

◆ ADE9000_AWATTNL

#define ADE9000_AWATTNL   NO_OS_BIT(0)

◆ ADE9000_AWSIGN

#define ADE9000_AWSIGN   NO_OS_BIT(0)

◆ ADE9000_BFVANL

#define ADE9000_BFVANL   NO_OS_BIT(11)

◆ ADE9000_BFVARNL

#define ADE9000_BFVARNL   NO_OS_BIT(10)

◆ ADE9000_BFWATTNL

#define ADE9000_BFWATTNL   NO_OS_BIT(9)

◆ ADE9000_BREGION

#define ADE9000_BREGION   NO_OS_GENMASK(3, 0)

◆ ADE9000_BURDEN_RES

#define ADE9000_BURDEN_RES   10

◆ ADE9000_BURST_CHAN

#define ADE9000_BURST_CHAN   NO_OS_GENMASK(3, 0)

◆ ADE9000_BURST_EN

#define ADE9000_BURST_EN   NO_OS_BIT(11)

◆ ADE9000_BVANL

#define ADE9000_BVANL   NO_OS_BIT(8)

◆ ADE9000_BVARNL

#define ADE9000_BVARNL   NO_OS_BIT(7)

◆ ADE9000_BVARSIGN

#define ADE9000_BVARSIGN   NO_OS_BIT(3)

◆ ADE9000_BWATTNL

#define ADE9000_BWATTNL   NO_OS_BIT(6)

◆ ADE9000_BWSIGN

#define ADE9000_BWSIGN   NO_OS_BIT(2)

◆ ADE9000_CF1_LT

#define ADE9000_CF1_LT   NO_OS_BIT(19)

◆ ADE9000_CF1DIS

#define ADE9000_CF1DIS   NO_OS_BIT(12)

◆ ADE9000_CF1SEL

#define ADE9000_CF1SEL   NO_OS_GENMASK(2, 0)

◆ ADE9000_CF2_LT

#define ADE9000_CF2_LT   NO_OS_BIT(20)

◆ ADE9000_CF2DIS

#define ADE9000_CF2DIS   NO_OS_BIT(13)

◆ ADE9000_CF2SEL

#define ADE9000_CF2SEL   NO_OS_GENMASK(5, 3)

◆ ADE9000_CF3_CFG

#define ADE9000_CF3_CFG   NO_OS_BIT(1)

◆ ADE9000_CF3_LT

#define ADE9000_CF3_LT   NO_OS_BIT(21)

◆ ADE9000_CF3DIS

#define ADE9000_CF3DIS   NO_OS_BIT(14)

◆ ADE9000_CF3SEL

#define ADE9000_CF3SEL   NO_OS_GENMASK(8, 6)

◆ ADE9000_CF4_CFG

#define ADE9000_CF4_CFG   NO_OS_GENMASK(3, 2)

◆ ADE9000_CF4_LT

#define ADE9000_CF4_LT   NO_OS_BIT(22)

◆ ADE9000_CF4DIS

#define ADE9000_CF4DIS   NO_OS_BIT(15)

◆ ADE9000_CF4SEL

#define ADE9000_CF4SEL   NO_OS_GENMASK(11, 9)

◆ ADE9000_CF_ACC_CLR

#define ADE9000_CF_ACC_CLR   NO_OS_BIT(5)

◆ ADE9000_CF_LTMR

#define ADE9000_CF_LTMR   NO_OS_GENMASK(18, 0)

◆ ADE9000_CFVANL

#define ADE9000_CFVANL   NO_OS_BIT(17)

◆ ADE9000_CFVARNL

#define ADE9000_CFVARNL   NO_OS_BIT(16)

◆ ADE9000_CFWATTNL

#define ADE9000_CFWATTNL   NO_OS_BIT(15)

◆ ADE9000_CHIP_ID

#define ADE9000_CHIP_ID   0x63

◆ ADE9000_CONFIG0

#define ADE9000_CONFIG0   0x00000000

◆ ADE9000_CONFIG1

#define ADE9000_CONFIG1   0x0002

◆ ADE9000_CONFIG2

#define ADE9000_CONFIG2   0x0C00

◆ ADE9000_CONFIG3

#define ADE9000_CONFIG3   0x0000

◆ ADE9000_CRC_ACT_NL_LVL_EN

#define ADE9000_CRC_ACT_NL_LVL_EN   NO_OS_BIT(7)

◆ ADE9000_CRC_APP_NL_LVL_EN

#define ADE9000_CRC_APP_NL_LVL_EN   NO_OS_BIT(9)

◆ ADE9000_CRC_DIP_CYC_EN

#define ADE9000_CRC_DIP_CYC_EN   NO_OS_BIT(4)

◆ ADE9000_CRC_DIP_LVL_EN

#define ADE9000_CRC_DIP_LVL_EN   NO_OS_BIT(3)

◆ ADE9000_CRC_EVENT_MASK_EN

#define ADE9000_CRC_EVENT_MASK_EN   NO_OS_BIT(2)

◆ ADE9000_CRC_MASK0_EN

#define ADE9000_CRC_MASK0_EN   NO_OS_BIT(0)

◆ ADE9000_CRC_MASK1_EN

#define ADE9000_CRC_MASK1_EN   NO_OS_BIT(1)

◆ ADE9000_CRC_REACT_NL_LVL_EN

#define ADE9000_CRC_REACT_NL_LVL_EN   NO_OS_BIT(8)

◆ ADE9000_CRC_SEQ_CYC_EN

#define ADE9000_CRC_SEQ_CYC_EN   NO_OS_BIT(12)

◆ ADE9000_CRC_SWELL_CYC_EN

#define ADE9000_CRC_SWELL_CYC_EN   NO_OS_BIT(6)

◆ ADE9000_CRC_SWELL_LVL_EN

#define ADE9000_CRC_SWELL_LVL_EN   NO_OS_BIT(5)

◆ ADE9000_CRC_WFB_CFG_EN

#define ADE9000_CRC_WFB_CFG_EN   NO_OS_BIT(13)

◆ ADE9000_CRC_WFB_PG_IRQEN

#define ADE9000_CRC_WFB_PG_IRQEN   NO_OS_BIT(14)

◆ ADE9000_CRC_WFB_TRG_CFG_EN

#define ADE9000_CRC_WFB_TRG_CFG_EN   NO_OS_BIT(15)

◆ ADE9000_CRC_ZXLPSEL_EN

#define ADE9000_CRC_ZXLPSEL_EN   NO_OS_BIT(11)

◆ ADE9000_CRC_ZXTOUT_EN

#define ADE9000_CRC_ZXTOUT_EN   NO_OS_BIT(10)

◆ ADE9000_CREGION

#define ADE9000_CREGION   NO_OS_GENMASK(3, 0)

◆ ADE9000_CURRENT_TR_FCN

#define ADE9000_CURRENT_TR_FCN   (ADE9000_CURRENT_TR_RATIO / ADE9000_BURDEN_RES)

◆ ADE9000_CURRENT_TR_RATIO

#define ADE9000_CURRENT_TR_RATIO   3000

◆ ADE9000_CVANL

#define ADE9000_CVANL   NO_OS_BIT(14)

◆ ADE9000_CVARNL

#define ADE9000_CVARNL   NO_OS_BIT(13)

◆ ADE9000_CVARSIGN

#define ADE9000_CVARSIGN   NO_OS_BIT(5)

◆ ADE9000_CWATTNL

#define ADE9000_CWATTNL   NO_OS_BIT(12)

◆ ADE9000_CWSIGN

#define ADE9000_CWSIGN   NO_OS_BIT(4)

◆ ADE9000_DICOEFF

#define ADE9000_DICOEFF   0x00000000

◆ ADE9000_DIP

#define ADE9000_DIP   NO_OS_BIT(0)

◆ ADE9000_DIP_SWELL_IRQ_MODE

#define ADE9000_DIP_SWELL_IRQ_MODE   NO_OS_BIT(10)

◆ ADE9000_DIPA_VAL

#define ADE9000_DIPA_VAL   NO_OS_GENMASK(23, 0)

◆ ADE9000_DIPB_VAL

#define ADE9000_DIPB_VAL   NO_OS_GENMASK(23, 0)

◆ ADE9000_DIPC_VAL

#define ADE9000_DIPC_VAL   NO_OS_GENMASK(23, 0)

◆ ADE9000_DIPLVL

#define ADE9000_DIPLVL   NO_OS_GENMASK(23, 0)

◆ ADE9000_DISAPLPF

#define ADE9000_DISAPLPF   NO_OS_BIT(12)

◆ ADE9000_DISRPLPF

#define ADE9000_DISRPLPF   NO_OS_BIT(13)

◆ ADE9000_DOWN_RES

#define ADE9000_DOWN_RES   1000

◆ ADE9000_EGY_LD_ACCUM

#define ADE9000_EGY_LD_ACCUM   NO_OS_BIT(4)

◆ ADE9000_EGY_PWR_EN

#define ADE9000_EGY_PWR_EN   NO_OS_BIT(0)

◆ ADE9000_EGY_TIME

#define ADE9000_EGY_TIME   0x1F3F

◆ ADE9000_EGY_TMR_MODE

#define ADE9000_EGY_TMR_MODE   NO_OS_BIT(1)

◆ ADE9000_EP_CFG

#define ADE9000_EP_CFG   0x0011

◆ ADE9000_EVENT_AFNOLOAD

#define ADE9000_EVENT_AFNOLOAD   NO_OS_BIT(13)

◆ ADE9000_EVENT_AFNOLOAD_MSK

#define ADE9000_EVENT_AFNOLOAD_MSK   NO_OS_BIT(13)

◆ ADE9000_EVENT_ANLOAD

#define ADE9000_EVENT_ANLOAD   NO_OS_BIT(10)

◆ ADE9000_EVENT_ANLOAD_MSK

#define ADE9000_EVENT_ANLOAD_MSK   NO_OS_BIT(10)

◆ ADE9000_EVENT_DIPA

#define ADE9000_EVENT_DIPA   NO_OS_BIT(0)

◆ ADE9000_EVENT_DIPAEN

#define ADE9000_EVENT_DIPAEN   NO_OS_BIT(0)

◆ ADE9000_EVENT_DIPB

#define ADE9000_EVENT_DIPB   NO_OS_BIT(1)

◆ ADE9000_EVENT_DIPBEN

#define ADE9000_EVENT_DIPBEN   NO_OS_BIT(1)

◆ ADE9000_EVENT_DIPC

#define ADE9000_EVENT_DIPC   NO_OS_BIT(2)

◆ ADE9000_EVENT_DIPCEN

#define ADE9000_EVENT_DIPCEN   NO_OS_BIT(2)

◆ ADE9000_EVENT_DREADY

#define ADE9000_EVENT_DREADY   NO_OS_BIT(16)

◆ ADE9000_EVENT_MASK

#define ADE9000_EVENT_MASK   0x00000000

◆ ADE9000_EVENT_READY_MSK

#define ADE9000_EVENT_READY_MSK   NO_OS_BIT(16)

◆ ADE9000_EVENT_REVPSUM1

#define ADE9000_EVENT_REVPSUM1   NO_OS_BIT(6)

◆ ADE9000_EVENT_REVPSUM1_MSK

#define ADE9000_EVENT_REVPSUM1_MSK   NO_OS_BIT(6)

◆ ADE9000_EVENT_REVPSUM2

#define ADE9000_EVENT_REVPSUM2   NO_OS_BIT(7)

◆ ADE9000_EVENT_REVPSUM2_MSK

#define ADE9000_EVENT_REVPSUM2_MSK   NO_OS_BIT(7)

◆ ADE9000_EVENT_REVPSUM3

#define ADE9000_EVENT_REVPSUM3   NO_OS_BIT(8)

◆ ADE9000_EVENT_REVPSUM3_MSK

#define ADE9000_EVENT_REVPSUM3_MSK   NO_OS_BIT(8)

◆ ADE9000_EVENT_REVPSUM4

#define ADE9000_EVENT_REVPSUM4   NO_OS_BIT(9)

◆ ADE9000_EVENT_REVPSUM4_MSK

#define ADE9000_EVENT_REVPSUM4_MSK   NO_OS_BIT(9)

◆ ADE9000_EVENT_RFNOLOAD

#define ADE9000_EVENT_RFNOLOAD   NO_OS_BIT(14)

◆ ADE9000_EVENT_RFNOLOAD_MSK

#define ADE9000_EVENT_RFNOLOAD_MSK   NO_OS_BIT(14)

◆ ADE9000_EVENT_RNLOAD

#define ADE9000_EVENT_RNLOAD   NO_OS_BIT(11)

◆ ADE9000_EVENT_RNLOAD_MSK

#define ADE9000_EVENT_RNLOAD_MSK   NO_OS_BIT(11)

◆ ADE9000_EVENT_SWELLA

#define ADE9000_EVENT_SWELLA   NO_OS_BIT(3)

◆ ADE9000_EVENT_SWELLAEN

#define ADE9000_EVENT_SWELLAEN   NO_OS_BIT(3)

◆ ADE9000_EVENT_SWELLB

#define ADE9000_EVENT_SWELLB   NO_OS_BIT(4)

◆ ADE9000_EVENT_SWELLBEN

#define ADE9000_EVENT_SWELLBEN   NO_OS_BIT(4)

◆ ADE9000_EVENT_SWELLC

#define ADE9000_EVENT_SWELLC   NO_OS_BIT(5)

◆ ADE9000_EVENT_SWELLCEN

#define ADE9000_EVENT_SWELLCEN   NO_OS_BIT(5)

◆ ADE9000_EVENT_VAFNOLOAD

#define ADE9000_EVENT_VAFNOLOAD   NO_OS_BIT(15)

◆ ADE9000_EVENT_VAFNOLOAD_MSK

#define ADE9000_EVENT_VAFNOLOAD_MSK   NO_OS_BIT(15)

◆ ADE9000_EVENT_VANLOAD

#define ADE9000_EVENT_VANLOAD   NO_OS_BIT(12)

◆ ADE9000_EVENT_VANLOAD_MSK

#define ADE9000_EVENT_VANLOAD_MSK   NO_OS_BIT(12)

◆ ADE9000_EXT_REF

#define ADE9000_EXT_REF   NO_OS_BIT(15)

◆ ADE9000_FORCE_CRC_UPDATE

#define ADE9000_FORCE_CRC_UPDATE   NO_OS_BIT(0)

◆ ADE9000_FS_VOLTAGE

#define ADE9000_FS_VOLTAGE   707

◆ ADE9000_HPF_CRN

#define ADE9000_HPF_CRN   NO_OS_GENMASK(11, 9)

◆ ADE9000_HPFDIS

#define ADE9000_HPFDIS   NO_OS_BIT(3)

◆ ADE9000_IA_DIN

#define ADE9000_IA_DIN   NO_OS_GENMASK(2, 0)

◆ ADE9000_IA_DISADC

#define ADE9000_IA_DISADC   NO_OS_BIT(0)

◆ ADE9000_IA_GAIN

#define ADE9000_IA_GAIN   NO_OS_GENMASK(1, 0)

◆ ADE9000_IB_DIN

#define ADE9000_IB_DIN   NO_OS_GENMASK(5, 3)

◆ ADE9000_IB_DISADC

#define ADE9000_IB_DISADC   NO_OS_BIT(1)

◆ ADE9000_IB_GAIN

#define ADE9000_IB_GAIN   NO_OS_GENMASK(3, 2)

◆ ADE9000_IC_DIN

#define ADE9000_IC_DIN   NO_OS_GENMASK(8, 6)

◆ ADE9000_IC_DISADC

#define ADE9000_IC_DISADC   NO_OS_BIT(2)

◆ ADE9000_IC_GAIN

#define ADE9000_IC_GAIN   NO_OS_GENMASK(5, 4)

◆ ADE9000_ICONSEL

#define ADE9000_ICONSEL   NO_OS_BIT(7)

◆ ADE9000_IN_DIN

#define ADE9000_IN_DIN   NO_OS_GENMASK(11, 9)

◆ ADE9000_IN_DISADC

#define ADE9000_IN_DISADC   NO_OS_BIT(3)

◆ ADE9000_IN_GAIN

#define ADE9000_IN_GAIN   NO_OS_GENMASK(7, 6)

◆ ADE9000_ININTEN

#define ADE9000_ININTEN   NO_OS_BIT(11)

◆ ADE9000_INTEN

#define ADE9000_INTEN   NO_OS_BIT(5)

◆ ADE9000_IPEAKVAL

#define ADE9000_IPEAKVAL   NO_OS_GENMASK(23, 0)

◆ ADE9000_IPPHASE

#define ADE9000_IPPHASE   NO_OS_GENMASK(26, 24)

◆ ADE9000_IRQ0_ON_IRQ1

#define ADE9000_IRQ0_ON_IRQ1   NO_OS_BIT(12)

◆ ADE9000_ISUM_CFG

#define ADE9000_ISUM_CFG   NO_OS_GENMASK(1, 0)

◆ ADE9000_LP_SEL

#define ADE9000_LP_SEL   NO_OS_GENMASK(4, 3)

◆ ADE9000_MASK0

#define ADE9000_MASK0   0x00000001

◆ ADE9000_MASK0_CF1

#define ADE9000_MASK0_CF1   NO_OS_BIT(11)

◆ ADE9000_MASK0_CF2

#define ADE9000_MASK0_CF2   NO_OS_BIT(12)

◆ ADE9000_MASK0_CF3

#define ADE9000_MASK0_CF3   NO_OS_BIT(13)

◆ ADE9000_MASK0_CF4

#define ADE9000_MASK0_CF4   NO_OS_BIT(14)

◆ ADE9000_MASK0_COH_WFB_FULL

#define ADE9000_MASK0_COH_WFB_FULL   NO_OS_BIT(23)

◆ ADE9000_MASK0_DREADY

#define ADE9000_MASK0_DREADY   NO_OS_BIT(15)

◆ ADE9000_MASK0_EGYRDY

#define ADE9000_MASK0_EGYRDY   NO_OS_BIT(0)

◆ ADE9000_MASK0_MISMTCH

#define ADE9000_MASK0_MISMTCH   NO_OS_BIT(24)

◆ ADE9000_MASK0_PAGE_FULL

#define ADE9000_MASK0_PAGE_FULL   NO_OS_BIT(17)

◆ ADE9000_MASK0_PWRRDY

#define ADE9000_MASK0_PWRRDY   NO_OS_BIT(18)

◆ ADE9000_MASK0_REVAPA

#define ADE9000_MASK0_REVAPA   NO_OS_BIT(1)

◆ ADE9000_MASK0_REVAPB

#define ADE9000_MASK0_REVAPB   NO_OS_BIT(2)

◆ ADE9000_MASK0_REVAPC

#define ADE9000_MASK0_REVAPC   NO_OS_BIT(3)

◆ ADE9000_MASK0_REVPSUM1

#define ADE9000_MASK0_REVPSUM1   NO_OS_BIT(7)

◆ ADE9000_MASK0_REVPSUM2

#define ADE9000_MASK0_REVPSUM2   NO_OS_BIT(8)

◆ ADE9000_MASK0_REVPSUM3

#define ADE9000_MASK0_REVPSUM3   NO_OS_BIT(9)

◆ ADE9000_MASK0_REVPSUM4

#define ADE9000_MASK0_REVPSUM4   NO_OS_BIT(10)

◆ ADE9000_MASK0_REVRPA

#define ADE9000_MASK0_REVRPA   NO_OS_BIT(4)

◆ ADE9000_MASK0_REVRPB

#define ADE9000_MASK0_REVRPB   NO_OS_BIT(5)

◆ ADE9000_MASK0_REVRPC

#define ADE9000_MASK0_REVRPC   NO_OS_BIT(6)

◆ ADE9000_MASK0_RMS1012RDY

#define ADE9000_MASK0_RMS1012RDY   NO_OS_BIT(20)

◆ ADE9000_MASK0_RMSONERDY

#define ADE9000_MASK0_RMSONERDY   NO_OS_BIT(19)

◆ ADE9000_MASK0_TEMP_RDY

#define ADE9000_MASK0_TEMP_RDY   NO_OS_BIT(25)

◆ ADE9000_MASK0_THD_PF_RDY

#define ADE9000_MASK0_THD_PF_RDY   NO_OS_BIT(21)

◆ ADE9000_MASK0_WFB_TRIG

#define ADE9000_MASK0_WFB_TRIG   NO_OS_BIT(22)

◆ ADE9000_MASK0_WFB_TRIG_IRQ

#define ADE9000_MASK0_WFB_TRIG_IRQ   NO_OS_BIT(16)

◆ ADE9000_MASK1

#define ADE9000_MASK1   0x00000000

◆ ADE9000_MASK1_AFNOLOAD

#define ADE9000_MASK1_AFNOLOAD   NO_OS_BIT(3)

◆ ADE9000_MASK1_ANLOAD

#define ADE9000_MASK1_ANLOAD   NO_OS_BIT(0)

◆ ADE9000_MASK1_CRC_CHG

#define ADE9000_MASK1_CRC_CHG   NO_OS_BIT(26)

◆ ADE9000_MASK1_CRC_DONE

#define ADE9000_MASK1_CRC_DONE   NO_OS_BIT(27)

◆ ADE9000_MASK1_DIPA

#define ADE9000_MASK1_DIPA   NO_OS_BIT(23)

◆ ADE9000_MASK1_DIPB

#define ADE9000_MASK1_DIPB   NO_OS_BIT(24)

◆ ADE9000_MASK1_DIPC

#define ADE9000_MASK1_DIPC   NO_OS_BIT(25)

◆ ADE9000_MASK1_ERROR0

#define ADE9000_MASK1_ERROR0   NO_OS_BIT(28)

◆ ADE9000_MASK1_ERROR1

#define ADE9000_MASK1_ERROR1   NO_OS_BIT(29)

◆ ADE9000_MASK1_ERROR2

#define ADE9000_MASK1_ERROR2   NO_OS_BIT(30)

◆ ADE9000_MASK1_ERROR3

#define ADE9000_MASK1_ERROR3   NO_OS_BIT(31)

◆ ADE9000_MASK1_OI

#define ADE9000_MASK1_OI   NO_OS_BIT(17)

◆ ADE9000_MASK1_RFNOLOAD

#define ADE9000_MASK1_RFNOLOAD   NO_OS_BIT(4)

◆ ADE9000_MASK1_RNLOAD

#define ADE9000_MASK1_RNLOAD   NO_OS_BIT(1)

◆ ADE9000_MASK1_SEQERR

#define ADE9000_MASK1_SEQERR   NO_OS_BIT(18)

◆ ADE9000_MASK1_SWELLA

#define ADE9000_MASK1_SWELLA   NO_OS_BIT(20)

◆ ADE9000_MASK1_SWELLB

#define ADE9000_MASK1_SWELLB   NO_OS_BIT(21)

◆ ADE9000_MASK1_SWELLC

#define ADE9000_MASK1_SWELLC   NO_OS_BIT(22)

◆ ADE9000_MASK1_VAFNOLOAD

#define ADE9000_MASK1_VAFNOLOAD   NO_OS_BIT(5)

◆ ADE9000_MASK1_VANLOAD

#define ADE9000_MASK1_VANLOAD   NO_OS_BIT(2)

◆ ADE9000_MASK1_ZXCOMB

#define ADE9000_MASK1_ZXCOMB   NO_OS_BIT(12)

◆ ADE9000_MASK1_ZXIA

#define ADE9000_MASK1_ZXIA   NO_OS_BIT(13)

◆ ADE9000_MASK1_ZXIB

#define ADE9000_MASK1_ZXIB   NO_OS_BIT(14)

◆ ADE9000_MASK1_ZXIC

#define ADE9000_MASK1_ZXIC   NO_OS_BIT(15)

◆ ADE9000_MASK1_ZXTOVA

#define ADE9000_MASK1_ZXTOVA   NO_OS_BIT(6)

◆ ADE9000_MASK1_ZXTOVB

#define ADE9000_MASK1_ZXTOVB   NO_OS_BIT(7)

◆ ADE9000_MASK1_ZXTOVC

#define ADE9000_MASK1_ZXTOVC   NO_OS_BIT(8)

◆ ADE9000_MASK1_ZXVA

#define ADE9000_MASK1_ZXVA   NO_OS_BIT(9)

◆ ADE9000_MASK1_ZXVB

#define ADE9000_MASK1_ZXVB   NO_OS_BIT(10)

◆ ADE9000_MASK1_ZXVC

#define ADE9000_MASK1_ZXVC   NO_OS_BIT(11)

◆ ADE9000_MTEN

#define ADE9000_MTEN   NO_OS_BIT(4)

◆ ADE9000_NOLOAD_TMR

#define ADE9000_NOLOAD_TMR   NO_OS_GENMASK(15, 13)

◆ ADE9000_OC_EN

#define ADE9000_OC_EN   NO_OS_GENMASK(15, 12)

◆ ADE9000_OI

#define ADE9000_OI   NO_OS_BIT(2)

◆ ADE9000_OI_VAL

#define ADE9000_OI_VAL   NO_OS_GENMASK(23, 0)

◆ ADE9000_OIB_VAL

#define ADE9000_OIB_VAL   NO_OS_GENMASK(23, 0)

◆ ADE9000_OIC_VAL

#define ADE9000_OIC_VAL   NO_OS_GENMASK(23, 0)

◆ ADE9000_OILVL_VAL

#define ADE9000_OILVL_VAL   NO_OS_GENMASK(23, 0)

◆ ADE9000_OIN_VAL

#define ADE9000_OIN_VAL   NO_OS_GENMASK(23, 0)

◆ ADE9000_OIPHASE

#define ADE9000_OIPHASE   NO_OS_GENMASK(3, 0)

◆ ADE9000_PCF_FS_CODES

#define ADE9000_PCF_FS_CODES   74532013

◆ ADE9000_PEAKSEL

#define ADE9000_PEAKSEL   NO_OS_GENMASK(4, 2)

◆ ADE9000_PGA_GAIN

#define ADE9000_PGA_GAIN   0x0000

◆ ADE9000_PWR_SETTLE

#define ADE9000_PWR_SETTLE   NO_OS_GENMASK(9, 8)

◆ ADE9000_PWR_SIGN_SEL_0

#define ADE9000_PWR_SIGN_SEL_0   NO_OS_BIT(6)

◆ ADE9000_PWR_SIGN_SEL_1

#define ADE9000_PWR_SIGN_SEL_1   NO_OS_BIT(7)

◆ ADE9000_RD_RST_EN

#define ADE9000_RD_RST_EN   NO_OS_BIT(5)

◆ ADE9000_REG_ACCMODE

#define ADE9000_REG_ACCMODE   0x0492

◆ ADE9000_REG_ACT_NL_LVL

#define ADE9000_REG_ACT_NL_LVL   0x041C

◆ ADE9000_REG_ADC_REDIRECT

#define ADE9000_REG_ADC_REDIRECT   0x0424

◆ ADE9000_REG_AFIRMS_1

#define ADE9000_REG_AFIRMS_1   0x0629

◆ ADE9000_REG_AFIRMS_2

#define ADE9000_REG_AFIRMS_2   0x068D

◆ ADE9000_REG_AFVA

#define ADE9000_REG_AFVA   0x0215

◆ ADE9000_REG_AFVA_1

#define ADE9000_REG_AFVA_1   0x0626

◆ ADE9000_REG_AFVA_2

#define ADE9000_REG_AFVA_2   0x068C

◆ ADE9000_REG_AFVA_ACC

#define ADE9000_REG_AFVA_ACC   0x0317

◆ ADE9000_REG_AFVAHR_HI

#define ADE9000_REG_AFVAHR_HI   0x0319

◆ ADE9000_REG_AFVAHR_LO

#define ADE9000_REG_AFVAHR_LO   0x0318

◆ ADE9000_REG_AFVAR

#define ADE9000_REG_AFVAR   0x0214

◆ ADE9000_REG_AFVAR_1

#define ADE9000_REG_AFVAR_1   0x0617

◆ ADE9000_REG_AFVAR_2

#define ADE9000_REG_AFVAR_2   0x0687

◆ ADE9000_REG_AFVAR_ACC

#define ADE9000_REG_AFVAR_ACC   0x030D

◆ ADE9000_REG_AFVARHR_HI

#define ADE9000_REG_AFVARHR_HI   0x030F

◆ ADE9000_REG_AFVARHR_LO

#define ADE9000_REG_AFVARHR_LO   0x030E

◆ ADE9000_REG_AFVAROS

#define ADE9000_REG_AFVAROS   0x0012

◆ ADE9000_REG_AFVRMS_1

#define ADE9000_REG_AFVRMS_1   0x062C

◆ ADE9000_REG_AFVRMS_2

#define ADE9000_REG_AFVRMS_2   0x068E

◆ ADE9000_REG_AFWATT

#define ADE9000_REG_AFWATT   0x0213

◆ ADE9000_REG_AFWATT_1

#define ADE9000_REG_AFWATT_1   0x0623

◆ ADE9000_REG_AFWATT_2

#define ADE9000_REG_AFWATT_2   0x068B

◆ ADE9000_REG_AFWATT_ACC

#define ADE9000_REG_AFWATT_ACC   0x0303

◆ ADE9000_REG_AFWATTHR_HI

#define ADE9000_REG_AFWATTHR_HI   0x0305

◆ ADE9000_REG_AFWATTHR_LO

#define ADE9000_REG_AFWATTHR_LO   0x0304

◆ ADE9000_REG_AFWATTOS

#define ADE9000_REG_AFWATTOS   0x0011

◆ ADE9000_REG_AI_LPF_DAT

#define ADE9000_REG_AI_LPF_DAT   0x0510

◆ ADE9000_REG_AI_PCF

#define ADE9000_REG_AI_PCF   0x020A

◆ ADE9000_REG_AI_PCF_1

#define ADE9000_REG_AI_PCF_1   0x0604

◆ ADE9000_REG_AI_PCF_2

#define ADE9000_REG_AI_PCF_2   0x0681

◆ ADE9000_REG_AI_SINC_DAT

#define ADE9000_REG_AI_SINC_DAT   0x0500

◆ ADE9000_REG_AIFRMS

#define ADE9000_REG_AIFRMS   0x020E

◆ ADE9000_REG_AIFRMSOS

#define ADE9000_REG_AIFRMSOS   0x0013

◆ ADE9000_REG_AIGAIN

#define ADE9000_REG_AIGAIN   0x0000

◆ ADE9000_REG_AIGAIN0

#define ADE9000_REG_AIGAIN0   0x0001

◆ ADE9000_REG_AIGAIN1

#define ADE9000_REG_AIGAIN1   0x0002

◆ ADE9000_REG_AIGAIN2

#define ADE9000_REG_AIGAIN2   0x0003

◆ ADE9000_REG_AIGAIN3

#define ADE9000_REG_AIGAIN3   0x0004

◆ ADE9000_REG_AIGAIN4

#define ADE9000_REG_AIGAIN4   0x0005

◆ ADE9000_REG_AIRMS

#define ADE9000_REG_AIRMS   0x020C

◆ ADE9000_REG_AIRMS1012

#define ADE9000_REG_AIRMS1012   0x021B

◆ ADE9000_REG_AIRMS1012_1

#define ADE9000_REG_AIRMS1012_1   0x0636

◆ ADE9000_REG_AIRMS1012_2

#define ADE9000_REG_AIRMS1012_2   0x0691

◆ ADE9000_REG_AIRMS1012OS

#define ADE9000_REG_AIRMS1012OS   0x0018

◆ ADE9000_REG_AIRMS_1

#define ADE9000_REG_AIRMS_1   0x0607

◆ ADE9000_REG_AIRMS_2

#define ADE9000_REG_AIRMS_2   0x0682

◆ ADE9000_REG_AIRMSONE

#define ADE9000_REG_AIRMSONE   0x0219

◆ ADE9000_REG_AIRMSONE_1

#define ADE9000_REG_AIRMSONE_1   0x062F

◆ ADE9000_REG_AIRMSONE_2

#define ADE9000_REG_AIRMSONE_2   0x068F

◆ ADE9000_REG_AIRMSONEOS

#define ADE9000_REG_AIRMSONEOS   0x0016

◆ ADE9000_REG_AIRMSOS

#define ADE9000_REG_AIRMSOS   0x000C

◆ ADE9000_REG_AITHD

#define ADE9000_REG_AITHD   0x0218

◆ ADE9000_REG_AITHD_1

#define ADE9000_REG_AITHD_1   0x0620

◆ ADE9000_REG_AITHD_2

#define ADE9000_REG_AITHD_2   0x068A

◆ ADE9000_REG_AMTREGION

#define ADE9000_REG_AMTREGION   0x021D

◆ ADE9000_REG_ANGL_IA_IB

#define ADE9000_REG_ANGL_IA_IB   0x0488

◆ ADE9000_REG_ANGL_IA_IC

#define ADE9000_REG_ANGL_IA_IC   0x048A

◆ ADE9000_REG_ANGL_IB_IC

#define ADE9000_REG_ANGL_IB_IC   0x0489

◆ ADE9000_REG_ANGL_VA_VB

#define ADE9000_REG_ANGL_VA_VB   0x0482

◆ ADE9000_REG_ANGL_VA_VC

#define ADE9000_REG_ANGL_VA_VC   0x0484

◆ ADE9000_REG_ANGL_VB_IA

#define ADE9000_REG_ANGL_VB_IA   0x0485

◆ ADE9000_REG_ANGL_VB_IB

#define ADE9000_REG_ANGL_VB_IB   0x0486

◆ ADE9000_REG_ANGL_VB_VC

#define ADE9000_REG_ANGL_VB_VC   0x0483

◆ ADE9000_REG_ANGL_VC_IC

#define ADE9000_REG_ANGL_VC_IC   0x0487

◆ ADE9000_REG_APERIOD

#define ADE9000_REG_APERIOD   0x0418

◆ ADE9000_REG_APF

#define ADE9000_REG_APF   0x0216

◆ ADE9000_REG_APF_1

#define ADE9000_REG_APF_1   0x061A

◆ ADE9000_REG_APF_2

#define ADE9000_REG_APF_2   0x0688

◆ ADE9000_REG_APGAIN

#define ADE9000_REG_APGAIN   0x000E

◆ ADE9000_REG_APHCAL0

#define ADE9000_REG_APHCAL0   0x0006

◆ ADE9000_REG_APHCAL1

#define ADE9000_REG_APHCAL1   0x0007

◆ ADE9000_REG_APHCAL2

#define ADE9000_REG_APHCAL2   0x0008

◆ ADE9000_REG_APHCAL3

#define ADE9000_REG_APHCAL3   0x0009

◆ ADE9000_REG_APHCAL4

#define ADE9000_REG_APHCAL4   0x000A

◆ ADE9000_REG_APP_NL_LVL

#define ADE9000_REG_APP_NL_LVL   0x041E

◆ ADE9000_REG_AV_LPF_DAT

#define ADE9000_REG_AV_LPF_DAT   0x0511

◆ ADE9000_REG_AV_PCF

#define ADE9000_REG_AV_PCF   0x020B

◆ ADE9000_REG_AV_PCF_1

#define ADE9000_REG_AV_PCF_1   0x0600

◆ ADE9000_REG_AV_PCF_2

#define ADE9000_REG_AV_PCF_2   0x0680

◆ ADE9000_REG_AV_SINC_DAT

#define ADE9000_REG_AV_SINC_DAT   0x0501

◆ ADE9000_REG_AVA

#define ADE9000_REG_AVA   0x0212

◆ ADE9000_REG_AVA_1

#define ADE9000_REG_AVA_1   0x0611

◆ ADE9000_REG_AVA_2

#define ADE9000_REG_AVA_2   0x0685

◆ ADE9000_REG_AVA_ACC

#define ADE9000_REG_AVA_ACC   0x02F9

◆ ADE9000_REG_AVAHR_HI

#define ADE9000_REG_AVAHR_HI   0x02FB

◆ ADE9000_REG_AVAHR_LO

#define ADE9000_REG_AVAHR_LO   0x02FA

◆ ADE9000_REG_AVAR

#define ADE9000_REG_AVAR   0x0211

◆ ADE9000_REG_AVAR_1

#define ADE9000_REG_AVAR_1   0x0614

◆ ADE9000_REG_AVAR_2

#define ADE9000_REG_AVAR_2   0x0686

◆ ADE9000_REG_AVAR_ACC

#define ADE9000_REG_AVAR_ACC   0x02EF

◆ ADE9000_REG_AVARHR_HI

#define ADE9000_REG_AVARHR_HI   0x02F1

◆ ADE9000_REG_AVARHR_LO

#define ADE9000_REG_AVARHR_LO   0x02F0

◆ ADE9000_REG_AVAROS

#define ADE9000_REG_AVAROS   0x0010

◆ ADE9000_REG_AVFRMS

#define ADE9000_REG_AVFRMS   0x020F

◆ ADE9000_REG_AVFRMSOS

#define ADE9000_REG_AVFRMSOS   0x0014

◆ ADE9000_REG_AVGAIN

#define ADE9000_REG_AVGAIN   0x000B

◆ ADE9000_REG_AVRMS

#define ADE9000_REG_AVRMS   0x020D

◆ ADE9000_REG_AVRMS1012

#define ADE9000_REG_AVRMS1012   0x021C

◆ ADE9000_REG_AVRMS1012_1

#define ADE9000_REG_AVRMS1012_1   0x0639

◆ ADE9000_REG_AVRMS1012_2

#define ADE9000_REG_AVRMS1012_2   0x0692

◆ ADE9000_REG_AVRMS1012OS

#define ADE9000_REG_AVRMS1012OS   0x0017

◆ ADE9000_REG_AVRMS_1

#define ADE9000_REG_AVRMS_1   0x060A

◆ ADE9000_REG_AVRMS_2

#define ADE9000_REG_AVRMS_2   0x0683

◆ ADE9000_REG_AVRMSONE

#define ADE9000_REG_AVRMSONE   0x021A

◆ ADE9000_REG_AVRMSONE_1

#define ADE9000_REG_AVRMSONE_1   0x0622

◆ ADE9000_REG_AVRMSONE_2

#define ADE9000_REG_AVRMSONE_2   0x0690

◆ ADE9000_REG_AVRMSONEOS

#define ADE9000_REG_AVRMSONEOS   0x0015

◆ ADE9000_REG_AVRMSOS

#define ADE9000_REG_AVRMSOS   0x000D

◆ ADE9000_REG_AVTHD

#define ADE9000_REG_AVTHD   0x0217

◆ ADE9000_REG_AVTHD_1

#define ADE9000_REG_AVTHD_1   0x061D

◆ ADE9000_REG_AVTHD_2

#define ADE9000_REG_AVTHD_2   0x0689

◆ ADE9000_REG_AWATT

#define ADE9000_REG_AWATT   0x0210

◆ ADE9000_REG_AWATT_1

#define ADE9000_REG_AWATT_1   0x060E

◆ ADE9000_REG_AWATT_2

#define ADE9000_REG_AWATT_2   0x0684

◆ ADE9000_REG_AWATT_ACC

#define ADE9000_REG_AWATT_ACC   0x02E5

◆ ADE9000_REG_AWATTHR_HI

#define ADE9000_REG_AWATTHR_HI   0x02E7

◆ ADE9000_REG_AWATTHR_LO

#define ADE9000_REG_AWATTHR_LO   0x02E6

◆ ADE9000_REG_AWATTOS

#define ADE9000_REG_AWATTOS   0x000F

◆ ADE9000_REG_BFIRMS_1

#define ADE9000_REG_BFIRMS_1   0x062A

◆ ADE9000_REG_BFIRMS_2

#define ADE9000_REG_BFIRMS_2   0x06A0

◆ ADE9000_REG_BFVA

#define ADE9000_REG_BFVA   0x0235

◆ ADE9000_REG_BFVA_1

#define ADE9000_REG_BFVA_1   0x0627

◆ ADE9000_REG_BFVA_2

#define ADE9000_REG_BFVA_2   0x069F

◆ ADE9000_REG_BFVA_ACC

#define ADE9000_REG_BFVA_ACC   0x0353

◆ ADE9000_REG_BFVAHR_HI

#define ADE9000_REG_BFVAHR_HI   0x0355

◆ ADE9000_REG_BFVAHR_LO

#define ADE9000_REG_BFVAHR_LO   0x0354

◆ ADE9000_REG_BFVAR

#define ADE9000_REG_BFVAR   0x0234

◆ ADE9000_REG_BFVAR_1

#define ADE9000_REG_BFVAR_1   0x0618

◆ ADE9000_REG_BFVAR_2

#define ADE9000_REG_BFVAR_2   0x069A

◆ ADE9000_REG_BFVAR_ACC

#define ADE9000_REG_BFVAR_ACC   0x0349

◆ ADE9000_REG_BFVARHR_HI

#define ADE9000_REG_BFVARHR_HI   0x034B

◆ ADE9000_REG_BFVARHR_LO

#define ADE9000_REG_BFVARHR_LO   0x034A

◆ ADE9000_REG_BFVAROS

#define ADE9000_REG_BFVAROS   0x0032

◆ ADE9000_REG_BFVRMS_1

#define ADE9000_REG_BFVRMS_1   0x062D

◆ ADE9000_REG_BFVRMS_2

#define ADE9000_REG_BFVRMS_2   0x06A1

◆ ADE9000_REG_BFWATT

#define ADE9000_REG_BFWATT   0x0233

◆ ADE9000_REG_BFWATT_1

#define ADE9000_REG_BFWATT_1   0x0624

◆ ADE9000_REG_BFWATT_2

#define ADE9000_REG_BFWATT_2   0x069E

◆ ADE9000_REG_BFWATT_ACC

#define ADE9000_REG_BFWATT_ACC   0x033F

◆ ADE9000_REG_BFWATTHR_HI

#define ADE9000_REG_BFWATTHR_HI   0x0341

◆ ADE9000_REG_BFWATTHR_LO

#define ADE9000_REG_BFWATTHR_LO   0x0340

◆ ADE9000_REG_BFWATTOS

#define ADE9000_REG_BFWATTOS   0x0031

◆ ADE9000_REG_BI_LPF_DAT

#define ADE9000_REG_BI_LPF_DAT   0x0512

◆ ADE9000_REG_BI_PCF

#define ADE9000_REG_BI_PCF   0x022A

◆ ADE9000_REG_BI_PCF_1

#define ADE9000_REG_BI_PCF_1   0x0605

◆ ADE9000_REG_BI_PCF_2

#define ADE9000_REG_BI_PCF_2   0x0694

◆ ADE9000_REG_BI_SINC_DAT

#define ADE9000_REG_BI_SINC_DAT   0x0502

◆ ADE9000_REG_BIFRMS

#define ADE9000_REG_BIFRMS   0x022E

◆ ADE9000_REG_BIFRMSOS

#define ADE9000_REG_BIFRMSOS   0x0033

◆ ADE9000_REG_BIGAIN

#define ADE9000_REG_BIGAIN   0x0020

◆ ADE9000_REG_BIGAIN0

#define ADE9000_REG_BIGAIN0   0x0021

◆ ADE9000_REG_BIGAIN1

#define ADE9000_REG_BIGAIN1   0x0022

◆ ADE9000_REG_BIGAIN2

#define ADE9000_REG_BIGAIN2   0x0023

◆ ADE9000_REG_BIGAIN3

#define ADE9000_REG_BIGAIN3   0x0024

◆ ADE9000_REG_BIGAIN4

#define ADE9000_REG_BIGAIN4   0x0025

◆ ADE9000_REG_BIRMS

#define ADE9000_REG_BIRMS   0x022C

◆ ADE9000_REG_BIRMS1012

#define ADE9000_REG_BIRMS1012   0x023B

◆ ADE9000_REG_BIRMS1012_1

#define ADE9000_REG_BIRMS1012_1   0x0637

◆ ADE9000_REG_BIRMS1012_2

#define ADE9000_REG_BIRMS1012_2   0x06A4

◆ ADE9000_REG_BIRMS1012OS

#define ADE9000_REG_BIRMS1012OS   0x0038

◆ ADE9000_REG_BIRMS_1

#define ADE9000_REG_BIRMS_1   0x0608

◆ ADE9000_REG_BIRMS_2

#define ADE9000_REG_BIRMS_2   0x0695

◆ ADE9000_REG_BIRMSONE

#define ADE9000_REG_BIRMSONE   0x0239

◆ ADE9000_REG_BIRMSONE_1

#define ADE9000_REG_BIRMSONE_1   0x0630

◆ ADE9000_REG_BIRMSONE_2

#define ADE9000_REG_BIRMSONE_2   0x06A2

◆ ADE9000_REG_BIRMSONEOS

#define ADE9000_REG_BIRMSONEOS   0x0036

◆ ADE9000_REG_BIRMSOS

#define ADE9000_REG_BIRMSOS   0x002C

◆ ADE9000_REG_BITHD

#define ADE9000_REG_BITHD   0x0238

◆ ADE9000_REG_BITHD_1

#define ADE9000_REG_BITHD_1   0x0621

◆ ADE9000_REG_BITHD_2

#define ADE9000_REG_BITHD_2   0x069D

◆ ADE9000_REG_BMTREGION

#define ADE9000_REG_BMTREGION   0x023D

◆ ADE9000_REG_BPERIOD

#define ADE9000_REG_BPERIOD   0x0419

◆ ADE9000_REG_BPF

#define ADE9000_REG_BPF   0x0236

◆ ADE9000_REG_BPF_1

#define ADE9000_REG_BPF_1   0x061B

◆ ADE9000_REG_BPF_2

#define ADE9000_REG_BPF_2   0x069B

◆ ADE9000_REG_BPGAIN

#define ADE9000_REG_BPGAIN   0x002E

◆ ADE9000_REG_BPHCAL0

#define ADE9000_REG_BPHCAL0   0x0026

◆ ADE9000_REG_BPHCAL1

#define ADE9000_REG_BPHCAL1   0x0027

◆ ADE9000_REG_BPHCAL2

#define ADE9000_REG_BPHCAL2   0x0028

◆ ADE9000_REG_BPHCAL3

#define ADE9000_REG_BPHCAL3   0x0029

◆ ADE9000_REG_BPHCAL4

#define ADE9000_REG_BPHCAL4   0x002A

◆ ADE9000_REG_BV_LPF_DAT

#define ADE9000_REG_BV_LPF_DAT   0x0513

◆ ADE9000_REG_BV_PCF

#define ADE9000_REG_BV_PCF   0x022B

◆ ADE9000_REG_BV_PCF_1

#define ADE9000_REG_BV_PCF_1   0x0601

◆ ADE9000_REG_BV_PCF_2

#define ADE9000_REG_BV_PCF_2   0x0693

◆ ADE9000_REG_BV_SINC_DAT

#define ADE9000_REG_BV_SINC_DAT   0x0503

◆ ADE9000_REG_BVA

#define ADE9000_REG_BVA   0x0232

◆ ADE9000_REG_BVA_1

#define ADE9000_REG_BVA_1   0x0612

◆ ADE9000_REG_BVA_2

#define ADE9000_REG_BVA_2   0x0698

◆ ADE9000_REG_BVA_ACC

#define ADE9000_REG_BVA_ACC   0x0335

◆ ADE9000_REG_BVAHR_HI

#define ADE9000_REG_BVAHR_HI   0x0337

◆ ADE9000_REG_BVAHR_LO

#define ADE9000_REG_BVAHR_LO   0x0336

◆ ADE9000_REG_BVAR

#define ADE9000_REG_BVAR   0x0231

◆ ADE9000_REG_BVAR_1

#define ADE9000_REG_BVAR_1   0x0615

◆ ADE9000_REG_BVAR_2

#define ADE9000_REG_BVAR_2   0x0699

◆ ADE9000_REG_BVAR_ACC

#define ADE9000_REG_BVAR_ACC   0x032B

◆ ADE9000_REG_BVARHR_HI

#define ADE9000_REG_BVARHR_HI   0x032D

◆ ADE9000_REG_BVARHR_LO

#define ADE9000_REG_BVARHR_LO   0x032C

◆ ADE9000_REG_BVAROS

#define ADE9000_REG_BVAROS   0x0030

◆ ADE9000_REG_BVFRMS

#define ADE9000_REG_BVFRMS   0x022F

◆ ADE9000_REG_BVFRMSOS

#define ADE9000_REG_BVFRMSOS   0x0034

◆ ADE9000_REG_BVGAIN

#define ADE9000_REG_BVGAIN   0x002B

◆ ADE9000_REG_BVRMS

#define ADE9000_REG_BVRMS   0x022D

◆ ADE9000_REG_BVRMS1012

#define ADE9000_REG_BVRMS1012   0x023C

◆ ADE9000_REG_BVRMS1012_1

#define ADE9000_REG_BVRMS1012_1   0x063A

◆ ADE9000_REG_BVRMS1012_2

#define ADE9000_REG_BVRMS1012_2   0x06A5

◆ ADE9000_REG_BVRMS1012OS

#define ADE9000_REG_BVRMS1012OS   0x0037

◆ ADE9000_REG_BVRMS_1

#define ADE9000_REG_BVRMS_1   0x060B

◆ ADE9000_REG_BVRMS_2

#define ADE9000_REG_BVRMS_2   0x0696

◆ ADE9000_REG_BVRMSONE

#define ADE9000_REG_BVRMSONE   0x023A

◆ ADE9000_REG_BVRMSONE_1

#define ADE9000_REG_BVRMSONE_1   0x0633

◆ ADE9000_REG_BVRMSONE_2

#define ADE9000_REG_BVRMSONE_2   0x06A3

◆ ADE9000_REG_BVRMSONEOS

#define ADE9000_REG_BVRMSONEOS   0x0035

◆ ADE9000_REG_BVRMSOS

#define ADE9000_REG_BVRMSOS   0x002D

◆ ADE9000_REG_BVTHD

#define ADE9000_REG_BVTHD   0x0237

◆ ADE9000_REG_BVTHD_1

#define ADE9000_REG_BVTHD_1   0x061E

◆ ADE9000_REG_BVTHD_2

#define ADE9000_REG_BVTHD_2   0x069C

◆ ADE9000_REG_BWATT

#define ADE9000_REG_BWATT   0x0230

◆ ADE9000_REG_BWATT_1

#define ADE9000_REG_BWATT_1   0x060F

◆ ADE9000_REG_BWATT_2

#define ADE9000_REG_BWATT_2   0x0697

◆ ADE9000_REG_BWATT_ACC

#define ADE9000_REG_BWATT_ACC   0x0321

◆ ADE9000_REG_BWATTHR_HI

#define ADE9000_REG_BWATTHR_HI   0x0323

◆ ADE9000_REG_BWATTHR_LO

#define ADE9000_REG_BWATTHR_LO   0x0322

◆ ADE9000_REG_BWATTOS

#define ADE9000_REG_BWATTOS   0x002F

◆ ADE9000_REG_CF1DEN

#define ADE9000_REG_CF1DEN   0x0494

◆ ADE9000_REG_CF2DEN

#define ADE9000_REG_CF2DEN   0x0495

◆ ADE9000_REG_CF3DEN

#define ADE9000_REG_CF3DEN   0x0496

◆ ADE9000_REG_CF4DEN

#define ADE9000_REG_CF4DEN   0x0497

◆ ADE9000_REG_CF_LCFG

#define ADE9000_REG_CF_LCFG   0x0425

◆ ADE9000_REG_CFIRMS_1

#define ADE9000_REG_CFIRMS_1   0x062B

◆ ADE9000_REG_CFIRMS_2

#define ADE9000_REG_CFIRMS_2   0x06B3

◆ ADE9000_REG_CFMODE

#define ADE9000_REG_CFMODE   0x0490

◆ ADE9000_REG_CFVA

#define ADE9000_REG_CFVA   0x0255

◆ ADE9000_REG_CFVA_1

#define ADE9000_REG_CFVA_1   0x0628

◆ ADE9000_REG_CFVA_2

#define ADE9000_REG_CFVA_2   0x06B2

◆ ADE9000_REG_CFVA_ACC

#define ADE9000_REG_CFVA_ACC   0x038F

◆ ADE9000_REG_CFVAHR_HI

#define ADE9000_REG_CFVAHR_HI   0x0391

◆ ADE9000_REG_CFVAHR_LO

#define ADE9000_REG_CFVAHR_LO   0x0390

◆ ADE9000_REG_CFVAR

#define ADE9000_REG_CFVAR   0x0254

◆ ADE9000_REG_CFVAR_1

#define ADE9000_REG_CFVAR_1   0x0619

◆ ADE9000_REG_CFVAR_2

#define ADE9000_REG_CFVAR_2   0x06AD

◆ ADE9000_REG_CFVAR_ACC

#define ADE9000_REG_CFVAR_ACC   0x0385

◆ ADE9000_REG_CFVARHR_HI

#define ADE9000_REG_CFVARHR_HI   0x0387

◆ ADE9000_REG_CFVARHR_LO

#define ADE9000_REG_CFVARHR_LO   0x0386

◆ ADE9000_REG_CFVAROS

#define ADE9000_REG_CFVAROS   0x0052

◆ ADE9000_REG_CFVRMS_1

#define ADE9000_REG_CFVRMS_1   0x062E

◆ ADE9000_REG_CFVRMS_2

#define ADE9000_REG_CFVRMS_2   0x06B4

◆ ADE9000_REG_CFWATT

#define ADE9000_REG_CFWATT   0x0253

◆ ADE9000_REG_CFWATT_1

#define ADE9000_REG_CFWATT_1   0x0625

◆ ADE9000_REG_CFWATT_2

#define ADE9000_REG_CFWATT_2   0x06B1

◆ ADE9000_REG_CFWATT_ACC

#define ADE9000_REG_CFWATT_ACC   0x037B

◆ ADE9000_REG_CFWATTHR_HI

#define ADE9000_REG_CFWATTHR_HI   0x037D

◆ ADE9000_REG_CFWATTHR_LO

#define ADE9000_REG_CFWATTHR_LO   0x037C

◆ ADE9000_REG_CFWATTOS

#define ADE9000_REG_CFWATTOS   0x0051

◆ ADE9000_REG_CHNL_DIS

#define ADE9000_REG_CHNL_DIS   0x04BA

◆ ADE9000_REG_CI_LPF_DAT

#define ADE9000_REG_CI_LPF_DAT   0x0514

◆ ADE9000_REG_CI_PCF

#define ADE9000_REG_CI_PCF   0x024A

◆ ADE9000_REG_CI_PCF_1

#define ADE9000_REG_CI_PCF_1   0x0606

◆ ADE9000_REG_CI_PCF_2

#define ADE9000_REG_CI_PCF_2   0x06A7

◆ ADE9000_REG_CI_SINC_DAT

#define ADE9000_REG_CI_SINC_DAT   0x0504

◆ ADE9000_REG_CIFRMS

#define ADE9000_REG_CIFRMS   0x024E

◆ ADE9000_REG_CIFRMSOS

#define ADE9000_REG_CIFRMSOS   0x0053

◆ ADE9000_REG_CIGAIN

#define ADE9000_REG_CIGAIN   0x0040

◆ ADE9000_REG_CIGAIN0

#define ADE9000_REG_CIGAIN0   0x0041

◆ ADE9000_REG_CIGAIN1

#define ADE9000_REG_CIGAIN1   0x0042

◆ ADE9000_REG_CIGAIN2

#define ADE9000_REG_CIGAIN2   0x0043

◆ ADE9000_REG_CIGAIN3

#define ADE9000_REG_CIGAIN3   0x0044

◆ ADE9000_REG_CIGAIN4

#define ADE9000_REG_CIGAIN4   0x0045

◆ ADE9000_REG_CIRMS

#define ADE9000_REG_CIRMS   0x024C

◆ ADE9000_REG_CIRMS1012

#define ADE9000_REG_CIRMS1012   0x025B

◆ ADE9000_REG_CIRMS1012_1

#define ADE9000_REG_CIRMS1012_1   0x0638

◆ ADE9000_REG_CIRMS1012_2

#define ADE9000_REG_CIRMS1012_2   0x06B7

◆ ADE9000_REG_CIRMS1012OS

#define ADE9000_REG_CIRMS1012OS   0x0058

◆ ADE9000_REG_CIRMS_1

#define ADE9000_REG_CIRMS_1   0x0609

◆ ADE9000_REG_CIRMS_2

#define ADE9000_REG_CIRMS_2   0x06A8

◆ ADE9000_REG_CIRMSONE

#define ADE9000_REG_CIRMSONE   0x0259

◆ ADE9000_REG_CIRMSONE_1

#define ADE9000_REG_CIRMSONE_1   0x0631

◆ ADE9000_REG_CIRMSONE_2

#define ADE9000_REG_CIRMSONE_2   0x06B5

◆ ADE9000_REG_CIRMSONEOS

#define ADE9000_REG_CIRMSONEOS   0x0056

◆ ADE9000_REG_CIRMSOS

#define ADE9000_REG_CIRMSOS   0x004C

◆ ADE9000_REG_CITHD

#define ADE9000_REG_CITHD   0x0258

◆ ADE9000_REG_CITHD_1

#define ADE9000_REG_CITHD_1   0x0622

◆ ADE9000_REG_CITHD_2

#define ADE9000_REG_CITHD_2   0x06B0

◆ ADE9000_REG_CMTREGION

#define ADE9000_REG_CMTREGION   0x025D

◆ ADE9000_REG_COM_PERIOD

#define ADE9000_REG_COM_PERIOD   0x041B

◆ ADE9000_REG_COMPMODE

#define ADE9000_REG_COMPMODE   0x0491

◆ ADE9000_REG_CONFIG0

#define ADE9000_REG_CONFIG0   0x0060

◆ ADE9000_REG_CONFIG1

#define ADE9000_REG_CONFIG1   0x0481

◆ ADE9000_REG_CONFIG2

#define ADE9000_REG_CONFIG2   0x04AF

◆ ADE9000_REG_CONFIG3

#define ADE9000_REG_CONFIG3   0x0493

◆ ADE9000_REG_CONFIG5

#define ADE9000_REG_CONFIG5   0x04A4

◆ ADE9000_REG_CPERIOD

#define ADE9000_REG_CPERIOD   0x041A

◆ ADE9000_REG_CPF

#define ADE9000_REG_CPF   0x0256

◆ ADE9000_REG_CPF_1

#define ADE9000_REG_CPF_1   0x061C

◆ ADE9000_REG_CPF_2

#define ADE9000_REG_CPF_2   0x06AE

◆ ADE9000_REG_CPGAIN

#define ADE9000_REG_CPGAIN   0x004E

◆ ADE9000_REG_CPHCAL0

#define ADE9000_REG_CPHCAL0   0x0046

◆ ADE9000_REG_CPHCAL1

#define ADE9000_REG_CPHCAL1   0x0047

◆ ADE9000_REG_CPHCAL2

#define ADE9000_REG_CPHCAL2   0x0048

◆ ADE9000_REG_CPHCAL3

#define ADE9000_REG_CPHCAL3   0x0049

◆ ADE9000_REG_CPHCAL4

#define ADE9000_REG_CPHCAL4   0x004A

◆ ADE9000_REG_CRC_FORCE

#define ADE9000_REG_CRC_FORCE   0x04B4

◆ ADE9000_REG_CRC_OPTEN

#define ADE9000_REG_CRC_OPTEN   0x04B5

◆ ADE9000_REG_CRC_RSLT

#define ADE9000_REG_CRC_RSLT   0x04A8

◆ ADE9000_REG_CRC_SPI

#define ADE9000_REG_CRC_SPI   0x04A9

◆ ADE9000_REG_CV_LPF_DAT

#define ADE9000_REG_CV_LPF_DAT   0x0515

◆ ADE9000_REG_CV_PCF

#define ADE9000_REG_CV_PCF   0x024B

◆ ADE9000_REG_CV_PCF_1

#define ADE9000_REG_CV_PCF_1   0x0602

◆ ADE9000_REG_CV_PCF_2

#define ADE9000_REG_CV_PCF_2   0x06A6

◆ ADE9000_REG_CV_SINC_DAT

#define ADE9000_REG_CV_SINC_DAT   0x0505

◆ ADE9000_REG_CVA

#define ADE9000_REG_CVA   0x0252

◆ ADE9000_REG_CVA_1

#define ADE9000_REG_CVA_1   0x0613

◆ ADE9000_REG_CVA_2

#define ADE9000_REG_CVA_2   0x06AB

◆ ADE9000_REG_CVA_ACC

#define ADE9000_REG_CVA_ACC   0x0371

◆ ADE9000_REG_CVAHR_HI

#define ADE9000_REG_CVAHR_HI   0x0373

◆ ADE9000_REG_CVAHR_LO

#define ADE9000_REG_CVAHR_LO   0x0372

◆ ADE9000_REG_CVAR

#define ADE9000_REG_CVAR   0x0251

◆ ADE9000_REG_CVAR_1

#define ADE9000_REG_CVAR_1   0x0616

◆ ADE9000_REG_CVAR_2

#define ADE9000_REG_CVAR_2   0x06AC

◆ ADE9000_REG_CVAR_ACC

#define ADE9000_REG_CVAR_ACC   0x0367

◆ ADE9000_REG_CVARHR_HI

#define ADE9000_REG_CVARHR_HI   0x0369

◆ ADE9000_REG_CVARHR_LO

#define ADE9000_REG_CVARHR_LO   0x0368

◆ ADE9000_REG_CVAROS

#define ADE9000_REG_CVAROS   0x0050

◆ ADE9000_REG_CVFRMS

#define ADE9000_REG_CVFRMS   0x024F

◆ ADE9000_REG_CVFRMSOS

#define ADE9000_REG_CVFRMSOS   0x0054

◆ ADE9000_REG_CVGAIN

#define ADE9000_REG_CVGAIN   0x004B

◆ ADE9000_REG_CVRMS

#define ADE9000_REG_CVRMS   0x024D

◆ ADE9000_REG_CVRMS1012

#define ADE9000_REG_CVRMS1012   0x025C

◆ ADE9000_REG_CVRMS1012_1

#define ADE9000_REG_CVRMS1012_1   0x063B

◆ ADE9000_REG_CVRMS1012_2

#define ADE9000_REG_CVRMS1012_2   0x06B8

◆ ADE9000_REG_CVRMS1012OS

#define ADE9000_REG_CVRMS1012OS   0x0057

◆ ADE9000_REG_CVRMS_1

#define ADE9000_REG_CVRMS_1   0x060C

◆ ADE9000_REG_CVRMS_2

#define ADE9000_REG_CVRMS_2   0x06A9

◆ ADE9000_REG_CVRMSONE

#define ADE9000_REG_CVRMSONE   0x025A

◆ ADE9000_REG_CVRMSONE_1

#define ADE9000_REG_CVRMSONE_1   0x0634

◆ ADE9000_REG_CVRMSONE_2

#define ADE9000_REG_CVRMSONE_2   0x06B6

◆ ADE9000_REG_CVRMSONEOS

#define ADE9000_REG_CVRMSONEOS   0x0055

◆ ADE9000_REG_CVRMSOS

#define ADE9000_REG_CVRMSOS   0x004D

◆ ADE9000_REG_CVTHD

#define ADE9000_REG_CVTHD   0x0257

◆ ADE9000_REG_CVTHD_1

#define ADE9000_REG_CVTHD_1   0x061F

◆ ADE9000_REG_CVTHD_2

#define ADE9000_REG_CVTHD_2   0x06AF

◆ ADE9000_REG_CWATT

#define ADE9000_REG_CWATT   0x0250

◆ ADE9000_REG_CWATT_1

#define ADE9000_REG_CWATT_1   0x0610

◆ ADE9000_REG_CWATT_2

#define ADE9000_REG_CWATT_2   0x06AA

◆ ADE9000_REG_CWATT_ACC

#define ADE9000_REG_CWATT_ACC   0x035D

◆ ADE9000_REG_CWATTHR_HI

#define ADE9000_REG_CWATTHR_HI   0x035F

◆ ADE9000_REG_CWATTHR_LO

#define ADE9000_REG_CWATTHR_LO   0x035E

◆ ADE9000_REG_CWATTOS

#define ADE9000_REG_CWATTOS   0x004F

◆ ADE9000_REG_DICOEFF

#define ADE9000_REG_DICOEFF   0x0072

◆ ADE9000_REG_DIP_CYC

#define ADE9000_REG_DIP_CYC   0x048B

◆ ADE9000_REG_DIP_LVL

#define ADE9000_REG_DIP_LVL   0x410

◆ ADE9000_REG_DIPA

#define ADE9000_REG_DIPA   0x411

◆ ADE9000_REG_DIPB

#define ADE9000_REG_DIPB   0x412

◆ ADE9000_REG_DIPC

#define ADE9000_REG_DIPC   0x413

◆ ADE9000_REG_EGY_TIME

#define ADE9000_REG_EGY_TIME   0x04B2

◆ ADE9000_REG_EP_CFG

#define ADE9000_REG_EP_CFG   0x04B0

◆ ADE9000_REG_EVENT_MASK

#define ADE9000_REG_EVENT_MASK   0x0407

◆ ADE9000_REG_EVENT_STATUS

#define ADE9000_REG_EVENT_STATUS   0x0404

◆ ADE9000_REG_IPEAK

#define ADE9000_REG_IPEAK   0x0400

◆ ADE9000_REG_ISUMLVL

#define ADE9000_REG_ISUMLVL   0x0073

◆ ADE9000_REG_ISUMRMS

#define ADE9000_REG_ISUMRMS   0x0269

◆ ADE9000_REG_ISUMRMSOS

#define ADE9000_REG_ISUMRMSOS   0x006C

◆ ADE9000_REG_LAST_CMD

#define ADE9000_REG_LAST_CMD   0x04AE

◆ ADE9000_REG_LAST_DATA_16

#define ADE9000_REG_LAST_DATA_16   0x04AC

◆ ADE9000_REG_LAST_DATA_32

#define ADE9000_REG_LAST_DATA_32   0x0423

◆ ADE9000_REG_MASK0

#define ADE9000_REG_MASK0   0x0405

◆ ADE9000_REG_MASK1

#define ADE9000_REG_MASK1   0x0406

◆ ADE9000_REG_MTTHR_H0

#define ADE9000_REG_MTTHR_H0   0x0066

◆ ADE9000_REG_MTTHR_H1

#define ADE9000_REG_MTTHR_H1   0x0067

◆ ADE9000_REG_MTTHR_H2

#define ADE9000_REG_MTTHR_H2   0x0068

◆ ADE9000_REG_MTTHR_H3

#define ADE9000_REG_MTTHR_H3   0x0069

◆ ADE9000_REG_MTTHR_H4

#define ADE9000_REG_MTTHR_H4   0x006A

◆ ADE9000_REG_MTTHR_L0

#define ADE9000_REG_MTTHR_L0   0x0061

◆ ADE9000_REG_MTTHR_L1

#define ADE9000_REG_MTTHR_L1   0x0062

◆ ADE9000_REG_MTTHR_L2

#define ADE9000_REG_MTTHR_L2   0x0063

◆ ADE9000_REG_MTTHR_L3

#define ADE9000_REG_MTTHR_L3   0x0064

◆ ADE9000_REG_MTTHR_L4

#define ADE9000_REG_MTTHR_L4   0x0065

◆ ADE9000_REG_NI_LPF_DAT

#define ADE9000_REG_NI_LPF_DAT   0x0516

◆ ADE9000_REG_NI_PCF

#define ADE9000_REG_NI_PCF   0x0265

◆ ADE9000_REG_NI_PCF_1

#define ADE9000_REG_NI_PCF_1   0x0603

◆ ADE9000_REG_NI_PCF_2

#define ADE9000_REG_NI_PCF_2   0x06B9

◆ ADE9000_REG_NI_SINC_DAT

#define ADE9000_REG_NI_SINC_DAT   0x0506

◆ ADE9000_REG_NIGAIN

#define ADE9000_REG_NIGAIN   0x006D

◆ ADE9000_REG_NIRMS

#define ADE9000_REG_NIRMS   0x0266

◆ ADE9000_REG_NIRMS1012

#define ADE9000_REG_NIRMS1012   0x0268

◆ ADE9000_REG_NIRMS1012_1

#define ADE9000_REG_NIRMS1012_1   0x063C

◆ ADE9000_REG_NIRMS1012_2

#define ADE9000_REG_NIRMS1012_2   0x06BC

◆ ADE9000_REG_NIRMS1012OS

#define ADE9000_REG_NIRMS1012OS   0x0070

◆ ADE9000_REG_NIRMS_1

#define ADE9000_REG_NIRMS_1   0x060D

◆ ADE9000_REG_NIRMS_2

#define ADE9000_REG_NIRMS_2   0x06BA

◆ ADE9000_REG_NIRMSONE

#define ADE9000_REG_NIRMSONE   0x0267

◆ ADE9000_REG_NIRMSONE_2

#define ADE9000_REG_NIRMSONE_2   0x06BB

◆ ADE9000_REG_NIRMSONEOS

#define ADE9000_REG_NIRMSONEOS   0x006F

◆ ADE9000_REG_NIRMSOS

#define ADE9000_REG_NIRMSOS   0x006B

◆ ADE9000_REG_NIRSONE_1

#define ADE9000_REG_NIRSONE_1   0x0635

◆ ADE9000_REG_NPHCAL

#define ADE9000_REG_NPHCAL   0x006E

◆ ADE9000_REG_NVAR_ACC

#define ADE9000_REG_NVAR_ACC   0x03A3

◆ ADE9000_REG_NWATT_ACC

#define ADE9000_REG_NWATT_ACC   0x039B

◆ ADE9000_REG_OIA

#define ADE9000_REG_OIA   0x040A

◆ ADE9000_REG_OIB

#define ADE9000_REG_OIB   0x040B

◆ ADE9000_REG_OIC

#define ADE9000_REG_OIC   0x040C

◆ ADE9000_REG_OILVL

#define ADE9000_REG_OILVL   0x0409

◆ ADE9000_REG_OIN

#define ADE9000_REG_OIN   0x040D

◆ ADE9000_REG_OISTATUS

#define ADE9000_REG_OISTATUS   0x048F

◆ ADE9000_REG_PART_ID

#define ADE9000_REG_PART_ID   0x0472

◆ ADE9000_REG_PGA_GAIN

#define ADE9000_REG_PGA_GAIN   0x04B9

◆ ADE9000_REG_PHNOLOAD

#define ADE9000_REG_PHNOLOAD   0x041F

◆ ADE9000_REG_PHSIGN

#define ADE9000_REG_PHSIGN   0x049D

◆ ADE9000_REG_PVAR_ACC

#define ADE9000_REG_PVAR_ACC   0x039F

◆ ADE9000_REG_PWATT_ACC

#define ADE9000_REG_PWATT_ACC   0x0397

◆ ADE9000_REG_PWR_TIME

#define ADE9000_REG_PWR_TIME   0x04B1

◆ ADE9000_REG_REACT_NL_LVL

#define ADE9000_REG_REACT_NL_LVL   0x041D

◆ ADE9000_REG_RESERVED1

#define ADE9000_REG_RESERVED1   0x04F0

◆ ADE9000_REG_RUN

#define ADE9000_REG_RUN   0x0480

◆ ADE9000_REG_SEQ_CYC

#define ADE9000_REG_SEQ_CYC   0x049C

◆ ADE9000_REG_STATUS0

#define ADE9000_REG_STATUS0   0x0402

◆ ADE9000_REG_STATUS1

#define ADE9000_REG_STATUS1   0x0403

◆ ADE9000_REG_SWELL_CYC

#define ADE9000_REG_SWELL_CYC   0x048C

◆ ADE9000_REG_SWELL_LVL

#define ADE9000_REG_SWELL_LVL   0x414

◆ ADE9000_REG_SWELLA

#define ADE9000_REG_SWELLA   0x415

◆ ADE9000_REG_SWELLB

#define ADE9000_REG_SWELLB   0x416

◆ ADE9000_REG_SWELLC

#define ADE9000_REG_SWELLC   0x417

◆ ADE9000_REG_TEMP_CFG

#define ADE9000_REG_TEMP_CFG   0x04B6

◆ ADE9000_REG_TEMP_RSLT

#define ADE9000_REG_TEMP_RSLT   0x04B7

◆ ADE9000_REG_TEMP_TRIM

#define ADE9000_REG_TEMP_TRIM   0x0474

◆ ADE9000_REG_USER_PERIOD

#define ADE9000_REG_USER_PERIOD   0x040E

◆ ADE9000_REG_VAR_DIS

#define ADE9000_REG_VAR_DIS   0x04E0

◆ ADE9000_REG_VARTHR

#define ADE9000_REG_VARTHR   0x0421

◆ ADE9000_REG_VATHR

#define ADE9000_REG_VATHR   0x0422

◆ ADE9000_REG_VERSION

#define ADE9000_REG_VERSION   0x04FE

◆ ADE9000_REG_VERSION2

#define ADE9000_REG_VERSION2   0x026A

◆ ADE9000_REG_VLEVEL

#define ADE9000_REG_VLEVEL   0x040F

◆ ADE9000_REG_VNOM

#define ADE9000_REG_VNOM   0x0071

◆ ADE9000_REG_VPEAK

#define ADE9000_REG_VPEAK   0x0401

◆ ADE9000_REG_WFB_CFG

#define ADE9000_REG_WFB_CFG   0x04A0

◆ ADE9000_REG_WFB_PG_IRQEN

#define ADE9000_REG_WFB_PG_IRQEN   0x04A1

◆ ADE9000_REG_WFB_TRG_CFG

#define ADE9000_REG_WFB_TRG_CFG   0x04A2

◆ ADE9000_REG_WFB_TRG_STAT

#define ADE9000_REG_WFB_TRG_STAT   0x04A3

◆ ADE9000_REG_WR_LOCK

#define ADE9000_REG_WR_LOCK   0x04BF

◆ ADE9000_REG_WTHR

#define ADE9000_REG_WTHR   0x0420

◆ ADE9000_REG_ZX_LP_SEL

#define ADE9000_REG_ZX_LP_SEL   0x049A

◆ ADE9000_REG_ZXTHRSH

#define ADE9000_REG_ZXTHRSH   0x0499

◆ ADE9000_REG_ZXTOUT

#define ADE9000_REG_ZXTOUT   0x0498

◆ ADE9000_RESAMPLED_FS_CODES

#define ADE9000_RESAMPLED_FS_CODES   18196

◆ ADE9000_RMS_FS_CODES

#define ADE9000_RMS_FS_CODES   52702092

◆ ADE9000_RMS_SRC_SEL

#define ADE9000_RMS_SRC_SEL   NO_OS_BIT(7)

◆ ADE9000_RUN_ON

#define ADE9000_RUN_ON   0x0001

◆ ADE9000_SELFREQ

#define ADE9000_SELFREQ   NO_OS_BIT(8)

◆ ADE9000_SPI_READ

#define ADE9000_SPI_READ   NO_OS_BIT(3)

◆ ADE9000_STATUS0_CF1

#define ADE9000_STATUS0_CF1   NO_OS_BIT(11)

◆ ADE9000_STATUS0_CF2

#define ADE9000_STATUS0_CF2   NO_OS_BIT(12)

◆ ADE9000_STATUS0_CF3

#define ADE9000_STATUS0_CF3   NO_OS_BIT(13)

◆ ADE9000_STATUS0_CF4

#define ADE9000_STATUS0_CF4   NO_OS_BIT(14)

◆ ADE9000_STATUS0_COH_PAGE_RDY

#define ADE9000_STATUS0_COH_PAGE_RDY   NO_OS_BIT(23)

◆ ADE9000_STATUS0_DREADY

#define ADE9000_STATUS0_DREADY   NO_OS_BIT(15)

◆ ADE9000_STATUS0_EGYRDY

#define ADE9000_STATUS0_EGYRDY   NO_OS_BIT(0)

◆ ADE9000_STATUS0_MISMTCH

#define ADE9000_STATUS0_MISMTCH   NO_OS_BIT(24)

◆ ADE9000_STATUS0_PAGE_FULL

#define ADE9000_STATUS0_PAGE_FULL   NO_OS_BIT(17)

◆ ADE9000_STATUS0_PWRRDY

#define ADE9000_STATUS0_PWRRDY   NO_OS_BIT(18)

◆ ADE9000_STATUS0_REVAPA

#define ADE9000_STATUS0_REVAPA   NO_OS_BIT(1)

◆ ADE9000_STATUS0_REVAPB

#define ADE9000_STATUS0_REVAPB   NO_OS_BIT(2)

◆ ADE9000_STATUS0_REVAPC

#define ADE9000_STATUS0_REVAPC   NO_OS_BIT(3)

◆ ADE9000_STATUS0_REVPSUM1

#define ADE9000_STATUS0_REVPSUM1   NO_OS_BIT(7)

◆ ADE9000_STATUS0_REVPSUM2

#define ADE9000_STATUS0_REVPSUM2   NO_OS_BIT(8)

◆ ADE9000_STATUS0_REVPSUM3

#define ADE9000_STATUS0_REVPSUM3   NO_OS_BIT(9)

◆ ADE9000_STATUS0_REVPSUM4

#define ADE9000_STATUS0_REVPSUM4   NO_OS_BIT(10)

◆ ADE9000_STATUS0_REVRPA

#define ADE9000_STATUS0_REVRPA   NO_OS_BIT(4)

◆ ADE9000_STATUS0_REVRPB

#define ADE9000_STATUS0_REVRPB   NO_OS_BIT(5)

◆ ADE9000_STATUS0_REVRPC

#define ADE9000_STATUS0_REVRPC   NO_OS_BIT(6)

◆ ADE9000_STATUS0_RMS1012RDY

#define ADE9000_STATUS0_RMS1012RDY   NO_OS_BIT(20)

◆ ADE9000_STATUS0_RMSONERDY

#define ADE9000_STATUS0_RMSONERDY   NO_OS_BIT(19)

◆ ADE9000_STATUS0_TEMP_RDY

#define ADE9000_STATUS0_TEMP_RDY   NO_OS_BIT(25)

◆ ADE9000_STATUS0_THD_PF_RDY

#define ADE9000_STATUS0_THD_PF_RDY   NO_OS_BIT(21)

◆ ADE9000_STATUS0_WFB_TRIG

#define ADE9000_STATUS0_WFB_TRIG   NO_OS_BIT(22)

◆ ADE9000_STATUS0_WFB_TRIG_IRQ

#define ADE9000_STATUS0_WFB_TRIG_IRQ   NO_OS_BIT(16)

◆ ADE9000_STATUS1_AFNOLOAD

#define ADE9000_STATUS1_AFNOLOAD   NO_OS_BIT(3)

◆ ADE9000_STATUS1_ANLOAD

#define ADE9000_STATUS1_ANLOAD   NO_OS_BIT(0)

◆ ADE9000_STATUS1_CRC_CHG

#define ADE9000_STATUS1_CRC_CHG   NO_OS_BIT(26)

◆ ADE9000_STATUS1_CRC_DONE

#define ADE9000_STATUS1_CRC_DONE   NO_OS_BIT(27)

◆ ADE9000_STATUS1_DIPA

#define ADE9000_STATUS1_DIPA   NO_OS_BIT(23)

◆ ADE9000_STATUS1_DIPB

#define ADE9000_STATUS1_DIPB   NO_OS_BIT(24)

◆ ADE9000_STATUS1_DIPC

#define ADE9000_STATUS1_DIPC   NO_OS_BIT(25)

◆ ADE9000_STATUS1_ERROR0

#define ADE9000_STATUS1_ERROR0   NO_OS_BIT(28)

◆ ADE9000_STATUS1_ERROR1

#define ADE9000_STATUS1_ERROR1   NO_OS_BIT(29)

◆ ADE9000_STATUS1_ERROR2

#define ADE9000_STATUS1_ERROR2   NO_OS_BIT(30)

◆ ADE9000_STATUS1_ERROR3

#define ADE9000_STATUS1_ERROR3   NO_OS_BIT(31)

◆ ADE9000_STATUS1_OI

#define ADE9000_STATUS1_OI   NO_OS_BIT(17)

◆ ADE9000_STATUS1_RFNOLOAD

#define ADE9000_STATUS1_RFNOLOAD   NO_OS_BIT(4)

◆ ADE9000_STATUS1_RNLOAD

#define ADE9000_STATUS1_RNLOAD   NO_OS_BIT(1)

◆ ADE9000_STATUS1_RSTDONE

#define ADE9000_STATUS1_RSTDONE   NO_OS_BIT(16)

◆ ADE9000_STATUS1_SEQERR

#define ADE9000_STATUS1_SEQERR   NO_OS_BIT(18)

◆ ADE9000_STATUS1_SWELLA

#define ADE9000_STATUS1_SWELLA   NO_OS_BIT(20)

◆ ADE9000_STATUS1_SWELLB

#define ADE9000_STATUS1_SWELLB   NO_OS_BIT(21)

◆ ADE9000_STATUS1_SWELLC

#define ADE9000_STATUS1_SWELLC   NO_OS_BIT(22)

◆ ADE9000_STATUS1_VAFNOLOAD

#define ADE9000_STATUS1_VAFNOLOAD   NO_OS_BIT(5)

◆ ADE9000_STATUS1_VANLOAD

#define ADE9000_STATUS1_VANLOAD   NO_OS_BIT(2)

◆ ADE9000_STATUS1_ZXCOMB

#define ADE9000_STATUS1_ZXCOMB   NO_OS_BIT(12)

◆ ADE9000_STATUS1_ZXIA

#define ADE9000_STATUS1_ZXIA   NO_OS_BIT(13)

◆ ADE9000_STATUS1_ZXIB

#define ADE9000_STATUS1_ZXIB   NO_OS_BIT(14)

◆ ADE9000_STATUS1_ZXIC

#define ADE9000_STATUS1_ZXIC   NO_OS_BIT(15)

◆ ADE9000_STATUS1_ZXTOVA

#define ADE9000_STATUS1_ZXTOVA   NO_OS_BIT(6)

◆ ADE9000_STATUS1_ZXTOVB

#define ADE9000_STATUS1_ZXTOVB   NO_OS_BIT(7)

◆ ADE9000_STATUS1_ZXTOVC

#define ADE9000_STATUS1_ZXTOVC   NO_OS_BIT(8)

◆ ADE9000_STATUS1_ZXVA

#define ADE9000_STATUS1_ZXVA   NO_OS_BIT(9)

◆ ADE9000_STATUS1_ZXVB

#define ADE9000_STATUS1_ZXVB   NO_OS_BIT(10)

◆ ADE9000_STATUS1_ZXVC

#define ADE9000_STATUS1_ZXVC   NO_OS_BIT(11)

◆ ADE9000_SUM1SIGN

#define ADE9000_SUM1SIGN   NO_OS_BIT(6)

◆ ADE9000_SUM2SIGN

#define ADE9000_SUM2SIGN   NO_OS_BIT(7)

◆ ADE9000_SUM3SIGN

#define ADE9000_SUM3SIGN   NO_OS_BIT(8)

◆ ADE9000_SUM4SIGN

#define ADE9000_SUM4SIGN   NO_OS_BIT(9)

◆ ADE9000_SWELL

#define ADE9000_SWELL   NO_OS_BIT(1)

◆ ADE9000_SWELLA_VAL

#define ADE9000_SWELLA_VAL   NO_OS_GENMASK(23, 0)

◆ ADE9000_SWELLB_VAL

#define ADE9000_SWELLB_VAL   NO_OS_GENMASK(23, 0)

◆ ADE9000_SWELLC_VAL

#define ADE9000_SWELLC_VAL   NO_OS_GENMASK(23, 0)

◆ ADE9000_SWELLLVL

#define ADE9000_SWELLLVL   NO_OS_GENMASK(23, 0)

◆ ADE9000_SWRST

#define ADE9000_SWRST   NO_OS_BIT(0)

◆ ADE9000_TEMP_CFG

#define ADE9000_TEMP_CFG   0x000C

◆ ADE9000_TEMP_EN

#define ADE9000_TEMP_EN   NO_OS_BIT(2)

◆ ADE9000_TEMP_GAIN

#define ADE9000_TEMP_GAIN   NO_OS_GENMASK(15, 0)

◆ ADE9000_TEMP_OFFSET

#define ADE9000_TEMP_OFFSET   NO_OS_GENMASK(31, 16)

◆ ADE9000_TEMP_RESULT

#define ADE9000_TEMP_RESULT   NO_OS_GENMASK(11, 0)

◆ ADE9000_TEMP_START

#define ADE9000_TEMP_START   NO_OS_BIT(3)

◆ ADE9000_TEMP_TIME

#define ADE9000_TEMP_TIME   NO_OS_GENMASK(1, 0)

◆ ADE9000_TERMSEL1

#define ADE9000_TERMSEL1   NO_OS_GENMASK(2, 0)

◆ ADE9000_TERMSEL2

#define ADE9000_TERMSEL2   NO_OS_GENMASK(5, 3)

◆ ADE9000_TERMSEL3

#define ADE9000_TERMSEL3   NO_OS_GENMASK(8, 6)

◆ ADE9000_TERMSEL4

#define ADE9000_TERMSEL4   NO_OS_GENMASK(11, 9)

◆ ADE9000_TRIG_FORCE

#define ADE9000_TRIG_FORCE   NO_OS_BIT(10)

◆ ADE9000_UP_RES

#define ADE9000_UP_RES   800000

◆ ADE9000_UPERIOD_SEL

#define ADE9000_UPERIOD_SEL   NO_OS_BIT(12)

◆ ADE9000_VA_DIN

#define ADE9000_VA_DIN   NO_OS_GENMASK(14, 12)

◆ ADE9000_VA_DISADC

#define ADE9000_VA_DISADC   NO_OS_BIT(4)

◆ ADE9000_VA_GAIN

#define ADE9000_VA_GAIN   NO_OS_GENMASK(9, 8)

◆ ADE9000_VARACC

#define ADE9000_VARACC   NO_OS_GENMASK(3, 2)

◆ ADE9000_VARDIS

#define ADE9000_VARDIS   NO_OS_BIT(0)

◆ ADE9000_VB_DIN

#define ADE9000_VB_DIN   NO_OS_GENMASK(17, 15)

◆ ADE9000_VB_DISADC

#define ADE9000_VB_DISADC   NO_OS_BIT(5)

◆ ADE9000_VB_GAIN

#define ADE9000_VB_GAIN   NO_OS_GENMASK(11, 10)

◆ ADE9000_VC_DIN

#define ADE9000_VC_DIN   NO_OS_GENMASK(20, 18)

◆ ADE9000_VC_DISADC

#define ADE9000_VC_DISADC   NO_OS_BIT(6)

◆ ADE9000_VC_GAIN

#define ADE9000_VC_GAIN   NO_OS_GENMASK(13, 12)

◆ ADE9000_VCONSEL

#define ADE9000_VCONSEL   NO_OS_GENMASK(6, 4)

◆ ADE9000_VLEVEL

#define ADE9000_VLEVEL   0x0022EA28

◆ ADE9000_VLEVEL_VAL

#define ADE9000_VLEVEL_VAL   NO_OS_GENMASK(23, 0)

◆ ADE9000_VNOMA_EN

#define ADE9000_VNOMA_EN   NO_OS_BIT(8)

◆ ADE9000_VNOMB_EN

#define ADE9000_VNOMB_EN   NO_OS_BIT(9)

◆ ADE9000_VNOMC_EN

#define ADE9000_VNOMC_EN   NO_OS_BIT(10)

◆ ADE9000_VOLTAGE_TR_FCN

#define ADE9000_VOLTAGE_TR_FCN   ((ADE9000_DOWN_RES + ADE9000_UP_RES) / ADE9000_DOWN_RES)

◆ ADE9000_VPEAKVAL

#define ADE9000_VPEAKVAL   NO_OS_GENMASK(23, 0)

◆ ADE9000_VPPHASE

#define ADE9000_VPPHASE   NO_OS_GENMASK(26, 24)

◆ ADE9000_WATT_FS_CODES

#define ADE9000_WATT_FS_CODES   20694066

◆ ADE9000_WATTACC

#define ADE9000_WATTACC   NO_OS_GENMASK(1, 0)

◆ ADE9000_WF_CAP_EN

#define ADE9000_WF_CAP_EN   NO_OS_BIT(4)

◆ ADE9000_WF_CAP_SEL

#define ADE9000_WF_CAP_SEL   NO_OS_BIT(5)

◆ ADE9000_WF_IN_EN

#define ADE9000_WF_IN_EN   NO_OS_BIT(12)

◆ ADE9000_WF_MODE

#define ADE9000_WF_MODE   NO_OS_BIT(7, 6)

◆ ADE9000_WF_SRC

#define ADE9000_WF_SRC   NO_OS_GENMASK(9, 8)

◆ ADE9000_WFB_CFG

#define ADE9000_WFB_CFG   0x1000

◆ ADE9000_WFB_LAST_PAGE

#define ADE9000_WFB_LAST_PAGE   NO_OS_GENMASK(15, 12)

◆ ADE9000_WFB_TRIG_ADDR

#define ADE9000_WFB_TRIG_ADDR   NO_OS_GENMASK(10, 0)

◆ ADE9000_ZX_LP_SEL

#define ADE9000_ZX_LP_SEL   0x001E

◆ ADE9000_ZX_SEL

#define ADE9000_ZX_SEL   NO_OS_GENMASK(2, 1)

◆ ADE9000_ZX_SRC_SEL

#define ADE9000_ZX_SRC_SEL   NO_OS_BIT(6)

◆ ADE9000_ZXCOMB

#define ADE9000_ZXCOMB   NO_OS_BIT(9)

◆ ADE9000_ZXIA

#define ADE9000_ZXIA   NO_OS_BIT(3)

◆ ADE9000_ZXIB

#define ADE9000_ZXIB   NO_OS_BIT(4)

◆ ADE9000_ZXIC

#define ADE9000_ZXIC   NO_OS_BIT(5)

◆ ADE9000_ZXVA

#define ADE9000_ZXVA   NO_OS_BIT(6)

◆ ADE9000_ZXVB

#define ADE9000_ZXVB   NO_OS_BIT(7)

◆ ADE9000_ZXVC

#define ADE9000_ZXVC   NO_OS_BIT(8)

◆ DISABLE

#define DISABLE   0x0000

◆ ENABLE

#define ENABLE   0x0001

◆ WFB_ELEMENT_ARRAY_SIZE

#define WFB_ELEMENT_ARRAY_SIZE   512

Enumeration Type Documentation

◆ ade9000_aregion_sel_e

enum ade9000_aregion_sel_e

ADE9000 These bits indicate which AIGAINx and APHCALx is currently being used.

Enumerator
ADE9000_AIGAIN_APHCAL_0 
ADE9000_AIGAIN_APHCAL_1 
ADE9000_AIGAIN_APHCAL_2 
ADE9000_AIGAIN_APHCAL_3 
ADE9000_AIGAIN_APHCAL_4 
ADE9000_AIGAIN_APHCAL_DISABLE 

◆ ade9000_bregion_sel_e

enum ade9000_bregion_sel_e

ADE9000 These bits indicate which BIGAINx and BPHCALx is currently being used.

Enumerator
ADE9000_BIGAIN_BPHCAL_0 
ADE9000_BIGAIN_BPHCAL_1 
ADE9000_BIGAIN_BPHCAL_2 
ADE9000_BIGAIN_BPHCAL_3 
ADE9000_BIGAIN_BPHCAL_4 
ADE9000_BIGAIN_BPHCAL_DISABLE 

◆ ade9000_burst_ch_e

enum ade9000_burst_ch_e

Selects which data to read out of the waveform buffer through SPI.

Enumerator
ADE9000_BURST_ALL_CH 
ADE9000_BURST_IA_VA 
ADE9000_BURST_IB_VB 
ADE9000_BURST_IC_VC 
ADE9000_BURST_IA 
ADE9000_BURST_VA 
ADE9000_BURST_IB 
ADE9000_BURST_VB 
ADE9000_BURST_IC 
ADE9000_BURST_VC 
ADE9000_BURST_IN 
ADE9000_BURST_DISABLED 

◆ ade9000_cf3_pin_out_cfg_e

enum ade9000_cf3_pin_out_cfg_e

ADE9000 These bits indicate which function to output on CF3 pin.

Enumerator
ADE9000_CF3_D_F_CONV 
ADE9000_CF3_ZX 

◆ ade9000_cf4_pin_out_cfg_e

enum ade9000_cf4_pin_out_cfg_e

ADE9000 These bits indicate which function to output on CF4 pin.

Enumerator
ADE9000_CF4_D_F_CONV 
ADE9000_CF4_D_F_CONV2 
ADE9000_CF4_EVENT 
ADE9000_CF4_DREADY 

◆ ade9000_cf4_sel_e

enum ade9000_cf4_sel_e

ADE9000 Type of energy output on the CF4 pin. Configure TERMSEL4 in the COMPMODE register to select which phases are included.

Enumerator
ADE9000_CF4_SEL_ACTIV_P 
ADE9000_CF4_SEL_REACTIV_P 
ADE9000_CF4_SEL_APPARENT_P 
ADE9000_CF4_SEL_FUN_ACTIVE_P 
ADE9000_CF4_SEL_FUN_REACTIVE_P 
ADE9000_CF4_SEL_FUN_APPARENT_P 
ADE9000_CF4_SEL_TOTAL_ACTIVE_P 
ADE9000_CF4_SEL_TOTAL_ACTIVE_P_2 

◆ ade9000_cregion_sel_e

enum ade9000_cregion_sel_e

ADE9000 These bits indicate which CIGAINx and CPHCALx is currently being used.

Enumerator
ADE9000_CIGAIN_CPHCAL_0 
ADE9000_CIGAIN_CPHCAL_1 
ADE9000_CIGAIN_CPHCAL_2 
ADE9000_CIGAIN_CPHCAL_3 
ADE9000_CIGAIN_CPHCAL_4 
ADE9000_CIGAIN_CPHCAL_DISABLE 

◆ ade9000_egy_model

enum ade9000_egy_model

ADE9000 available user energy use models.

Enumerator
ADE9000_EGY_WITH_RESET 
ADE9000_EGY_HALF_LINE_CYCLES 
ADE9000_EGY_NR_SAMPLES 

◆ ade9000_freq_sel_e

enum ade9000_freq_sel_e

ADE9000 Freq value.

Enumerator
ADE9000_SELFREQ_50 
ADE9000_SELFREQ_60 

◆ ade9000_hpf_freq_e

enum ade9000_hpf_freq_e

High-pass filter corner (f3dB) enabled when the HPFDIS bit in the CONFIG0 register is equal to zero.

Enumerator
ADE9000_HPF_77_39 
ADE9000_HPF_39_275 
ADE9000_HPF_19_79 
ADE9000_HPF_9_935 
ADE9000_HPF_4_98 
ADE9000_HPF_2_495 
ADE9000_HPF_1_25 
ADE9000_HPF_0_625 

◆ ade9000_isum_cfg_e

enum ade9000_isum_cfg_e

ADE9000 isum calculation configuration.

Enumerator
ADE9000_ISUM_APROX_N 
ADE9000_ISUM_DET_MISM_POS 
ADE9000_ISUM_DET_MISM_NEG 
ADE9000_ISUM_APROX_N_RMS 

◆ ade9000_line_period_sel_e

enum ade9000_line_period_sel_e

Selects line period measurement used for VRMS½ cycle, 10 cycle rms/12 cycle rms, and resampling.

Enumerator
ADE9000_APERIOD 
ADE9000_BPERIOD 
ADE9000_CPERIOD 
ADE9000_COM_PERIOD 

◆ ade9000_no_load_tmr_e

enum ade9000_no_load_tmr_e

This register configures how many 8 kSPS samples to evaluate the no load condition over.

Enumerator
ADE9000_NOLOAD_SAMPLES_64 
ADE9000_NOLOAD_SAMPLES_128 
ADE9000_NOLOAD_SAMPLES_256 
ADE9000_NOLOAD_SAMPLES_512 
ADE9000_NOLOAD_SAMPLES_1024 
ADE9000_NOLOAD_SAMPLES_2048 
ADE9000_NOLOAD_SAMPLES_4096 
ADE9000_NOLOAD_SAMPLES_DISABLE 

◆ ade9000_pga_gain_e

enum ade9000_pga_gain_e

PGA gain.

Enumerator
ADE9000_PGA_GAIN_1 
ADE9000_PGA_GAIN_2 
ADE9000_PGA_GAIN_3 
ADE9000_PGA_GAIN_4 

◆ ade9000_phase

enum ade9000_phase

ADE9000 available phases.

Enumerator
ADE9000_PHASE_A 
ADE9000_PHASE_B 
ADE9000_PHASE_C 

◆ ade9000_temp_time_e

enum ade9000_temp_time_e

Select the number of temperature readings to average.

Enumerator
ADE9000_TEMP_TIME_1 
ADE9000_TEMP_TIME_256 
ADE9000_TEMP_TIME_512 
ADE9000_TEMP_TIME_1024 

◆ ade9000_var_acc_mode_e

enum ade9000_var_acc_mode_e

ADE9000 Total and fundamental reactive power accumulation mode for energy registers and CFx pulses.

Enumerator
ADE9000_ACC_SIGNED 
ADE9000_ACC_ABSOLUTE 
ADE9000_ACC_POSITIVE 
ADE9000_ACC_NEGATIVE 

◆ ade9000_vconsel_e

enum ade9000_vconsel_e

ADE9000 3-wire and 4-wire hardware configuration selection.

Enumerator
ADE9000_4WIRE_WYE 
ADE9000_3WIRE_DELTA 
ADE9000_4WIRE_WYE_VA_VC 
ADE9000_4WIRE_WYE_VA 
ADE9000_3WIRE_DELTA_2 

◆ ade9000_wf_mode_e

enum ade9000_wf_mode_e

Fixed data rate waveforms filling and trigger based modes.

Enumerator
ADE9000_MODE_STOP_FULL 
ADE9000_MODE_TRIG_EN_EVENTS 
ADE9000_MODE_CENTER_CAPTURE 
ADE9000_MODE_SAVE_EVENT_ADDR 

◆ ade9000_wf_src_e

enum ade9000_wf_src_e

Waveform buffer source and DREADY (data ready update rate) selection.

Enumerator
ADE9000_SRC_SINC4 
ADE9000_SRC_SINC4_IIR 
ADE9000_SRC_DSP 

◆ ade9000_zx_select_e

enum ade9000_zx_select_e

Selects the zero-crossing signal, which can be routed to the CF3/ZX output pin and used for line cycle energy accumulation.

Enumerator
ADE9000_ZXVA_SEL 
ADE9000_ZXVB_SEL 
ADE9000_ZXVC_SEL 
ADE9000_ZXCOMB_SEL 

Function Documentation

◆ ade9000_get_int_status0()

int ade9000_get_int_status0 ( struct ade9000_dev *  dev,
uint32_t  msk,
uint8_t *  status 
)

Get interrupt indicator from STATUS0 register.

Parameters
dev- The device structure.
msk- Interrupt mask.
status- Status indicator.
Returns
0 in case of success, negative error code otherwise.
Here is the caller graph for this function:

◆ ade9000_init()

int ade9000_init ( struct ade9000_dev **  device,
struct ade9000_init_param  init_param 
)

Initialize the device.

Parameters
device- The device structure.
init_param- The structure that contains the device initial parameters.
Returns
0 in case of success, negative error code otherwise.
Here is the caller graph for this function:

◆ ade9000_read()

int ade9000_read ( struct ade9000_dev *  dev,
uint16_t  reg_addr,
uint32_t *  reg_data 
)

Read device register.

Parameters
dev- The device structure.
reg_addr- The register address.
reg_data- The data read from the register.
Returns
0 in case of success, negative error code otherwise.
Here is the caller graph for this function:

◆ ade9000_read_data_ph()

int ade9000_read_data_ph ( struct ade9000_dev *  dev,
enum ade9000_phase  phase 
)

Read the power/energy for specific phase.

Parameters
dev- The device structure.
phase- ADE9000 Phase.
Returns
0 in case of success, negative error code otherwise.
Here is the caller graph for this function:

◆ ade9000_read_temp()

int ade9000_read_temp ( struct ade9000_dev *  dev)

Read the temperature.

Parameters
dev- The device structure.
Returns
0 in case of success, negative error code otherwise.
Here is the caller graph for this function:

◆ ade9000_remove()

int ade9000_remove ( struct ade9000_dev *  dev)

Remove the device and release resources.

Parameters
dev- The device structure.
Returns
0 in case of success, negative error code otherwise.

◆ ade9000_set_egy_model()

int ade9000_set_egy_model ( struct ade9000_dev *  dev,
enum ade9000_egy_model  model,
uint16_t  value 
)

Set User Energy use model.

Parameters
dev- The device structure.
model- The User Energy use model to be set.
value- value specific to the user energy use model, it can be either 1 for reading with reset, number of half line cycles or number of samples.
Returns
0 in case of success, negative error code otherwise.

◆ ade9000_setup()

int ade9000_setup ( struct ade9000_dev *  dev)

Setup the device.

Parameters
dev- The device structure.
Returns
0 in case of success, negative error code otherwise.
Here is the caller graph for this function:

◆ ade9000_update_bits()

int ade9000_update_bits ( struct ade9000_dev *  dev,
uint16_t  reg_addr,
uint32_t  mask,
uint32_t  reg_data 
)

Update specific register bits.

Parameters
dev- The device structure.
reg_addr- The register address.
mask- Specific bits mask.
reg_data- The data to be written.
Returns
0 in case of success, negative error code otherwise.
Here is the caller graph for this function:

◆ ade9000_write()

int ade9000_write ( struct ade9000_dev *  dev,
uint16_t  reg_addr,
uint32_t  reg_data 
)

Write device register.

Parameters
dev-The device structure.
reg_addr- The register address.
reg_data- The data to be written.
Returns
0 in case of success, negative error code otherwise.
Here is the caller graph for this function:
Generated by   doxygen 1.8.17