Implementation of ADF4030 Driver. More...

#include <stdint.h>
#include <string.h>
#include "no_os_units.h"
#include "no_os_util.h"
#include "no_os_spi.h"

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Classes
struct	adf4030_chan_spec

struct	adf4030_dev

struct	adf4030_init_param
	ADF4030 Initialization Parameters structure. More...

Macros
#define	ADF4030_SOFT_RESET_R_MSK NO_OS_BIT(7)

#define	ADF4030_LSB_FIRST_R_MSK NO_OS_BIT(6)

#define	ADF4030_ADDRESS_ASC_R_MSK NO_OS_BIT(5)

#define	ADF4030_SDO_ACTIVE_R_MSK NO_OS_BIT(4)

#define	ADF4030_SDO_ACTIVE_MSK NO_OS_BIT(3)

#define	ADF4030_ADDRESS_ASC_MSK NO_OS_BIT(2)

#define	ADF4030_LSB_FIRST_MSK NO_OS_BIT(1)

#define	ADF4030_SOFT_RESET_MSK NO_OS_BIT(0)

#define	ADF4030_RESET_CMD 0x81

#define	ADF4030_CHIP_TYPE 0x06

#define	ADF4030_PRODUCT_ID_LSB 0x0005

#define	ADF4030_PRODUCT_ID_MSB 0x0005

#define	ADF4030_SCRATCHPAD_MSK NO_OS_GENMASK(7, 0)

#define	ADF4030_TDC_TARGET NO_OS_GENMASK(4, 0)

#define	ADF4030_MANUAL_MODE NO_OS_BIT(7)

#define	ADF4030_EN_ALIGN NO_OS_BIT(6)

#define	ADF4030_TDC_SOURCE NO_OS_GENMASK(4, 0)

#define	ADF4030_EN_DRV7 NO_OS_BIT(7)

#define	ADF4030_EN_DRV6 NO_OS_BIT(6)

#define	ADF4030_EN_DRV5 NO_OS_BIT(5)

#define	ADF4030_EN_DRV4 NO_OS_BIT(4)

#define	ADF4030_EN_DRV3 NO_OS_BIT(3)

#define	ADF4030_EN_DRV2 NO_OS_BIT(2)

#define	ADF4030_EN_DRV1 NO_OS_BIT(1)

#define	ADF4030_EN_DRV0 NO_OS_BIT(0)

#define	ADF4030_PRBS5 NO_OS_BIT(7)

#define	ADF4030_PRBS4 NO_OS_BIT(6)

#define	ADF4030_PRBS3 NO_OS_BIT(5)

#define	ADF4030_PRBS2 NO_OS_BIT(4)

#define	ADF4030_PRBS1 NO_OS_BIT(3)

#define	ADF4030_PRBS0 NO_OS_BIT(2)

#define	ADF4030_EN_DRV9 NO_OS_BIT(1)

#define	ADF4030_EN_DRV8 NO_OS_BIT(0)

#define	ADF4030_CHAN_INV3 NO_OS_BIT(7)

#define	ADF4030_CHAN_INV2 NO_OS_BIT(6)

#define	ADF4030_CHAN_INV1 NO_OS_BIT(5)

#define	ADF4030_CHAN_INV0 NO_OS_BIT(4)

#define	ADF4030_PRBS9 NO_OS_BIT(3)

#define	ADF4030_PRBS8 NO_OS_BIT(2)

#define	ADF4030_PRBS7 NO_OS_BIT(1)

#define	ADF4030_PRBS6 NO_OS_BIT(0)

#define	ADF4030_FALL_EDGE_SRC NO_OS_BIT(7)

#define	ADF4030_FALL_EDGE_TGT NO_OS_BIT(6)

#define	ADF4030_CHAN_INV9 NO_OS_BIT(5)

#define	ADF4030_CHAN_INV8 NO_OS_BIT(4)

#define	ADF4030_CHAN_INV7 NO_OS_BIT(3)

#define	ADF4030_CHAN_INV6 NO_OS_BIT(2)

#define	ADF4030_CHAN_INV5 NO_OS_BIT(1)

#define	ADF4030_CHAN_INV4 NO_OS_BIT(0)

#define	ADF4030_TDC_ARM_M NO_OS_BIT(7)

#define	ADF4030_AVGRXP NO_OS_GENMASK(4, 0)

#define	ADF4030_NDEL_ADJ NO_OS_BIT(7)

#define	ADF4030_STOP_FSM NO_OS_BIT(6)

#define	ADF4030_ADEL NO_OS_GENMASK(5, 0)

#define	ADF4030_DELTA_NDEL_COAR_LSB NO_OS_GENMASK(7, 0)

#define	ADF4030_DELTA_NDEL_COAR_MSB NO_OS_GENMASK(7, 0)

#define	ADF4030_TDC_OFFSET_COM_LSB NO_OS_GENMASK(7, 0)

#define	ADF4030_TDC_OFFSET_COM_MID NO_OS_GENMASK(7, 0)

#define	ADF4030_TDC_OFFSET_COM_MSB NO_OS_GENMASK(4, 0)

#define	ADF4030_TDC_OFFSET0_LSB NO_OS_GENMASK(7, 0)

#define	ADF4030_TDC_OFFSET0_MSB NO_OS_GENMASK(7, 0)

#define	ADF4030_TDC_OFFSET1_LSB NO_OS_GENMASK(7, 0)

#define	ADF4030_TDC_OFFSET1_MSB NO_OS_GENMASK(7, 0)

#define	ADF4030_TDC_OFFSET2_LSB NO_OS_GENMASK(7, 0)

#define	ADF4030_TDC_OFFSET2_MSB NO_OS_GENMASK(7, 0)

#define	ADF4030_TDC_OFFSET3_LSB NO_OS_GENMASK(7, 0)

#define	ADF4030_TDC_OFFSET3_MSB NO_OS_GENMASK(7, 0)

#define	ADF4030_TDC_OFFSET4_LSB NO_OS_GENMASK(7, 0)

#define	ADF4030_TDC_OFFSET4_MSB NO_OS_GENMASK(7, 0)

#define	ADF4030_TDC_OFFSET5_LSB NO_OS_GENMASK(7, 0)

#define	ADF4030_TDC_OFFSET5_MSB NO_OS_GENMASK(7, 0)

#define	ADF4030_TDC_OFFSET6_LSB NO_OS_GENMASK(7, 0)

#define	ADF4030_TDC_OFFSET6_MSB NO_OS_GENMASK(7, 0)

#define	ADF4030_TDC_OFFSET7_LSB NO_OS_GENMASK(7, 0)

#define	ADF4030_TDC_OFFSET7_MSB NO_OS_GENMASK(7, 0)

#define	ADF4030_TDC_OFFSET8_LSB NO_OS_GENMASK(7, 0)

#define	ADF4030_TDC_OFFSET8_MSB NO_OS_GENMASK(7, 0)

#define	ADF4030_TDC_OFFSET9_LSB NO_OS_GENMASK(7, 0)

#define	ADF4030_TDC_OFFSET9_MSB NO_OS_GENMASK(7, 0)

#define	ADF4030_ONE_SHOT NO_OS_BIT(7)

#define	ADF4030_CYCLES NO_OS_BIT(6)

#define	ADF4030_DELCAL NO_OS_GENMASK(5, 0)

#define	ADF4030_BSYNC_CAL_ON_1_0 NO_OS_GENMASK(7, 6)

#define	ADF4030_ALIGN_THOLD NO_OS_GENMASK(5, 0)

#define	ADF4030_BSYNC_CAL_ON_9_2 NO_OS_GENMASK(7, 0)

#define	ADF4030_ALIGN_CYCLES NO_OS_GENMASK(7, 5)

#define	ADF4030_AUTO_PF_BG NO_OS_BIT(4)

#define	ADF4030_EN_BKGND_ALGN NO_OS_BIT(3)

#define	ADF4030_EN_SERIAL_ALIGN NO_OS_BIT(2)

#define	ADF4030_EN_CYCS_RED NO_OS_BIT(1)

#define	ADF4030_EN_ITER NO_OS_BIT(0)

#define	ADF4030_RST_BSYNC_CH_7_0 NO_OS_GENMASK(7, 0)

#define	ADF4030_RST_SYS NO_OS_BIT(7)

#define	ADF4030_MSTR_RST_BSYNC NO_OS_BIT(6)

#define	ADF4030_RST_BSYNC_CH_9_8 NO_OS_GENMASK(1, 0)

#define	ADF4030_PD_DRV7 NO_OS_BIT(7)

#define	ADF4030_PD_DRV6 NO_OS_BIT(6)

#define	ADF4030_PD_DRV5 NO_OS_BIT(5)

#define	ADF4030_PD_DRV4 NO_OS_BIT(4)

#define	ADF4030_PD_DRV3 NO_OS_BIT(3)

#define	ADF4030_PD_DRV2 NO_OS_BIT(2)

#define	ADF4030_PD_DRV1 NO_OS_BIT(1)

#define	ADF4030_PD_DRV0 NO_OS_BIT(0)

#define	ADF4030_PD_TX_PATH5 NO_OS_BIT(7)

#define	ADF4030_PD_TX_PATH4 NO_OS_BIT(6)

#define	ADF4030_PD_TX_PATH3 NO_OS_BIT(5)

#define	ADF4030_PD_TX_PATH2 NO_OS_BIT(4)

#define	ADF4030_PD_TX_PATH1 NO_OS_BIT(3)

#define	ADF4030_PD_TX_PATH0 NO_OS_BIT(2)

#define	ADF4030_PD_DRV9 NO_OS_BIT(1)

#define	ADF4030_PD_DRV8 NO_OS_BIT(0)

#define	ADF4030_PD_ALL NO_OS_BIT(7)

#define	ADF4030_PD_PLL NO_OS_BIT(6)

#define	ADF4030_PD_TDC NO_OS_BIT(5)

#define	ADF4030_PD_ADC NO_OS_BIT(4)

#define	ADF4030_PD_TX_PATH9 NO_OS_BIT(3)

#define	ADF4030_PD_TX_PATH8 NO_OS_BIT(2)

#define	ADF4030_PD_TX_PATH7 NO_OS_BIT(1)

#define	ADF4030_PD_TX_PATH6 NO_OS_BIT(0)

#define	ADF4030_ODIV_SEL0 NO_OS_BIT(7)

#define	ADF4030_BOOST0 NO_OS_BIT(6)

#define	ADF4030_RCM0 NO_OS_GENMASK(5, 0)

#define	ADF4030_AUTO_PD_RCV0 NO_OS_BIT(7)

#define	ADF4030_FLOAT_RX0 NO_OS_BIT(5)

#define	ADF4030_FLOAT_TX0 NO_OS_BIT(4)

#define	ADF4030_LINK_RX0 NO_OS_BIT(3)

#define	ADF4030_LINK_TX0 NO_OS_BIT(2)

#define	ADF4030_AC_COUPLED0 NO_OS_BIT(1)

#define	ADF4030_ODIV_SEL1 NO_OS_BIT(7)

#define	ADF4030_BOOST1 NO_OS_BIT(6)

#define	ADF4030_RCM1 NO_OS_GENMASK(5, 0)

#define	ADF4030_AUTO_PD_RCV1 NO_OS_BIT(7)

#define	ADF4030_FLOAT_RX1 NO_OS_BIT(5)

#define	ADF4030_FLOAT_TX1 NO_OS_BIT(4)

#define	ADF4030_LINK_RX1 NO_OS_BIT(3)

#define	ADF4030_LINK_TX1 NO_OS_BIT(2)

#define	ADF4030_AC_COUPLED1 NO_OS_BIT(1)

#define	ADF4030_ODIV_SEL2 NO_OS_BIT(7)

#define	ADF4030_BOOST2 NO_OS_BIT(6)

#define	ADF4030_RCM2 NO_OS_GENMASK(5, 0)

#define	ADF4030_AUTO_PD_RCV2 NO_OS_BIT(7)

#define	ADF4030_FLOAT_RX2 NO_OS_BIT(5)

#define	ADF4030_FLOAT_TX2 NO_OS_BIT(4)

#define	ADF4030_LINK_RX2 NO_OS_BIT(3)

#define	ADF4030_LINK_TX2 NO_OS_BIT(2)

#define	ADF4030_AC_COUPLED2 NO_OS_BIT(1)

#define	ADF4030_ODIV_SEL3 NO_OS_BIT(7)

#define	ADF4030_BOOST3 NO_OS_BIT(6)

#define	ADF4030_RCM3 NO_OS_GENMASK(5, 0)

#define	ADF4030_AUTO_PD_RCV3 NO_OS_BIT(7)

#define	ADF4030_FLOAT_RX3 NO_OS_BIT(5)

#define	ADF4030_FLOAT_TX3 NO_OS_BIT(4)

#define	ADF4030_LINK_RX3 NO_OS_BIT(3)

#define	ADF4030_LINK_TX3 NO_OS_BIT(2)

#define	ADF4030_AC_COUPLED3 NO_OS_BIT(1)

#define	ADF4030_ODIV_SEL4 NO_OS_BIT(7)

#define	ADF4030_BOOST4 NO_OS_BIT(6)

#define	ADF4030_RCM4 NO_OS_GENMASK(5, 0)

#define	ADF4030_AUTO_PD_RCV4 NO_OS_BIT(7)

#define	ADF4030_FLOAT_RX4 NO_OS_BIT(5)

#define	ADF4030_FLOAT_TX4 NO_OS_BIT(4)

#define	ADF4030_LINK_RX4 NO_OS_BIT(3)

#define	ADF4030_LINK_TX4 NO_OS_BIT(2)

#define	ADF4030_AC_COUPLED4 NO_OS_BIT(1)

#define	ADF4030_ODIV_SEL5 NO_OS_BIT(7)

#define	ADF4030_BOOST5 NO_OS_BIT(6)

#define	ADF4030_RCM5 NO_OS_GENMASK(5, 0)

#define	ADF4030_AUTO_PD_RCV5 NO_OS_BIT(7)

#define	ADF4030_FLOAT_RX5 NO_OS_BIT(5)

#define	ADF4030_FLOAT_TX5 NO_OS_BIT(4)

#define	ADF4030_LINK_RX5 NO_OS_BIT(3)

#define	ADF4030_LINK_TX5 NO_OS_BIT(2)

#define	ADF4030_AC_COUPLED5 NO_OS_BIT(1)

#define	ADF4030_ODIV_SEL6 NO_OS_BIT(7)

#define	ADF4030_BOOST6 NO_OS_BIT(6)

#define	ADF4030_RCM6 NO_OS_GENMASK(5, 0)

#define	ADF4030_AUTO_PD_RCV6 NO_OS_BIT(7)

#define	ADF4030_FLOAT_RX6 NO_OS_BIT(5)

#define	ADF4030_FLOAT_TX6 NO_OS_BIT(4)

#define	ADF4030_LINK_RX6 NO_OS_BIT(3)

#define	ADF4030_LINK_TX6 NO_OS_BIT(2)

#define	ADF4030_AC_COUPLED6 NO_OS_BIT(1)

#define	ADF4030_ODIV_SEL7 NO_OS_BIT(7)

#define	ADF4030_BOOST7 NO_OS_BIT(6)

#define	ADF4030_RCM7 NO_OS_GENMASK(5, 0)

#define	ADF4030_AUTO_PD_RCV7 NO_OS_BIT(7)

#define	ADF4030_FLOAT_RX7 NO_OS_BIT(5)

#define	ADF4030_FLOAT_TX7 NO_OS_BIT(4)

#define	ADF4030_LINK_RX7 NO_OS_BIT(3)

#define	ADF4030_LINK_TX7 NO_OS_BIT(2)

#define	ADF4030_AC_COUPLED7 NO_OS_BIT(1)

#define	ADF4030_ODIV_SEL8 NO_OS_BIT(7)

#define	ADF4030_BOOST8 NO_OS_BIT(6)

#define	ADF4030_RCM8 NO_OS_GENMASK(5, 0)

#define	ADF4030_AUTO_PD_RCV8 NO_OS_BIT(7)

#define	ADF4030_FLOAT_RX8 NO_OS_BIT(5)

#define	ADF4030_FLOAT_TX8 NO_OS_BIT(4)

#define	ADF4030_LINK_RX8 NO_OS_BIT(3)

#define	ADF4030_LINK_TX8 NO_OS_BIT(2)

#define	ADF4030_AC_COUPLED8 NO_OS_BIT(1)

#define	ADF4030_ODIV_SEL9 NO_OS_BIT(7)

#define	ADF4030_BOOST9 NO_OS_BIT(6)

#define	ADF4030_RCM9 NO_OS_GENMASK(5, 0)

#define	ADF4030_AUTO_PD_RCV9 NO_OS_BIT(7)

#define	ADF4030_FLOAT_RX9 NO_OS_BIT(5)

#define	ADF4030_FLOAT_TX9 NO_OS_BIT(4)

#define	ADF4030_LINK_RX9 NO_OS_BIT(3)

#define	ADF4030_LINK_TX9 NO_OS_BIT(2)

#define	ADF4030_AC_COUPLED9 NO_OS_BIT(1)

#define	ADF4030_ODIVA_LSB NO_OS_GENMASK(7, 0)

#define	ADF4030_ODIVB_LSB NO_OS_GENMASK(7, 4)

#define	ADF4030_ODIVA_MSB NO_OS_GENMASK(3, 0)

#define	ADF4030_ODIVB_MSB NO_OS_GENMASK(7, 0)

#define	ADF4030_NDIV NO_OS_GENMASK(7, 0)

#define	ADF4030_CP_I NO_OS_GENMASK(6, 5)

#define	ADF4030_RDIV NO_OS_GENMASK(4, 0)

#define	ADF4030_RST_PLL_CAL NO_OS_BIT(7)

#define	ADF4030_PLL_CAL_EN NO_OS_BIT(6)

#define	ADF4030_CMOS_OV NO_OS_BIT(7)

#define	ADF4030_RST_ALIGN_IRQ NO_OS_BIT(5)

#define	ADF4030_RST_TEMP NO_OS_BIT(5)

#define	ADF4030_MASK_TDC_ERR NO_OS_BIT(4)

#define	ADF4030_MASK_LD NO_OS_BIT(3)

#define	ADF4030_MASK_ALIGN_IRQ NO_OS_BIT(2)

#define	ADF4030_MASK_TEMP NO_OS_BIT(1)

#define	ADF4030_IRQB_OPEN_DRAIN NO_OS_BIT(0)

#define	ADF4030_ADC_C_CNV NO_OS_BIT(6)

#define	ADF4030_RST_TDC_ERR NO_OS_BIT(7)

#define	ADF4030_ADC_CLK_SEL NO_OS_BIT(6)

#define	ADF4030_EN_ADC_CNV NO_OS_BIT(2)

#define	ADF4030_EN_ADC_CLK NO_OS_BIT(1)

#define	ADF4030_EN_ADC NO_OS_BIT(0)

#define	ADF4030_MUXCODE1 NO_OS_GENMASK(4, 0)

#define	ADF4030_MUXCODE2 NO_OS_GENMASK(4, 0)

#define	ADF4030_GPO2 NO_OS_BIT(7)

#define	ADF4030_GPO1 NO_OS_BIT(6)

#define	ADF4030_ADC_ST_CNV NO_OS_BIT(0)

#define	ADF4030_TDC_RSLT_UI_LSB NO_OS_GENMASK(7, 0)

#define	ADF4030_TDC_RSLT_UI_MID NO_OS_GENMASK(7, 0)

#define	ADF4030_TDC_RSLT_UI_MSB NO_OS_GENMASK(7, 0)

#define	ADF4030_REF_OK NO_OS_BIT(6)

#define	ADF4030_TDC_BUSY NO_OS_BIT(4)

#define	ADF4030_DL_BUSY NO_OS_BIT(3)

#define	ADF4030_MATH_BUSY NO_OS_BIT(2)

#define	ADF4030_ADC_BUSY NO_OS_BIT(1)

#define	ADF4030_FSM_BUSY NO_OS_BIT(0)

#define	ADF4030_TEMP_MON NO_OS_BIT(4)

#define	ADF4030_TMP_ALIGN_ERR NO_OS_BIT(3)

#define	ADF4030_TDC_ERR NO_OS_GENMASK(2, 1)

#define	ADF4030_PLL_LD NO_OS_BIT(0)

#define	ADF4030_TEMP_MEAS_LSB NO_OS_GENMASK(7, 0)

#define	ADF4030_TEMP_MEAS_MSB NO_OS_BIT(0)

#define	ADF4030_SPI_4W_CFG(x)

#define	ADF4030_SPI_LSB_CFG(x)

#define	ADF4030_SPI_SCRATCHPAD_TEST 0x5A

#define	ADF4030_CHANNEL_TX_PD_SEPARATOR 6

#define	ADF4030_CHANNEL_DRV_SEPARATOR 8

#define	ADF4030_CHANNEL_PRBS_SEPARATOR 6

#define	ADF4030_CHANNEL_INV_SEPARATOR 4

#define	ADF4030_POR_DELAY_US 200

#define	ADF4030_RCM_CONST1 7000

#define	ADF4030_RCM_CONST2 735

#define	ADF4030_RCM_CONST3 10

#define	ADF4030_RCM_CONST4 265

#define	ADF4030_RCM_CURRENT0 14

#define	ADF4030_RCM_CURRENT1 20

#define	ADF4030_RCM_VOLTAGE_MIN0 504

#define	ADF4030_RCM_VOLTAGE_MAX0 1304

#define	ADF4030_RCM_VOLTAGE_MIN1 720

#define	ADF4030_RCM_VOLTAGE_MAX1 1863

#define	ADF4030_SPI_WRITE_CMD 0x0

#define	ADF4030_SPI_READ_CMD 0x8000

#define	ADF4030_CHIP_ADDRESS(x)

#define	ADF4030_SPI_DUMMY_DATA 0x00

#define	ADF4030_BUFF_SIZE_BYTES 3

#define	ADF4030_CHANNEL_NUMBER 10

#define	ADF4030_ADC_CLK_DIV 64U

#define	ADF4030_VCO_FREQ_MIN 2375000000U

#define	ADF4030_VCO_FREQ_MAX 2625000000U

#define	ADF4030_PFD_FREQ_MIN 10000000U

#define	ADF4030_PFD_FREQ_MAX 20000000U

#define	ADF4030_BSYNC_FREQ_MIN 650000U

#define	ADF4030_BSYNC_FREQ_MAX 200000000U

#define	ADF4030_REF_FREQ_MAX 250000000U

#define	ADF4030_REF_FREQ_MIN 10000000

#define	ADF4030_REF_DIV_MAX 31

#define	ADF4030_R_DIV_MIN 1U

#define	ADF4030_R_DIV_MAX 31U

#define	ADF4030_N_DIV_MIN 8U

#define	ADF4030_N_DIV_MAX 255U

#define	ADF4030_O_DIV_MIN 10U

#define	ADF4030_O_DIV_MAX 4095U

#define	ADF4030_ALIGN_CYCLES_MIN (1U)

#define	ADF4030_ALIGN_CYCLES_MAX (8U)

#define	ADF4030_CHIP_ADDRESS_MIN 0U

#define	ADF4030_CHIP_ADDRESS_MAX 15U

Enumerations
enum	adf4030_terminations_e { TX_VOLTAGE_DRIVER = 0 , TX_CURRENT_DRIVER_UNTERMINATED , TX_CURRENT_DRIVER_TERMINATED , RX_DC_COUPLED_CLKS , RX_AC_COUPLED_CLKS , RX_DC_COUPLED_HCSL }

Functions
int	adf4030_spi_write (struct adf4030_dev *dev, uint16_t reg_addr, uint8_t data)
	Writes data to ADF4030 over SPI.

int	adf4030_spi_read (struct adf4030_dev dev, uint16_t reg_addr, uint8_t data)
	Reads data from ADF4030 over SPI.

int	adf4030_spi_update_bits (struct adf4030_dev *dev, uint16_t reg_addr, uint8_t mask, uint8_t data)
	Updates the values of the ADF4030 register.

int	adf4030_set_default_regs (struct adf4030_dev *dev, bool spi_4wire)
	Applys a softreset, sets the SPI 4 wire mode and writes the default registers.

int	adf4030_set_temperature (struct adf4030_dev *dev, bool en)
	Set Temperature Readback feature's initial state. This function should be called before reading temperature to trigger measurement.

int	adf4030_get_temperature (struct adf4030_dev dev, int16_t temperature)
	Gets the value of the approximate die temperature.

int	adf4030_set_chip_address (struct adf4030_dev *dev, uint8_t addr)
	Set the chip address value.

int	adf4030_set_ref_clk (struct adf4030_dev *dev, uint32_t val)
	Set the desired reference frequency and reset everything over to maximum supported value of 250MHz to the max. value and everything under the minimum supported value of 10MHz to the min.

int	adf4030_set_vco_freq (struct adf4030_dev *dev, uint32_t vco_freq)
	Set the desired VCO frequency.

int	adf4030_get_vco_freq (struct adf4030_dev dev, uint32_t vco_freq)
	Get the VCO frequency in Hz.

int	adf4030_set_bsync_freq (struct adf4030_dev *dev, uint32_t bsync_freq, bool odivb_sel)
	Set the BSYNC frequency in Hz. Output divider will be choose according to odiv sel argument.

int	adf4030_get_bsync_freq (struct adf4030_dev dev, uint32_t bsync_freq, bool odivb_sel)
	Get the BSYNC frequency in Hz.

int	adf4030_set_tdc_source (struct adf4030_dev *dev, uint8_t tdc_source)
	Set the TDC source.

int	adf4030_get_tdc_source (struct adf4030_dev dev, uint8_t tdc_source)
	Get the TDC source.

int	adf4030_set_tdc_measurement (struct adf4030_dev *dev, uint8_t tdc_target)
	Set the TDC measurement target and start the measurement. Before calling this function, please set tdc_source to the desired bsync channel.

int	adf4030_get_tdc_measurement (struct adf4030_dev dev, int64_t tdc_result_fs)
	Get the TDC measurement result. Reads bitfileds and calculates the TDC result with period of the BSYNC signal.

int	adf4030_set_alignment_iter (struct adf4030_dev *dev, uint8_t iter_number)
	Set the iteration number of alignment.

int	adf4030_get_alignment_iter (struct adf4030_dev dev, uint8_t iter_number)
	Get the iteration number of alignment.

int	adf4030_set_alignment_threshold (struct adf4030_dev *dev, uint32_t threshold_fs)
	Set the alignment threshold in femtoseconds.

int	adf4030_get_alignment_threshold (struct adf4030_dev dev, uint32_t threshold_fs)
	Get the alignment threshold in femtoseconds.

int	adf4030_set_single_ch_alignment (struct adf4030_dev *dev, uint8_t tdc_target_ch)
	Perform single-channel alignment. Before calling this function, please set tdc_source to the desired bsync channel.

int	adf4030_set_serial_alignment (struct adf4030_dev *dev, uint16_t channel_flags)
	Set serial alignment for multiple BSYNC channels.

int	adf4030_get_serial_alignment (struct adf4030_dev dev, uint16_t channel_flags)
	Get the serial alignment channel flags for multiple BSYNC channels.

int	adf4030_set_background_serial_alignment (struct adf4030_dev *dev, uint16_t channel_flags)
	Set background serial alignment for multiple BSYNC channels.

int	adf4030_get_background_serial_alignment (struct adf4030_dev dev, uint16_t channel_flags)
	Get the background serial alignment channel flags for multiple BSYNC channels.

int	adf4030_set_channel_delay (struct adf4030_dev *dev, uint8_t channel, int64_t delay_fs)
	Set the delay for a specific BSYNC channel. This Delay will show up between TDC_SOURCE and channel.

int	adf4030_get_channel_delay (struct adf4030_dev dev, uint8_t channel, int64_t delay_fs)
	Get the delay for a specific channel.

int	adf4030_set_channel_direction (struct adf4030_dev *dev, uint8_t channel, bool tx_en)
	Set the TX-RX direction of a specific channel.

int	adf4030_get_channel_direction (struct adf4030_dev dev, uint8_t channel, bool tx_en)
	Get the TX direction (TX/RX) of a specific channel.

int	adf4030_set_channel_termination (struct adf4030_dev *dev, uint8_t channel, enum adf4030_terminations_e termination)
	Set the termination type for a specific channel.

int	adf4030_get_channel_termination (struct adf4030_dev dev, uint8_t channel, enum adf4030_terminations_e termination)
	Get the termination type for a specific channel.

int	adf4030_set_channel_prbs (struct adf4030_dev *dev, uint8_t channel, bool prbs_en)
	Set the PRBS (Pseudo-Random Binary Sequence) state for a specific channel.

int	adf4030_get_channel_prbs (struct adf4030_dev dev, uint8_t channel, bool prbs_en)
	Get the PRBS (Pseudo-Random Binary Sequence) state for a specific channel.

int	adf4030_set_channel_odivb (struct adf4030_dev *dev, uint8_t channel, bool odivb_en)
	Set the output divider selection for a specific channel. If odivb_en is enabled, the output divider b will be used for the channel. Otherwise, the output divider a will be used.

int	adf4030_get_channel_odivb (struct adf4030_dev dev, uint8_t channel, bool odivb_en)
	Get the output divider selection for a specific channel. If odivb_en is enabled, the output divider b will be used for the channel. Otherwise, the output divider a will be used.

int	adf4030_set_channel_invert (struct adf4030_dev *dev, uint8_t channel, bool invert_en)
	Set the inversion state for the BSYNC channel.

int	adf4030_get_channel_invert (struct adf4030_dev dev, uint8_t channel, bool invert_en)
	Get the inversion state for a specific channel.

int	adf4030_set_channel_voltage (struct adf4030_dev *dev, uint8_t channel, uint32_t voltage_mv)
	Set the voltage level for the BSYNC channel.

int	adf4030_get_channel_voltage (struct adf4030_dev dev, uint8_t channel, uint32_t voltage_mv)
	Get the voltage level for a specific channel.

int	adf4030_init (struct adf4030_dev *dev, struct adf4030_init_param init_param)
	Initializes the adf4030.

int	adf4030_remove (struct adf4030_dev *dev)
	Free resources allocated for adf4030.

Detailed Description

Implementation of ADF4030 Driver.

Author: Sirac Kucukarabacioglu (sirac.nosp@m..kuc.nosp@m.ukara.nosp@m.baci.nosp@m.oglu@.nosp@m.anal.nosp@m.og.co.nosp@m.m)

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
Neither the name of Analog Devices, Inc. nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Macro Definition Documentation

◆ ADF4030_AC_COUPLED0

#define ADF4030_AC_COUPLED0 NO_OS_BIT(1)

◆ ADF4030_AC_COUPLED1

#define ADF4030_AC_COUPLED1 NO_OS_BIT(1)

◆ ADF4030_AC_COUPLED2

#define ADF4030_AC_COUPLED2 NO_OS_BIT(1)

◆ ADF4030_AC_COUPLED3

#define ADF4030_AC_COUPLED3 NO_OS_BIT(1)

◆ ADF4030_AC_COUPLED4

#define ADF4030_AC_COUPLED4 NO_OS_BIT(1)

◆ ADF4030_AC_COUPLED5

#define ADF4030_AC_COUPLED5 NO_OS_BIT(1)

◆ ADF4030_AC_COUPLED6

#define ADF4030_AC_COUPLED6 NO_OS_BIT(1)

◆ ADF4030_AC_COUPLED7

#define ADF4030_AC_COUPLED7 NO_OS_BIT(1)

◆ ADF4030_AC_COUPLED8

#define ADF4030_AC_COUPLED8 NO_OS_BIT(1)

◆ ADF4030_AC_COUPLED9

#define ADF4030_AC_COUPLED9 NO_OS_BIT(1)

◆ ADF4030_ADC_BUSY

#define ADF4030_ADC_BUSY NO_OS_BIT(1)

◆ ADF4030_ADC_C_CNV

#define ADF4030_ADC_C_CNV NO_OS_BIT(6)

◆ ADF4030_ADC_CLK_DIV

#define ADF4030_ADC_CLK_DIV 64U

◆ ADF4030_ADC_CLK_SEL

#define ADF4030_ADC_CLK_SEL NO_OS_BIT(6)

◆ ADF4030_ADC_ST_CNV

#define ADF4030_ADC_ST_CNV NO_OS_BIT(0)

◆ ADF4030_ADDRESS_ASC_MSK

#define ADF4030_ADDRESS_ASC_MSK NO_OS_BIT(2)

◆ ADF4030_ADDRESS_ASC_R_MSK

#define ADF4030_ADDRESS_ASC_R_MSK NO_OS_BIT(5)

◆ ADF4030_ADEL

#define ADF4030_ADEL NO_OS_GENMASK(5, 0)

◆ ADF4030_ALIGN_CYCLES

#define ADF4030_ALIGN_CYCLES NO_OS_GENMASK(7, 5)

◆ ADF4030_ALIGN_CYCLES_MAX

#define ADF4030_ALIGN_CYCLES_MAX (8U)

◆ ADF4030_ALIGN_CYCLES_MIN

#define ADF4030_ALIGN_CYCLES_MIN (1U)

◆ ADF4030_ALIGN_THOLD

#define ADF4030_ALIGN_THOLD NO_OS_GENMASK(5, 0)

◆ ADF4030_AUTO_PD_RCV0

#define ADF4030_AUTO_PD_RCV0 NO_OS_BIT(7)

◆ ADF4030_AUTO_PD_RCV1

#define ADF4030_AUTO_PD_RCV1 NO_OS_BIT(7)

◆ ADF4030_AUTO_PD_RCV2

#define ADF4030_AUTO_PD_RCV2 NO_OS_BIT(7)

◆ ADF4030_AUTO_PD_RCV3

#define ADF4030_AUTO_PD_RCV3 NO_OS_BIT(7)

◆ ADF4030_AUTO_PD_RCV4

#define ADF4030_AUTO_PD_RCV4 NO_OS_BIT(7)

◆ ADF4030_AUTO_PD_RCV5

#define ADF4030_AUTO_PD_RCV5 NO_OS_BIT(7)

◆ ADF4030_AUTO_PD_RCV6

#define ADF4030_AUTO_PD_RCV6 NO_OS_BIT(7)

◆ ADF4030_AUTO_PD_RCV7

#define ADF4030_AUTO_PD_RCV7 NO_OS_BIT(7)

◆ ADF4030_AUTO_PD_RCV8

#define ADF4030_AUTO_PD_RCV8 NO_OS_BIT(7)

◆ ADF4030_AUTO_PD_RCV9

#define ADF4030_AUTO_PD_RCV9 NO_OS_BIT(7)

◆ ADF4030_AUTO_PF_BG

#define ADF4030_AUTO_PF_BG NO_OS_BIT(4)

◆ ADF4030_AVGRXP

#define ADF4030_AVGRXP NO_OS_GENMASK(4, 0)

◆ ADF4030_BOOST0

#define ADF4030_BOOST0 NO_OS_BIT(6)

◆ ADF4030_BOOST1

#define ADF4030_BOOST1 NO_OS_BIT(6)

◆ ADF4030_BOOST2

#define ADF4030_BOOST2 NO_OS_BIT(6)

◆ ADF4030_BOOST3

#define ADF4030_BOOST3 NO_OS_BIT(6)

◆ ADF4030_BOOST4

#define ADF4030_BOOST4 NO_OS_BIT(6)

◆ ADF4030_BOOST5

#define ADF4030_BOOST5 NO_OS_BIT(6)

◆ ADF4030_BOOST6

#define ADF4030_BOOST6 NO_OS_BIT(6)

◆ ADF4030_BOOST7

#define ADF4030_BOOST7 NO_OS_BIT(6)

◆ ADF4030_BOOST8

#define ADF4030_BOOST8 NO_OS_BIT(6)

◆ ADF4030_BOOST9

#define ADF4030_BOOST9 NO_OS_BIT(6)

◆ ADF4030_BSYNC_CAL_ON_1_0

#define ADF4030_BSYNC_CAL_ON_1_0 NO_OS_GENMASK(7, 6)

◆ ADF4030_BSYNC_CAL_ON_9_2

#define ADF4030_BSYNC_CAL_ON_9_2 NO_OS_GENMASK(7, 0)

◆ ADF4030_BSYNC_FREQ_MAX

#define ADF4030_BSYNC_FREQ_MAX 200000000U

◆ ADF4030_BSYNC_FREQ_MIN

#define ADF4030_BSYNC_FREQ_MIN 650000U

◆ ADF4030_BUFF_SIZE_BYTES

#define ADF4030_BUFF_SIZE_BYTES 3

◆ ADF4030_CHAN_INV0

#define ADF4030_CHAN_INV0 NO_OS_BIT(4)

◆ ADF4030_CHAN_INV1

#define ADF4030_CHAN_INV1 NO_OS_BIT(5)

◆ ADF4030_CHAN_INV2

#define ADF4030_CHAN_INV2 NO_OS_BIT(6)

◆ ADF4030_CHAN_INV3

#define ADF4030_CHAN_INV3 NO_OS_BIT(7)

◆ ADF4030_CHAN_INV4

#define ADF4030_CHAN_INV4 NO_OS_BIT(0)

◆ ADF4030_CHAN_INV5

#define ADF4030_CHAN_INV5 NO_OS_BIT(1)

◆ ADF4030_CHAN_INV6

#define ADF4030_CHAN_INV6 NO_OS_BIT(2)

◆ ADF4030_CHAN_INV7

#define ADF4030_CHAN_INV7 NO_OS_BIT(3)

◆ ADF4030_CHAN_INV8

#define ADF4030_CHAN_INV8 NO_OS_BIT(4)

◆ ADF4030_CHAN_INV9

#define ADF4030_CHAN_INV9 NO_OS_BIT(5)

◆ ADF4030_CHANNEL_DRV_SEPARATOR

#define ADF4030_CHANNEL_DRV_SEPARATOR 8

◆ ADF4030_CHANNEL_INV_SEPARATOR

#define ADF4030_CHANNEL_INV_SEPARATOR 4

◆ ADF4030_CHANNEL_NUMBER

#define ADF4030_CHANNEL_NUMBER 10

◆ ADF4030_CHANNEL_PRBS_SEPARATOR

#define ADF4030_CHANNEL_PRBS_SEPARATOR 6

◆ ADF4030_CHANNEL_TX_PD_SEPARATOR

#define ADF4030_CHANNEL_TX_PD_SEPARATOR 6

◆ ADF4030_CHIP_ADDRESS

#define ADF4030_CHIP_ADDRESS ( x )

Value:

(x << 9)

◆ ADF4030_CHIP_ADDRESS_MAX

#define ADF4030_CHIP_ADDRESS_MAX 15U

◆ ADF4030_CHIP_ADDRESS_MIN

#define ADF4030_CHIP_ADDRESS_MIN 0U

◆ ADF4030_CHIP_TYPE

#define ADF4030_CHIP_TYPE 0x06

◆ ADF4030_CMOS_OV

#define ADF4030_CMOS_OV NO_OS_BIT(7)

◆ ADF4030_CP_I

#define ADF4030_CP_I NO_OS_GENMASK(6, 5)

◆ ADF4030_CYCLES

#define ADF4030_CYCLES NO_OS_BIT(6)

◆ ADF4030_DELCAL

#define ADF4030_DELCAL NO_OS_GENMASK(5, 0)

◆ ADF4030_DELTA_NDEL_COAR_LSB

#define ADF4030_DELTA_NDEL_COAR_LSB NO_OS_GENMASK(7, 0)

◆ ADF4030_DELTA_NDEL_COAR_MSB

#define ADF4030_DELTA_NDEL_COAR_MSB NO_OS_GENMASK(7, 0)

◆ ADF4030_DL_BUSY

#define ADF4030_DL_BUSY NO_OS_BIT(3)

◆ ADF4030_EN_ADC

#define ADF4030_EN_ADC NO_OS_BIT(0)

◆ ADF4030_EN_ADC_CLK

#define ADF4030_EN_ADC_CLK NO_OS_BIT(1)

◆ ADF4030_EN_ADC_CNV

#define ADF4030_EN_ADC_CNV NO_OS_BIT(2)

◆ ADF4030_EN_ALIGN

#define ADF4030_EN_ALIGN NO_OS_BIT(6)

◆ ADF4030_EN_BKGND_ALGN

#define ADF4030_EN_BKGND_ALGN NO_OS_BIT(3)

◆ ADF4030_EN_CYCS_RED

#define ADF4030_EN_CYCS_RED NO_OS_BIT(1)

◆ ADF4030_EN_DRV0

#define ADF4030_EN_DRV0 NO_OS_BIT(0)

◆ ADF4030_EN_DRV1

#define ADF4030_EN_DRV1 NO_OS_BIT(1)

◆ ADF4030_EN_DRV2

#define ADF4030_EN_DRV2 NO_OS_BIT(2)

◆ ADF4030_EN_DRV3

#define ADF4030_EN_DRV3 NO_OS_BIT(3)

◆ ADF4030_EN_DRV4

#define ADF4030_EN_DRV4 NO_OS_BIT(4)

◆ ADF4030_EN_DRV5

#define ADF4030_EN_DRV5 NO_OS_BIT(5)

◆ ADF4030_EN_DRV6

#define ADF4030_EN_DRV6 NO_OS_BIT(6)

◆ ADF4030_EN_DRV7

#define ADF4030_EN_DRV7 NO_OS_BIT(7)

◆ ADF4030_EN_DRV8

#define ADF4030_EN_DRV8 NO_OS_BIT(0)

◆ ADF4030_EN_DRV9

#define ADF4030_EN_DRV9 NO_OS_BIT(1)

◆ ADF4030_EN_ITER

#define ADF4030_EN_ITER NO_OS_BIT(0)

◆ ADF4030_EN_SERIAL_ALIGN

#define ADF4030_EN_SERIAL_ALIGN NO_OS_BIT(2)

◆ ADF4030_FALL_EDGE_SRC

#define ADF4030_FALL_EDGE_SRC NO_OS_BIT(7)

◆ ADF4030_FALL_EDGE_TGT

#define ADF4030_FALL_EDGE_TGT NO_OS_BIT(6)

◆ ADF4030_FLOAT_RX0

#define ADF4030_FLOAT_RX0 NO_OS_BIT(5)

◆ ADF4030_FLOAT_RX1

#define ADF4030_FLOAT_RX1 NO_OS_BIT(5)

◆ ADF4030_FLOAT_RX2

#define ADF4030_FLOAT_RX2 NO_OS_BIT(5)

◆ ADF4030_FLOAT_RX3

#define ADF4030_FLOAT_RX3 NO_OS_BIT(5)

◆ ADF4030_FLOAT_RX4

#define ADF4030_FLOAT_RX4 NO_OS_BIT(5)

◆ ADF4030_FLOAT_RX5

#define ADF4030_FLOAT_RX5 NO_OS_BIT(5)

◆ ADF4030_FLOAT_RX6

#define ADF4030_FLOAT_RX6 NO_OS_BIT(5)

◆ ADF4030_FLOAT_RX7

#define ADF4030_FLOAT_RX7 NO_OS_BIT(5)

◆ ADF4030_FLOAT_RX8

#define ADF4030_FLOAT_RX8 NO_OS_BIT(5)

◆ ADF4030_FLOAT_RX9

#define ADF4030_FLOAT_RX9 NO_OS_BIT(5)

◆ ADF4030_FLOAT_TX0

#define ADF4030_FLOAT_TX0 NO_OS_BIT(4)

◆ ADF4030_FLOAT_TX1

#define ADF4030_FLOAT_TX1 NO_OS_BIT(4)

◆ ADF4030_FLOAT_TX2

#define ADF4030_FLOAT_TX2 NO_OS_BIT(4)

◆ ADF4030_FLOAT_TX3

#define ADF4030_FLOAT_TX3 NO_OS_BIT(4)

◆ ADF4030_FLOAT_TX4

#define ADF4030_FLOAT_TX4 NO_OS_BIT(4)

◆ ADF4030_FLOAT_TX5

#define ADF4030_FLOAT_TX5 NO_OS_BIT(4)

◆ ADF4030_FLOAT_TX6

#define ADF4030_FLOAT_TX6 NO_OS_BIT(4)

◆ ADF4030_FLOAT_TX7

#define ADF4030_FLOAT_TX7 NO_OS_BIT(4)

◆ ADF4030_FLOAT_TX8

#define ADF4030_FLOAT_TX8 NO_OS_BIT(4)

◆ ADF4030_FLOAT_TX9

#define ADF4030_FLOAT_TX9 NO_OS_BIT(4)

◆ ADF4030_FSM_BUSY

#define ADF4030_FSM_BUSY NO_OS_BIT(0)

◆ ADF4030_GPO1

#define ADF4030_GPO1 NO_OS_BIT(6)

◆ ADF4030_GPO2

#define ADF4030_GPO2 NO_OS_BIT(7)

◆ ADF4030_IRQB_OPEN_DRAIN

#define ADF4030_IRQB_OPEN_DRAIN NO_OS_BIT(0)

◆ ADF4030_LINK_RX0

#define ADF4030_LINK_RX0 NO_OS_BIT(3)

◆ ADF4030_LINK_RX1

#define ADF4030_LINK_RX1 NO_OS_BIT(3)

◆ ADF4030_LINK_RX2

#define ADF4030_LINK_RX2 NO_OS_BIT(3)

◆ ADF4030_LINK_RX3

#define ADF4030_LINK_RX3 NO_OS_BIT(3)

◆ ADF4030_LINK_RX4

#define ADF4030_LINK_RX4 NO_OS_BIT(3)

◆ ADF4030_LINK_RX5

#define ADF4030_LINK_RX5 NO_OS_BIT(3)

◆ ADF4030_LINK_RX6

#define ADF4030_LINK_RX6 NO_OS_BIT(3)

◆ ADF4030_LINK_RX7

#define ADF4030_LINK_RX7 NO_OS_BIT(3)

◆ ADF4030_LINK_RX8

#define ADF4030_LINK_RX8 NO_OS_BIT(3)

◆ ADF4030_LINK_RX9

#define ADF4030_LINK_RX9 NO_OS_BIT(3)

◆ ADF4030_LINK_TX0

#define ADF4030_LINK_TX0 NO_OS_BIT(2)

◆ ADF4030_LINK_TX1

#define ADF4030_LINK_TX1 NO_OS_BIT(2)

◆ ADF4030_LINK_TX2

#define ADF4030_LINK_TX2 NO_OS_BIT(2)

◆ ADF4030_LINK_TX3

#define ADF4030_LINK_TX3 NO_OS_BIT(2)

◆ ADF4030_LINK_TX4

#define ADF4030_LINK_TX4 NO_OS_BIT(2)

◆ ADF4030_LINK_TX5

#define ADF4030_LINK_TX5 NO_OS_BIT(2)

◆ ADF4030_LINK_TX6

#define ADF4030_LINK_TX6 NO_OS_BIT(2)

◆ ADF4030_LINK_TX7

#define ADF4030_LINK_TX7 NO_OS_BIT(2)

◆ ADF4030_LINK_TX8

#define ADF4030_LINK_TX8 NO_OS_BIT(2)

◆ ADF4030_LINK_TX9

#define ADF4030_LINK_TX9 NO_OS_BIT(2)

◆ ADF4030_LSB_FIRST_MSK

#define ADF4030_LSB_FIRST_MSK NO_OS_BIT(1)

◆ ADF4030_LSB_FIRST_R_MSK

#define ADF4030_LSB_FIRST_R_MSK NO_OS_BIT(6)

◆ ADF4030_MANUAL_MODE

#define ADF4030_MANUAL_MODE NO_OS_BIT(7)

◆ ADF4030_MASK_ALIGN_IRQ

#define ADF4030_MASK_ALIGN_IRQ NO_OS_BIT(2)

◆ ADF4030_MASK_LD

#define ADF4030_MASK_LD NO_OS_BIT(3)

◆ ADF4030_MASK_TDC_ERR

#define ADF4030_MASK_TDC_ERR NO_OS_BIT(4)

◆ ADF4030_MASK_TEMP

#define ADF4030_MASK_TEMP NO_OS_BIT(1)

◆ ADF4030_MATH_BUSY

#define ADF4030_MATH_BUSY NO_OS_BIT(2)

◆ ADF4030_MSTR_RST_BSYNC

#define ADF4030_MSTR_RST_BSYNC NO_OS_BIT(6)

◆ ADF4030_MUXCODE1

#define ADF4030_MUXCODE1 NO_OS_GENMASK(4, 0)

◆ ADF4030_MUXCODE2

#define ADF4030_MUXCODE2 NO_OS_GENMASK(4, 0)

◆ ADF4030_N_DIV_MAX

#define ADF4030_N_DIV_MAX 255U

◆ ADF4030_N_DIV_MIN

#define ADF4030_N_DIV_MIN 8U

◆ ADF4030_NDEL_ADJ

#define ADF4030_NDEL_ADJ NO_OS_BIT(7)

◆ ADF4030_NDIV

#define ADF4030_NDIV NO_OS_GENMASK(7, 0)

◆ ADF4030_O_DIV_MAX

#define ADF4030_O_DIV_MAX 4095U

◆ ADF4030_O_DIV_MIN

#define ADF4030_O_DIV_MIN 10U

◆ ADF4030_ODIV_SEL0

#define ADF4030_ODIV_SEL0 NO_OS_BIT(7)

◆ ADF4030_ODIV_SEL1

#define ADF4030_ODIV_SEL1 NO_OS_BIT(7)

◆ ADF4030_ODIV_SEL2

#define ADF4030_ODIV_SEL2 NO_OS_BIT(7)

◆ ADF4030_ODIV_SEL3

#define ADF4030_ODIV_SEL3 NO_OS_BIT(7)

◆ ADF4030_ODIV_SEL4

#define ADF4030_ODIV_SEL4 NO_OS_BIT(7)

◆ ADF4030_ODIV_SEL5

#define ADF4030_ODIV_SEL5 NO_OS_BIT(7)

◆ ADF4030_ODIV_SEL6

#define ADF4030_ODIV_SEL6 NO_OS_BIT(7)

◆ ADF4030_ODIV_SEL7

#define ADF4030_ODIV_SEL7 NO_OS_BIT(7)

◆ ADF4030_ODIV_SEL8

#define ADF4030_ODIV_SEL8 NO_OS_BIT(7)

◆ ADF4030_ODIV_SEL9

#define ADF4030_ODIV_SEL9 NO_OS_BIT(7)

◆ ADF4030_ODIVA_LSB

#define ADF4030_ODIVA_LSB NO_OS_GENMASK(7, 0)

◆ ADF4030_ODIVA_MSB

#define ADF4030_ODIVA_MSB NO_OS_GENMASK(3, 0)

◆ ADF4030_ODIVB_LSB

#define ADF4030_ODIVB_LSB NO_OS_GENMASK(7, 4)

◆ ADF4030_ODIVB_MSB

#define ADF4030_ODIVB_MSB NO_OS_GENMASK(7, 0)

◆ ADF4030_ONE_SHOT

#define ADF4030_ONE_SHOT NO_OS_BIT(7)

◆ ADF4030_PD_ADC

#define ADF4030_PD_ADC NO_OS_BIT(4)

◆ ADF4030_PD_ALL

#define ADF4030_PD_ALL NO_OS_BIT(7)

◆ ADF4030_PD_DRV0

#define ADF4030_PD_DRV0 NO_OS_BIT(0)

◆ ADF4030_PD_DRV1

#define ADF4030_PD_DRV1 NO_OS_BIT(1)

◆ ADF4030_PD_DRV2

#define ADF4030_PD_DRV2 NO_OS_BIT(2)

◆ ADF4030_PD_DRV3

#define ADF4030_PD_DRV3 NO_OS_BIT(3)

◆ ADF4030_PD_DRV4

#define ADF4030_PD_DRV4 NO_OS_BIT(4)

◆ ADF4030_PD_DRV5

#define ADF4030_PD_DRV5 NO_OS_BIT(5)

◆ ADF4030_PD_DRV6

#define ADF4030_PD_DRV6 NO_OS_BIT(6)

◆ ADF4030_PD_DRV7

#define ADF4030_PD_DRV7 NO_OS_BIT(7)

◆ ADF4030_PD_DRV8

#define ADF4030_PD_DRV8 NO_OS_BIT(0)

◆ ADF4030_PD_DRV9

#define ADF4030_PD_DRV9 NO_OS_BIT(1)

◆ ADF4030_PD_PLL

#define ADF4030_PD_PLL NO_OS_BIT(6)

◆ ADF4030_PD_TDC

#define ADF4030_PD_TDC NO_OS_BIT(5)

◆ ADF4030_PD_TX_PATH0

#define ADF4030_PD_TX_PATH0 NO_OS_BIT(2)

◆ ADF4030_PD_TX_PATH1

#define ADF4030_PD_TX_PATH1 NO_OS_BIT(3)

◆ ADF4030_PD_TX_PATH2

#define ADF4030_PD_TX_PATH2 NO_OS_BIT(4)

◆ ADF4030_PD_TX_PATH3

#define ADF4030_PD_TX_PATH3 NO_OS_BIT(5)

◆ ADF4030_PD_TX_PATH4

#define ADF4030_PD_TX_PATH4 NO_OS_BIT(6)

◆ ADF4030_PD_TX_PATH5

#define ADF4030_PD_TX_PATH5 NO_OS_BIT(7)

◆ ADF4030_PD_TX_PATH6

#define ADF4030_PD_TX_PATH6 NO_OS_BIT(0)

◆ ADF4030_PD_TX_PATH7

#define ADF4030_PD_TX_PATH7 NO_OS_BIT(1)

◆ ADF4030_PD_TX_PATH8

#define ADF4030_PD_TX_PATH8 NO_OS_BIT(2)

◆ ADF4030_PD_TX_PATH9

#define ADF4030_PD_TX_PATH9 NO_OS_BIT(3)

◆ ADF4030_PFD_FREQ_MAX

#define ADF4030_PFD_FREQ_MAX 20000000U

◆ ADF4030_PFD_FREQ_MIN

#define ADF4030_PFD_FREQ_MIN 10000000U

◆ ADF4030_PLL_CAL_EN

#define ADF4030_PLL_CAL_EN NO_OS_BIT(6)

◆ ADF4030_PLL_LD

#define ADF4030_PLL_LD NO_OS_BIT(0)

◆ ADF4030_POR_DELAY_US

#define ADF4030_POR_DELAY_US 200

◆ ADF4030_PRBS0

#define ADF4030_PRBS0 NO_OS_BIT(2)

◆ ADF4030_PRBS1

#define ADF4030_PRBS1 NO_OS_BIT(3)

◆ ADF4030_PRBS2

#define ADF4030_PRBS2 NO_OS_BIT(4)

◆ ADF4030_PRBS3

#define ADF4030_PRBS3 NO_OS_BIT(5)

◆ ADF4030_PRBS4

#define ADF4030_PRBS4 NO_OS_BIT(6)

◆ ADF4030_PRBS5

#define ADF4030_PRBS5 NO_OS_BIT(7)

◆ ADF4030_PRBS6

#define ADF4030_PRBS6 NO_OS_BIT(0)

◆ ADF4030_PRBS7

#define ADF4030_PRBS7 NO_OS_BIT(1)

◆ ADF4030_PRBS8

#define ADF4030_PRBS8 NO_OS_BIT(2)

◆ ADF4030_PRBS9

#define ADF4030_PRBS9 NO_OS_BIT(3)

◆ ADF4030_PRODUCT_ID_LSB

#define ADF4030_PRODUCT_ID_LSB 0x0005

◆ ADF4030_PRODUCT_ID_MSB

#define ADF4030_PRODUCT_ID_MSB 0x0005

◆ ADF4030_R_DIV_MAX

#define ADF4030_R_DIV_MAX 31U

◆ ADF4030_R_DIV_MIN

#define ADF4030_R_DIV_MIN 1U

◆ ADF4030_RCM0

#define ADF4030_RCM0 NO_OS_GENMASK(5, 0)

◆ ADF4030_RCM1

#define ADF4030_RCM1 NO_OS_GENMASK(5, 0)

◆ ADF4030_RCM2

#define ADF4030_RCM2 NO_OS_GENMASK(5, 0)

◆ ADF4030_RCM3

#define ADF4030_RCM3 NO_OS_GENMASK(5, 0)

◆ ADF4030_RCM4

#define ADF4030_RCM4 NO_OS_GENMASK(5, 0)

◆ ADF4030_RCM5

#define ADF4030_RCM5 NO_OS_GENMASK(5, 0)

◆ ADF4030_RCM6

#define ADF4030_RCM6 NO_OS_GENMASK(5, 0)

◆ ADF4030_RCM7

#define ADF4030_RCM7 NO_OS_GENMASK(5, 0)

◆ ADF4030_RCM8

#define ADF4030_RCM8 NO_OS_GENMASK(5, 0)

◆ ADF4030_RCM9

#define ADF4030_RCM9 NO_OS_GENMASK(5, 0)

◆ ADF4030_RCM_CONST1

#define ADF4030_RCM_CONST1 7000

◆ ADF4030_RCM_CONST2

#define ADF4030_RCM_CONST2 735

◆ ADF4030_RCM_CONST3

#define ADF4030_RCM_CONST3 10

◆ ADF4030_RCM_CONST4

#define ADF4030_RCM_CONST4 265

◆ ADF4030_RCM_CURRENT0

#define ADF4030_RCM_CURRENT0 14

◆ ADF4030_RCM_CURRENT1

#define ADF4030_RCM_CURRENT1 20

◆ ADF4030_RCM_VOLTAGE_MAX0

#define ADF4030_RCM_VOLTAGE_MAX0 1304

◆ ADF4030_RCM_VOLTAGE_MAX1

#define ADF4030_RCM_VOLTAGE_MAX1 1863

◆ ADF4030_RCM_VOLTAGE_MIN0

#define ADF4030_RCM_VOLTAGE_MIN0 504

◆ ADF4030_RCM_VOLTAGE_MIN1

#define ADF4030_RCM_VOLTAGE_MIN1 720

◆ ADF4030_RDIV

#define ADF4030_RDIV NO_OS_GENMASK(4, 0)

◆ ADF4030_REF_DIV_MAX

#define ADF4030_REF_DIV_MAX 31

◆ ADF4030_REF_FREQ_MAX

#define ADF4030_REF_FREQ_MAX 250000000U

◆ ADF4030_REF_FREQ_MIN

#define ADF4030_REF_FREQ_MIN 10000000

◆ ADF4030_REF_OK

#define ADF4030_REF_OK NO_OS_BIT(6)

◆ ADF4030_RESET_CMD

#define ADF4030_RESET_CMD 0x81

◆ ADF4030_RST_ALIGN_IRQ

#define ADF4030_RST_ALIGN_IRQ NO_OS_BIT(5)

◆ ADF4030_RST_BSYNC_CH_7_0

#define ADF4030_RST_BSYNC_CH_7_0 NO_OS_GENMASK(7, 0)

◆ ADF4030_RST_BSYNC_CH_9_8

#define ADF4030_RST_BSYNC_CH_9_8 NO_OS_GENMASK(1, 0)

◆ ADF4030_RST_PLL_CAL

#define ADF4030_RST_PLL_CAL NO_OS_BIT(7)

◆ ADF4030_RST_SYS

#define ADF4030_RST_SYS NO_OS_BIT(7)

◆ ADF4030_RST_TDC_ERR

#define ADF4030_RST_TDC_ERR NO_OS_BIT(7)

◆ ADF4030_RST_TEMP

#define ADF4030_RST_TEMP NO_OS_BIT(5)

◆ ADF4030_SCRATCHPAD_MSK

#define ADF4030_SCRATCHPAD_MSK NO_OS_GENMASK(7, 0)

◆ ADF4030_SDO_ACTIVE_MSK

#define ADF4030_SDO_ACTIVE_MSK NO_OS_BIT(3)

◆ ADF4030_SDO_ACTIVE_R_MSK

#define ADF4030_SDO_ACTIVE_R_MSK NO_OS_BIT(4)

◆ ADF4030_SOFT_RESET_MSK

#define ADF4030_SOFT_RESET_MSK NO_OS_BIT(0)

◆ ADF4030_SOFT_RESET_R_MSK

#define ADF4030_SOFT_RESET_R_MSK NO_OS_BIT(7)

◆ ADF4030_SPI_4W_CFG

#define ADF4030_SPI_4W_CFG ( x )

Value:

(no_os_field_prep(ADF4030_SDO_ACTIVE_MSK, x) | \

no_os_field_prep(ADF4030_SDO_ACTIVE_R_MSK, x))

ADF4030_SDO_ACTIVE_R_MSK

#define ADF4030_SDO_ACTIVE_R_MSK

Definition adf4030.h:46

ADF4030_SDO_ACTIVE_MSK

#define ADF4030_SDO_ACTIVE_MSK

Definition adf4030.h:47

no_os_field_prep

uint32_t no_os_field_prep(uint32_t mask, uint32_t val)

◆ ADF4030_SPI_DUMMY_DATA

#define ADF4030_SPI_DUMMY_DATA 0x00

◆ ADF4030_SPI_LSB_CFG

#define ADF4030_SPI_LSB_CFG ( x )

Value:

(no_os_field_prep(ADF4030_LSB_FIRST_MSK, x) | \

no_os_field_prep(ADF4030_LSB_FIRST_R_MSK, x))

ADF4030_LSB_FIRST_R_MSK

#define ADF4030_LSB_FIRST_R_MSK

Definition adf4030.h:44

ADF4030_LSB_FIRST_MSK

#define ADF4030_LSB_FIRST_MSK

Definition adf4030.h:49

◆ ADF4030_SPI_READ_CMD

#define ADF4030_SPI_READ_CMD 0x8000

◆ ADF4030_SPI_SCRATCHPAD_TEST

#define ADF4030_SPI_SCRATCHPAD_TEST 0x5A

◆ ADF4030_SPI_WRITE_CMD

#define ADF4030_SPI_WRITE_CMD 0x0

◆ ADF4030_STOP_FSM

#define ADF4030_STOP_FSM NO_OS_BIT(6)

◆ ADF4030_TDC_ARM_M

#define ADF4030_TDC_ARM_M NO_OS_BIT(7)

◆ ADF4030_TDC_BUSY

#define ADF4030_TDC_BUSY NO_OS_BIT(4)

◆ ADF4030_TDC_ERR

#define ADF4030_TDC_ERR NO_OS_GENMASK(2, 1)

◆ ADF4030_TDC_OFFSET0_LSB

#define ADF4030_TDC_OFFSET0_LSB NO_OS_GENMASK(7, 0)

◆ ADF4030_TDC_OFFSET0_MSB

#define ADF4030_TDC_OFFSET0_MSB NO_OS_GENMASK(7, 0)

◆ ADF4030_TDC_OFFSET1_LSB

#define ADF4030_TDC_OFFSET1_LSB NO_OS_GENMASK(7, 0)

◆ ADF4030_TDC_OFFSET1_MSB

#define ADF4030_TDC_OFFSET1_MSB NO_OS_GENMASK(7, 0)

◆ ADF4030_TDC_OFFSET2_LSB

#define ADF4030_TDC_OFFSET2_LSB NO_OS_GENMASK(7, 0)

◆ ADF4030_TDC_OFFSET2_MSB

#define ADF4030_TDC_OFFSET2_MSB NO_OS_GENMASK(7, 0)

◆ ADF4030_TDC_OFFSET3_LSB

#define ADF4030_TDC_OFFSET3_LSB NO_OS_GENMASK(7, 0)

◆ ADF4030_TDC_OFFSET3_MSB

#define ADF4030_TDC_OFFSET3_MSB NO_OS_GENMASK(7, 0)

◆ ADF4030_TDC_OFFSET4_LSB

#define ADF4030_TDC_OFFSET4_LSB NO_OS_GENMASK(7, 0)

◆ ADF4030_TDC_OFFSET4_MSB

#define ADF4030_TDC_OFFSET4_MSB NO_OS_GENMASK(7, 0)

◆ ADF4030_TDC_OFFSET5_LSB

#define ADF4030_TDC_OFFSET5_LSB NO_OS_GENMASK(7, 0)

◆ ADF4030_TDC_OFFSET5_MSB

#define ADF4030_TDC_OFFSET5_MSB NO_OS_GENMASK(7, 0)

◆ ADF4030_TDC_OFFSET6_LSB

#define ADF4030_TDC_OFFSET6_LSB NO_OS_GENMASK(7, 0)

◆ ADF4030_TDC_OFFSET6_MSB

#define ADF4030_TDC_OFFSET6_MSB NO_OS_GENMASK(7, 0)

◆ ADF4030_TDC_OFFSET7_LSB

#define ADF4030_TDC_OFFSET7_LSB NO_OS_GENMASK(7, 0)

◆ ADF4030_TDC_OFFSET7_MSB

#define ADF4030_TDC_OFFSET7_MSB NO_OS_GENMASK(7, 0)

◆ ADF4030_TDC_OFFSET8_LSB

#define ADF4030_TDC_OFFSET8_LSB NO_OS_GENMASK(7, 0)

◆ ADF4030_TDC_OFFSET8_MSB

#define ADF4030_TDC_OFFSET8_MSB NO_OS_GENMASK(7, 0)

◆ ADF4030_TDC_OFFSET9_LSB

#define ADF4030_TDC_OFFSET9_LSB NO_OS_GENMASK(7, 0)

◆ ADF4030_TDC_OFFSET9_MSB

#define ADF4030_TDC_OFFSET9_MSB NO_OS_GENMASK(7, 0)

◆ ADF4030_TDC_OFFSET_COM_LSB

#define ADF4030_TDC_OFFSET_COM_LSB NO_OS_GENMASK(7, 0)

◆ ADF4030_TDC_OFFSET_COM_MID

#define ADF4030_TDC_OFFSET_COM_MID NO_OS_GENMASK(7, 0)

◆ ADF4030_TDC_OFFSET_COM_MSB

#define ADF4030_TDC_OFFSET_COM_MSB NO_OS_GENMASK(4, 0)

◆ ADF4030_TDC_RSLT_UI_LSB

#define ADF4030_TDC_RSLT_UI_LSB NO_OS_GENMASK(7, 0)

◆ ADF4030_TDC_RSLT_UI_MID

#define ADF4030_TDC_RSLT_UI_MID NO_OS_GENMASK(7, 0)

◆ ADF4030_TDC_RSLT_UI_MSB

#define ADF4030_TDC_RSLT_UI_MSB NO_OS_GENMASK(7, 0)

◆ ADF4030_TDC_SOURCE

#define ADF4030_TDC_SOURCE NO_OS_GENMASK(4, 0)

◆ ADF4030_TDC_TARGET

#define ADF4030_TDC_TARGET NO_OS_GENMASK(4, 0)

◆ ADF4030_TEMP_MEAS_LSB

#define ADF4030_TEMP_MEAS_LSB NO_OS_GENMASK(7, 0)

◆ ADF4030_TEMP_MEAS_MSB

#define ADF4030_TEMP_MEAS_MSB NO_OS_BIT(0)

◆ ADF4030_TEMP_MON

#define ADF4030_TEMP_MON NO_OS_BIT(4)

◆ ADF4030_TMP_ALIGN_ERR

#define ADF4030_TMP_ALIGN_ERR NO_OS_BIT(3)

◆ ADF4030_VCO_FREQ_MAX

#define ADF4030_VCO_FREQ_MAX 2625000000U

◆ ADF4030_VCO_FREQ_MIN

#define ADF4030_VCO_FREQ_MIN 2375000000U

Enumeration Type Documentation

◆ adf4030_terminations_e

enum adf4030_terminations_e

Enumerator
TX_VOLTAGE_DRIVER
TX_CURRENT_DRIVER_UNTERMINATED
TX_CURRENT_DRIVER_TERMINATED
RX_DC_COUPLED_CLKS
RX_AC_COUPLED_CLKS
RX_DC_COUPLED_HCSL

Function Documentation

◆ adf4030_get_alignment_iter()

int adf4030_get_alignment_iter	(	struct adf4030_dev *	dev,
		uint8_t *	iter_number )

Get the iteration number of alignment.

Parameters

dev	- The device structure.
iter_number	- Read value of number of iterations in one alignment.

Returns: - 0 in case of success or negative error code otherwise.

◆ adf4030_get_alignment_threshold()

int adf4030_get_alignment_threshold	(	struct adf4030_dev *	dev,
		uint32_t *	threshold_fs )

Get the alignment threshold in femtoseconds.

Parameters

dev	- The device structure.
threshold_fs	- Read value of alignment threshold in femtoseconds.

Returns: - 0 in case of success or negative error code otherwise.

◆ adf4030_get_background_serial_alignment()

int adf4030_get_background_serial_alignment	(	struct adf4030_dev *	dev,
		uint16_t *	channel_flags )

Get the background serial alignment channel flags for multiple BSYNC channels.

Parameters

dev	- The device structure.
channel_flags	- Read value of the channel alignment flags.

Returns: - 0 in case of success or negative error code otherwise.

◆ adf4030_get_bsync_freq()

int adf4030_get_bsync_freq	(	struct adf4030_dev *	dev,
		uint32_t *	bsync_freq,
		bool	odivb_sel )

Get the BSYNC frequency in Hz.

Parameters

dev	- The device structure.
bsync_freq	- The read BSYNC frequency in Hz.
odivb_sel	- Selects the output divider to read.

Returns: - 0 in case of success or negative error code otherwise.

◆ adf4030_get_channel_delay()

int adf4030_get_channel_delay	(	struct adf4030_dev *	dev,
		uint8_t	channel,
		int64_t *	delay_fs )

Get the delay for a specific channel.

Parameters

dev	- The device structure.
channel	- The channel to get the delay for.
delay_fs	- Read value of the delay in femtoseconds.

Returns: - 0 in case of success or negative error code otherwise.

◆ adf4030_get_channel_direction()

int adf4030_get_channel_direction	(	struct adf4030_dev *	dev,
		uint8_t	channel,
		bool *	tx_en )

Get the TX direction (TX/RX) of a specific channel.

Parameters

dev	- The device structure.
channel	- The channel to get the direction for.
tx_en	- Read the channel's TX direction status.

Returns: - 0 in case of success or negative error code otherwise.

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◆ adf4030_get_channel_invert()

int adf4030_get_channel_invert	(	struct adf4030_dev *	dev,
		uint8_t	channel,
		bool *	invert_en )

Get the inversion state for a specific channel.

Parameters

dev	- The device structure.
channel	- The channel to get the inversion state for.
invert_en	- Pointer to store the inversion state.

Returns: - 0 in case of success or negative error code otherwise.

◆ adf4030_get_channel_odivb()

int adf4030_get_channel_odivb	(	struct adf4030_dev *	dev,
		uint8_t	channel,
		bool *	odivb_en )

Get the output divider selection for a specific channel. If odivb_en is enabled, the output divider b will be used for the channel. Otherwise, the output divider a will be used.

Parameters

dev	- The device structure.
channel	- The channel to get the output divider for.
odivb_en	- Pointer to store the output divider state.

Returns: - 0 in case of success or negative error code otherwise.

◆ adf4030_get_channel_prbs()

int adf4030_get_channel_prbs	(	struct adf4030_dev *	dev,
		uint8_t	channel,
		bool *	prbs_en )

Get the PRBS (Pseudo-Random Binary Sequence) state for a specific channel.

Parameters

dev	- The device structure.
channel	- The channel to get the PRBS state for.
prbs_en	- Pointer to store the PRBS state.

Returns: - 0 in case of success or negative error code otherwise.

◆ adf4030_get_channel_termination()

int adf4030_get_channel_termination	(	struct adf4030_dev *	dev,
		uint8_t	channel,
		enum adf4030_terminations_e *	termination )

Get the termination type for a specific channel.

Parameters

dev	- The device structure.
channel	- The channel to get the termination for.
termination	- Read value of the termination type.

Returns: - 0 in case of success or negative error code otherwise.

◆ adf4030_get_channel_voltage()

int adf4030_get_channel_voltage	(	struct adf4030_dev *	dev,
		uint8_t	channel,
		uint32_t *	voltage_mv )

Get the voltage level for a specific channel.

Parameters

dev	- The device structure.
channel	- The channel to get the voltage level for.
voltage_mv	- Read value of the voltage level in millivolts.

Returns: - 0 in case of success or negative error code otherwise.

◆ adf4030_get_serial_alignment()

int adf4030_get_serial_alignment	(	struct adf4030_dev *	dev,
		uint16_t *	channel_flags )

Get the serial alignment channel flags for multiple BSYNC channels.

Parameters

dev	- The device structure.
channel_flags	- Read value of the channel alignment flags.

Returns: - 0 in case of success or negative error code otherwise.

◆ adf4030_get_tdc_measurement()

int adf4030_get_tdc_measurement	(	struct adf4030_dev *	dev,
		int64_t *	tdc_result_fs )

Get the TDC measurement result. Reads bitfileds and calculates the TDC result with period of the BSYNC signal.

Parameters

dev	- The device structure.
tdc_result_fs	- Read TDC measurement result in femtoseconds.

Returns: - 0 in case of success or negative error code otherwise.

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◆ adf4030_get_tdc_source()

int adf4030_get_tdc_source	(	struct adf4030_dev *	dev,
		uint8_t *	tdc_source )

Get the TDC source.

Parameters

dev	- The device structure.
tdc_source	- Read TDC source value.

Returns: - 0 in case of success or negative error code otherwise.

◆ adf4030_get_temperature()

int adf4030_get_temperature	(	struct adf4030_dev *	dev,
		int16_t *	temperature )

Gets the value of the approximate die temperature.

Parameters

dev	- The device structure.
temperature	- The read value of the Temperature Readback.

Returns: - 0 in case of success or negative error code.

◆ adf4030_get_vco_freq()

int adf4030_get_vco_freq	(	struct adf4030_dev *	dev,
		uint32_t *	vco_freq )

Get the VCO frequency in Hz.

Parameters

dev	- The device structure.
vco_freq	- The VCO frequency in Hz.

Returns: - 0 in case of success, negative error code otherwise.

◆ adf4030_init()

int adf4030_init	(	struct adf4030_dev **	dev,
		struct adf4030_init_param *	init_param )

Initializes the adf4030.

Parameters

dev	- The device structure.
init_param	- The structure containing the device initial parameters.

Returns: - 0 in case of success or negative error code.

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◆ adf4030_remove()

int adf4030_remove ( struct adf4030_dev * dev )

Free resources allocated for adf4030.

Parameters

dev	- The device structure.

Returns: - 0 in case of success or negative error code.

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◆ adf4030_set_alignment_iter()

int adf4030_set_alignment_iter	(	struct adf4030_dev *	dev,
		uint8_t	iter_number )

Set the iteration number of alignment.

Parameters

dev	- The device structure.
iter_number	- The number of iterations for the alignment.

Returns: - 0 in case of success or negative error code otherwise.

◆ adf4030_set_alignment_threshold()

int adf4030_set_alignment_threshold	(	struct adf4030_dev *	dev,
		uint32_t	threshold_fs )

Set the alignment threshold in femtoseconds.

Parameters

dev	- The device structure.
threshold_fs	- The alignment threshold in femtoseconds.

Returns: - 0 in case of success or negative error code otherwise.

◆ adf4030_set_background_serial_alignment()

int adf4030_set_background_serial_alignment	(	struct adf4030_dev *	dev,
		uint16_t	channel_flags )

Set background serial alignment for multiple BSYNC channels.

Parameters

dev	- The device structure.
channel_flags	- Flags indicating the channels to align.

Returns: - 0 in case of success or negative error code otherwise.

◆ adf4030_set_bsync_freq()

int adf4030_set_bsync_freq	(	struct adf4030_dev *	dev,
		uint32_t	bsync_freq,
		bool	odivb_sel )

Set the BSYNC frequency in Hz. Output divider will be choose according to odiv sel argument.

Parameters

dev	- The device structure.
bsync_freq	- The VCO frequency in Hz.
odivb_sel	- Selects the output divider which will be set.

Returns: - 0 in case of success, negative error code otherwise.

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◆ adf4030_set_channel_delay()

int adf4030_set_channel_delay	(	struct adf4030_dev *	dev,
		uint8_t	channel,
		int64_t	delay_fs )

Set the delay for a specific BSYNC channel. This Delay will show up between TDC_SOURCE and channel.

Parameters

dev	- The device structure.
channel	- The channel to set the delay for.
delay_fs	- The delay in femtoseconds.

Returns: - 0 in case of success or negative error code otherwise.

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◆ adf4030_set_channel_direction()

int adf4030_set_channel_direction	(	struct adf4030_dev *	dev,
		uint8_t	channel,
		bool	tx_en )

Set the TX-RX direction of a specific channel.

Parameters

dev	- The device structure.
channel	- The channel to set the direction for.
tx_en	- Enable or disable the channel.

Returns: - 0 in case of success or negative error code otherwise.

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◆ adf4030_set_channel_invert()

int adf4030_set_channel_invert	(	struct adf4030_dev *	dev,
		uint8_t	channel,
		bool	invert_en )

Set the inversion state for the BSYNC channel.

Parameters

dev	- The device structure.
channel	- The channel to set the inversion state for.
invert_en	- Enable or disable inversion.

Returns: - 0 in case of success or negative error code otherwise.

◆ adf4030_set_channel_odivb()

int adf4030_set_channel_odivb	(	struct adf4030_dev *	dev,
		uint8_t	channel,
		bool	odivb_en )

Set the output divider selection for a specific channel. If odivb_en is enabled, the output divider b will be used for the channel. Otherwise, the output divider a will be used.

Parameters

dev	- The device structure.
channel	- The channel to set the output divider for.
odivb_en	- Enable or disable the output divider b for the channel.

Returns: - 0 in case of success or negative error code otherwise.

◆ adf4030_set_channel_prbs()

int adf4030_set_channel_prbs	(	struct adf4030_dev *	dev,
		uint8_t	channel,
		bool	prbs_en )

Set the PRBS (Pseudo-Random Binary Sequence) state for a specific channel.

Parameters

dev	- The device structure.
channel	- The channel to set the PRBS state for.
prbs_en	- Enable or disable PRBS.

Returns: - 0 in case of success or negative error code otherwise.

◆ adf4030_set_channel_termination()

int adf4030_set_channel_termination	(	struct adf4030_dev *	dev,
		uint8_t	channel,
		enum adf4030_terminations_e	termination )

Set the termination type for a specific channel.

Parameters

dev	- The device structure.
channel	- The channel to set the termination for.
termination	- The termination type.

Returns: - 0 in case of success or negative error code otherwise.

◆ adf4030_set_channel_voltage()

int adf4030_set_channel_voltage	(	struct adf4030_dev *	dev,
		uint8_t	channel,
		uint32_t	voltage_mv )

Set the voltage level for the BSYNC channel.

Parameters

dev	- The device structure.
channel	- The channel to set the voltage level for.
voltage_mv	- The desired voltage level in millivolts.

Returns: - 0 in case of success or negative error code otherwise.

◆ adf4030_set_chip_address()

int adf4030_set_chip_address	(	struct adf4030_dev *	dev,
		uint8_t	addr )

Set the chip address value.

Parameters

dev	- The device structure.
addr	- The desired chip address value.

Returns: - 0 in case of success or negative error code.

◆ adf4030_set_default_regs()

int adf4030_set_default_regs	(	struct adf4030_dev *	dev,
		bool	spi_4wire )

Applys a softreset, sets the SPI 4 wire mode and writes the default registers.

Parameters

dev	- The device structure
spi_4wire	- SPI 4 wire feature enable input

Returns: - 0 in case of success, negative error code otherwise.

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◆ adf4030_set_ref_clk()

int adf4030_set_ref_clk	(	struct adf4030_dev *	dev,
		uint32_t	val )

Set the desired reference frequency and reset everything over to maximum supported value of 250MHz to the max. value and everything under the minimum supported value of 10MHz to the min.

Parameters

dev	- The device structure.
val	- The desired reference frequency in Hz.

Returns: - 0 in case of success or negative error code.

◆ adf4030_set_serial_alignment()

int adf4030_set_serial_alignment	(	struct adf4030_dev *	dev,
		uint16_t	channel_flags )

Set serial alignment for multiple BSYNC channels.

Parameters

dev	- The device structure.
channel_flags	- Flags indicating the channels to align.

Returns: - 0 in case of success or negative error code otherwise.

◆ adf4030_set_single_ch_alignment()

int adf4030_set_single_ch_alignment	(	struct adf4030_dev *	dev,
		uint8_t	tdc_target_ch )

Perform single-channel alignment. Before calling this function, please set tdc_source to the desired bsync channel.

Parameters

dev	- The device structure.
tdc_target_ch	- The TDC Target channel for alignment.

Returns: - 0 in case of success or negative error code otherwise.

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◆ adf4030_set_tdc_measurement()

int adf4030_set_tdc_measurement	(	struct adf4030_dev *	dev,
		uint8_t	tdc_target )

Set the TDC measurement target and start the measurement. Before calling this function, please set tdc_source to the desired bsync channel.

Parameters

dev	- The device structure.
tdc_target	- TDC measurement target.

Returns: - 0 in case of success or negative error code otherwise.

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◆ adf4030_set_tdc_source()

int adf4030_set_tdc_source	(	struct adf4030_dev *	dev,
		uint8_t	tdc_source )

Set the TDC source.

Parameters

dev	- The device structure.
tdc_source	- The desired TDC source value.

Returns: - 0 in case of success or negative error code otherwise.

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◆ adf4030_set_temperature()

int adf4030_set_temperature	(	struct adf4030_dev *	dev,
		bool	en )

Set Temperature Readback feature's initial state. This function should be called before reading temperature to trigger measurement.

Parameters

dev	- The device structure.
en	- The enable or disable Temperature readback feature.

Returns: - 0 in case of success or negative error code.

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◆ adf4030_set_vco_freq()

int adf4030_set_vco_freq	(	struct adf4030_dev *	dev,
		uint32_t	vco_freq )

Set the desired VCO frequency.

Parameters

dev	- The device structure.
vco_freq	- The desired reference frequency in Hz.

Returns: - 0 in case of success or negative error code.

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◆ adf4030_spi_read()

int adf4030_spi_read	(	struct adf4030_dev *	dev,
		uint16_t	reg_addr,
		uint8_t *	data )

Reads data from ADF4030 over SPI.

Parameters

dev	- The device structure.
reg_addr	- The register address.
data	- Data read from the device.

Returns: - 0 in case of success or negative error code otherwise.

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◆ adf4030_spi_update_bits()

int adf4030_spi_update_bits	(	struct adf4030_dev *	dev,
		uint16_t	reg_addr,
		uint8_t	mask,
		uint8_t	data )

Updates the values of the ADF4030 register.

Parameters

dev	- The device structure.
reg_addr	- The register address.
mask	- Bits to be updated.
data	- Update value for the mask.

Returns: - 0 in case of success or negative error code otherwise.

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◆ adf4030_spi_write()

int adf4030_spi_write	(	struct adf4030_dev *	dev,
		uint16_t	reg_addr,
		uint8_t	data )

Writes data to ADF4030 over SPI.

Parameters

dev	- The device structure.
reg_addr	- The register address.
data	- Data value to write.

Returns: - 0 in case of success or negative error code otherwise.

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Classes

Macros

Enumerations

Functions

Detailed Description

Macro Definition Documentation

◆ ADF4030_AC_COUPLED0

◆ ADF4030_AC_COUPLED1

◆ ADF4030_AC_COUPLED2

◆ ADF4030_AC_COUPLED3

◆ ADF4030_AC_COUPLED4

◆ ADF4030_AC_COUPLED5

◆ ADF4030_AC_COUPLED6

◆ ADF4030_AC_COUPLED7

◆ ADF4030_AC_COUPLED8

◆ ADF4030_AC_COUPLED9

◆ ADF4030_ADC_BUSY

◆ ADF4030_ADC_C_CNV

◆ ADF4030_ADC_CLK_DIV

◆ ADF4030_ADC_CLK_SEL

◆ ADF4030_ADC_ST_CNV

◆ ADF4030_ADDRESS_ASC_MSK

◆ ADF4030_ADDRESS_ASC_R_MSK

◆ ADF4030_ADEL

◆ ADF4030_ALIGN_CYCLES

◆ ADF4030_ALIGN_CYCLES_MAX

◆ ADF4030_ALIGN_CYCLES_MIN

◆ ADF4030_ALIGN_THOLD

◆ ADF4030_AUTO_PD_RCV0

◆ ADF4030_AUTO_PD_RCV1

◆ ADF4030_AUTO_PD_RCV2

◆ ADF4030_AUTO_PD_RCV3

◆ ADF4030_AUTO_PD_RCV4

◆ ADF4030_AUTO_PD_RCV5

◆ ADF4030_AUTO_PD_RCV6

◆ ADF4030_AUTO_PD_RCV7

◆ ADF4030_AUTO_PD_RCV8

◆ ADF4030_AUTO_PD_RCV9

◆ ADF4030_AUTO_PF_BG

◆ ADF4030_AVGRXP

◆ ADF4030_BOOST0

◆ ADF4030_BOOST1

◆ ADF4030_BOOST2

◆ ADF4030_BOOST3

◆ ADF4030_BOOST4

◆ ADF4030_BOOST5

◆ ADF4030_BOOST6

◆ ADF4030_BOOST7

◆ ADF4030_BOOST8

◆ ADF4030_BOOST9

◆ ADF4030_BSYNC_CAL_ON_1_0

◆ ADF4030_BSYNC_CAL_ON_9_2

◆ ADF4030_BSYNC_FREQ_MAX

◆ ADF4030_BSYNC_FREQ_MIN

◆ ADF4030_BUFF_SIZE_BYTES

◆ ADF4030_CHAN_INV0

◆ ADF4030_CHAN_INV1

◆ ADF4030_CHAN_INV2

◆ ADF4030_CHAN_INV3

◆ ADF4030_CHAN_INV4

◆ ADF4030_CHAN_INV5

◆ ADF4030_CHAN_INV6

◆ ADF4030_CHAN_INV7

◆ ADF4030_CHAN_INV8

◆ ADF4030_CHAN_INV9

◆ ADF4030_CHANNEL_DRV_SEPARATOR

◆ ADF4030_CHANNEL_INV_SEPARATOR

◆ ADF4030_CHANNEL_NUMBER

◆ ADF4030_CHANNEL_PRBS_SEPARATOR

◆ ADF4030_CHANNEL_TX_PD_SEPARATOR

◆ ADF4030_CHIP_ADDRESS

◆ ADF4030_CHIP_ADDRESS_MAX

◆ ADF4030_CHIP_ADDRESS_MIN

◆ ADF4030_CHIP_TYPE

◆ ADF4030_CMOS_OV

◆ ADF4030_CP_I

◆ ADF4030_CYCLES

◆ ADF4030_DELCAL

◆ ADF4030_DELTA_NDEL_COAR_LSB

◆ ADF4030_DELTA_NDEL_COAR_MSB