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#define | ADF5902_REG0 0x0 |
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#define | ADF5902_REG1 0x1 |
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#define | ADF5902_REG2 0x2 |
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#define | ADF5902_REG3 0x3 |
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#define | ADF5902_REG4 0x4 |
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#define | ADF5902_REG5 0x5 |
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#define | ADF5902_REG6 0x6 |
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#define | ADF5902_REG7 0x7 |
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#define | ADF5902_REG8 0x8 |
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#define | ADF5902_REG9 0x9 |
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#define | ADF5902_REG10 0xA |
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#define | ADF5902_REG11 0xB |
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#define | ADF5902_REG12 0xC |
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#define | ADF5902_REG13 0xD |
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#define | ADF5902_REG14 0xE |
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#define | ADF5902_REG15 0xF |
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#define | ADF5902_REG16 0x10 |
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#define | ADF5902_REG17 0x11 |
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#define | ADF5902_REG0_PLO(x) |
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#define | ADF5902_REG0_PTX1(x) |
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#define | ADF5902_REG0_PTX2(x) |
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#define | ADF5902_REG0_PADC(x) |
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#define | ADF5902_REG0_VCAL(x) |
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#define | ADF5902_REG0_PVCO(x) |
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#define | ADF5902_REG0_TX1C(x) |
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#define | ADF5902_REG0_TX2C(x) |
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#define | ADF5902_REG0_RESERVED (0x4007FU << 13) |
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#define | ADF5902_POWER_DOWN_LO 0x0 |
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#define | ADF5902_POWER_UP_LO 0x1 |
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#define | ADF5902_POWER_DOWN_TX1 0x0 |
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#define | ADF5902_POWER_UP_TX1 0x1 |
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#define | ADF5902_POWER_DOWN_TX2 0x0 |
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#define | ADF5902_POWER_UP_TX2 0x1 |
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#define | ADF5902_POWER_DOWN_ADC 0x0 |
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#define | ADF5902_POWER_UP_ADC 0x1 |
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#define | ADF5902_VCO_NORMAL_OP 0x0 |
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#define | ADF5902_VCO_FULL_CAL 0x1 |
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#define | ADF5902_POWER_DOWN_VCO 0x0 |
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#define | ADF5902_POWER_UP_VCO 0x1 |
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#define | ADF5902_TX1_NORMAL_OP 0x0 |
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#define | ADF5902_TX1_AMP_CAL 0x1 |
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#define | ADF5902_TX2_NORMAL_OP 0x0 |
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#define | ADF5902_TX2_AMP_CAL 0x1 |
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#define | ADF5902_REG1_TX_AMP_CAL_REF(x) |
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#define | ADF5902_REG1_RESERVED (0x7FFBFU << 13) |
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#define | ADF5902_TX_AMP_CAL_MIN_REF_CODE 0x00 |
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#define | ADF5902_TX_AMP_CAL_MAX_REF_CODE 0xFF |
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#define | ADF5902_REG2_ADC_CLK_DIV(x) |
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#define | ADF5902_REG2_ADC_AVG(x) |
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#define | ADF5902_REG2_ADC_START(x) |
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#define | ADF5902_REG2_RESERVED (0x2 << 16) |
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#define | ADF5902_ADC_MIN_CLK_DIVIDER 0x1 |
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#define | ADF5902_ADC_MAX_CLK_DIVIDER 0x7F |
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#define | ADF5902_ADC_AVG_1 0x0 |
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#define | ADF5902_ADC_AVG_2 0x1 |
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#define | ADF5902_ADC_AVG_3 0x2 |
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#define | ADF5902_ADC_AVG_4 0x3 |
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#define | ADF5902_ADC_NORMAL_OP 0x0 |
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#define | ADF5902_START_ADC_CONV 0x1 |
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#define | ADF5902_REG3_READBACK_CTRL(x) |
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#define | ADF5902_REG3_IO_LVL(x) |
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#define | ADF5902_REG3_MUXOUT(x) |
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#define | ADF5902_REG3_RESERVED (0x189 << 16) |
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#define | ADF5902_REG_RB_NONE 0x0 |
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#define | ADF5902_REG0_RB 0x1 |
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#define | ADF5902_REG1_RB 0x2 |
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#define | ADF5902_REG2_RB 0x3 |
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#define | ADF5902_REG3_RB 0x4 |
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#define | ADF5902_REG4_RB 0x5 |
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#define | ADF5902_REG5_RB 0x6 |
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#define | ADF5902_REG6_RB 0x7 |
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#define | ADF5902_REG7_RB 0x8 |
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#define | ADF5902_REG8_RB 0x9 |
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#define | ADF5902_REG9_RB 0xA |
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#define | ADF5902_REG10_RB 0xB |
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#define | ADF5902_REG11_RB 0xC |
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#define | ADF5902_REG12_RB 0xD |
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#define | ADF5902_REG13_SEL_0_RB 0xE |
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#define | ADF5902_REG14_SEL_0_RB 0xF |
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#define | ADF5902_REG15_SEL_0_RB 0x10 |
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#define | ADF5902_REG16_SEL_0_RB 0x11 |
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#define | ADF5902_REG17_RB 0x12 |
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#define | ADF5902_ADC_RB 0x16 |
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#define | ADF5902_FREQ_RB 0x1A |
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#define | ADF5902_REG13_SEL_1_RB 0x33 |
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#define | ADF5902_REG14_SEL_1_RB 0x34 |
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#define | ADF5902_REG15_SEL_1_RB 0x35 |
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#define | ADF5902_REG16_SEL_1_RB 0x36 |
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#define | ADF5902_REG13_SEL_2_RB 0x37 |
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#define | ADF5902_REG14_SEL_2_RB 0x38 |
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#define | ADF5902_REG15_SEL_2_RB 0x39 |
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#define | ADF5902_REG16_SEL_2_RB 0x3A |
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#define | ADF5902_REG13_SEL_3_RB 0x3B |
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#define | ADF5902_REG14_SEL_3_RB 0x3C |
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#define | ADF5902_REG15_SEL_3_RB 0x3D |
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#define | ADF5902_REG16_SEL_3_RB 0x3F |
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#define | ADF5902_IO_LVL_1V8 0x0 |
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#define | ADF5902_IO_LVL_3V3 0x1 |
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#define | ADF5902_MUXOUT_TRISTATE_OUT 0x0 |
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#define | ADF5902_MUXOUT_LOGIC_HIGH 0x1 |
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#define | ADF5902_MUXOUT_LOGIC_LOW 0x2 |
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#define | ADF5902_MUXOUT_R_DIV_OUT 0x3 |
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#define | ADF5902_MUXOUT_N_DIV_OUT 0x4 |
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#define | ADF5902_MUXOUT_CAL_BUSY 0x7 |
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#define | ADF5902_MUXOUT_R_DIV_OUT_2 0xB |
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#define | ADF5902_MUXOUT_N_DIV_OUT_2 0xC |
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#define | ADF5902_MUXOUT_RAMP_STATUS 0xF |
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#define | ADF5902_REG4_TEST_BUS(x) |
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#define | ADF5902_REG4_RESERVED (0x0 << 16) |
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#define | ADF5902_TEST_BUS_NONE 0x0000 |
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#define | ADF5902_RAMP_COMPL_TO_MUXOUT 0x00C0 |
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#define | ADF5902_RAMP_DOWN_TO_MUXOUT 0x0100 |
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#define | ADF5902_TEMP_SENS_TO_ATEST 0x0503 |
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#define | ADF5902_TEMP_SENS_TO_ADC 0x0903 |
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#define | ADF5902_REG5_FRAC_MSB_WORD(x) |
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#define | ADF5902_REG5_INTEGER_WORD(x) |
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#define | ADF5902_REG5_RAMP_ON(x) |
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#define | ADF5902_REG5_RESERVED (0x0 << 30) |
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#define | ADF5902_MIN_FRAC_MSB_WORD 0x000 |
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#define | ADF5902_MAX_FRAC_MSB_WORD 0xFFF |
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#define | ADF5902_MIN_INT_MSB_WORD 0x000 |
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#define | ADF5902_MAX_INT_MSB_WORD 0xFFF |
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#define | ADF5902_RAMP_ON_DISABLED 0x0 |
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#define | ADF5902_RAMP_ON_ENABLED 0x1 |
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#define | ADF5902_REG6_FRAC_LSB_WORD(x) |
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#define | ADF5902_REG6_RESERVED (0x0 << 18) |
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#define | ADF5902_MIN_FRAC_LSB_WORD 0x000 |
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#define | ADF5902_MAX_FRAC_LSB_WORD 0x1FFF |
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#define | ADF5902_REG7_R_DIVIDER(x) |
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#define | ADF5902_REG7_REF_DOUBLER(x) |
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#define | ADF5902_REG7_R_DIV_2(x) |
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#define | ADF5902_REG7_CLK_DIV(x) |
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#define | ADF5902_REG7_MASTER_RESET(x) |
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#define | ADF5902_REG7_RESERVED ((0x0 << 26) | (0x1 << 24)) |
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#define | ADF5902_MIN_R_DIVIDER 0x01 |
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#define | ADF5902_MAX_R_DIVIDER 0x1F |
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#define | ADF5902_R_DIV_2_DISABLE 0x0 |
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#define | ADF5902_R_DIV_2_ENABLE 0x1 |
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#define | ADF5902_REF_DOUBLER_DISABLE 0x0 |
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#define | ADF5902_REF_DOUBLER_ENABLE 0x1 |
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#define | ADF5902_MIN_CLK_DIVIDER 0x000 |
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#define | ADF5902_MAX_CLK_DIVIDER 0xFFF |
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#define | ADF5902_MASTER_RESET_DISABLE 0x0 |
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#define | ADF5902_MASTER_RESET_ENABLE 0x1 |
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#define | ADF5902_REG8_FREQ_CAL_DIV(x) |
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#define | ADF5902_REG8_RESERVED (0x8000 << 15) |
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#define | ADF5902_MIN_FREQ_CAL_DIV 0x000 |
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#define | ADF5902_MAX_FREQ_CAL_DIV 0x3FF |
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#define | ADF5902_REG9_RESERVED_CALIB (0x15105C9 << 5) |
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#define | ADF5902_REG9_RESERVED_NORMAL (0x14005C9 << 5) |
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#define | ADF5902_REG10_RESERVED (0xE99532 << 5) |
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#define | ADF5902_REG11_CNTR_RESET(x) |
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#define | ADF5902_REG11_RAMP_MODE(x) |
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#define | ADF5902_REG11_SING_FULL_TRI(x) |
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#define | ADF5902_REG11_SD_RESET(x) |
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#define | ADF5902_REG11_RESERVED ((0x0 << 6) | (0x0 << 10) | (0x0 << 12)) |
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#define | ADF5902_CNTR_RESET_DISABLE 0x0 |
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#define | ADF5902_CNTR_RESET_ENABLE 0x1 |
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#define | ADF5902_CONT_SAWTOOTH 0x0 |
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#define | ADF5902_SAWTOOTH_BURST 0x1 |
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#define | ADF5902_CONTINUOUS_TRIANGULAR 0x2 |
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#define | ADF5902_SINGLE_RAMP_BURST 0x3 |
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#define | ADF5902_SINGLE_FULL_TRI_DISBLE 0x0 |
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#define | ADF5902_SINGLE_FULL_TRI_ENABLE 0x1 |
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#define | ADF5902_SD_RESET_ENABLE 0x0 |
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#define | ADF5902_SD_RESET_DISABLE 0x1 |
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#define | ADF5902_REG12_CP_TRISTATE(x) |
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#define | ADF5902_REG12_CHARGE_PUMP(x) |
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#define | ADF5902_REG12_RESERVED ((0x0 << 5) | (0x1 << 16) | (0x2 << 21)) |
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#define | ADF5902_CP_TRISTATE_DISABLE 0x0 |
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#define | ADF5902_CP_TRISTATE_ENABLE 0x1 |
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#define | ADF5902_CP_CURRENT_280UA 0x0 |
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#define | ADF5902_CP_CURRENT_560UA 0x1 |
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#define | ADF5902_CP_CURRENT_840UA 0x2 |
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#define | ADF5902_CP_CURRENT_1MA12 0x3 |
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#define | ADF5902_CP_CURRENT_1MA40 0x4 |
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#define | ADF5902_CP_CURRENT_1MA68 0x5 |
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#define | ADF5902_CP_CURRENT_1MA96 0x6 |
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#define | ADF5902_CP_CURRENT_2MA24 0x7 |
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#define | ADF5902_CP_CURRENT_2MA52 0x8 |
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#define | ADF5902_CP_CURRENT_2MA80 0x9 |
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#define | ADF5902_CP_CURRENT_3MA08 0xA |
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#define | ADF5902_CP_CURRENT_3MA36 0xB |
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#define | ADF5902_CP_CURRENT_3MA64 0xC |
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#define | ADF5902_CP_CURRENT_3MA92 0xD |
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#define | ADF5902_CP_CURRENT_4MA20 0xE |
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#define | ADF5902_CP_CURRENT_4MA48 0xF |
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#define | ADF5902_REG13_CLK_DIV_SEL(x) |
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#define | ADF5902_REG13_CLK_DIV_2(x) |
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#define | ADF5902_REG13_CLK_DIV_MODE(x) |
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#define | ADF5902_REG13_LE_SEL(x) |
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#define | ADF5902_REG13_RESERVED (0x0 << 22) |
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#define | ADF5902_CLK_DIV_SEL_0 0x0 |
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#define | ADF5902_CLK_DIV_SEL_1 0x1 |
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#define | ADF5902_CLK_DIV_SEL_2 0x2 |
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#define | ADF5902_CLK_DIV_SEL_3 0x3 |
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#define | ADF5902_MIN_CLK_DIV_2 0x000 |
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#define | ADF5902_MAX_CLK_DIV_2 0xFFF |
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#define | ADF5902_CLK_DIV_OFF 0x0 |
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#define | ADF5902_FREQ_MEASURE 0x2 |
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#define | ADF5902_RAMP_DIV 0x3 |
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#define | ADF5902_LE_FROM_PIN 0x0 |
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#define | ADF5902_LE_SYNC_REFIN 0x1 |
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#define | ADF5902_REG14_DEV_WORD(x) |
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#define | ADF5902_REG14_DEV_OFFSET(x) |
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#define | ADF5902_REG14_DEV_SEL(x) |
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#define | ADF5902_REG14_TX_RAMP_CLK(x) |
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#define | ADF5902_REG14_TX_DATA_INV(x) |
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#define | ADF5902_REG14_RESERVED (0x0 << 27) |
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#define | ADF5902_MAX_DEV_WORD 0x7FFF |
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#define | ADF5902_MIN_DEV_WORD (int16_t)0x8000 |
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#define | ADF5902_MAX_DEV_OFFSET 0x9 |
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#define | ADF5902_MIN_DEV_OFFSET 0x0 |
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#define | ADF5902_DEV_SEL_0 0x0 |
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#define | ADF5902_DEV_SEL_1 0x1 |
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#define | ADF5902_DEV_SEL_2 0x2 |
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#define | ADF5902_DEV_SEL_3 0x3 |
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#define | ADF5902_TX_RAMP_CLK_DIV 0x0 |
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#define | ADF5902_TX_RAMP_TX_DATA_PIN 0x1 |
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#define | AD5902_TX_DATA_INV_DISABLE 0x0 |
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#define | AD5902_TX_DATA_INV_ENABLE 0x1 |
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#define | ADF5902_REG15_STEP_WORD(x) |
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#define | ADF5902_REG15_STEP_SEL(x) |
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#define | ADF5902_REG15_RESERVED (0x0 << 27) |
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#define | ADF5902_MIN_STEP_WORD 0x00000 |
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#define | ADF5902_MAX_STEP_WORD 0xFFFFF |
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#define | ADF5902_STEP_SEL_0 0x0 |
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#define | ADF5902_STEP_SEL_1 0x1 |
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#define | ADF5902_STEP_SEL_2 0x2 |
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#define | ADF5902_STEP_SEL_3 0x3 |
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#define | ADF5902_REG16_DEL_START_WORD(x) |
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#define | ADF5902_REG16_RAMP_DEL(x) |
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#define | ADF5902_REG16_TX_DATA_TRIG(x) |
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#define | ADF5902_REG16_DEL_SEL(x) |
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#define | ADF5902_REG16_RESERVED ((0x0 << 17) | (0x0 << 21) | (0x1 << 25)) |
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#define | ADF5902_MIN_DELAY_START_WRD 0x000 |
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#define | ADF5902_MAX_DELAY_START_WRD 0xFFF |
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#define | ADF5902_RAMP_DEL_DISABLE 0x0 |
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#define | ADF5902_RAMP_DEL_ENABLE 0x1 |
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#define | ADF5902_TX_DATA_TRIG_DISABLE 0x0 |
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#define | ADF5902_TX_DATA_TRIG_ENABLE 0x1 |
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#define | ADF5902_DEL_SEL_0 0x0 |
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#define | ADF5902_DEL_SEL_1 0x1 |
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#define | ADF5902_DEL_SEL_2 0x2 |
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#define | ADF5902_DEL_SEL_3 0x3 |
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#define | ADF5902_REG17_RESERVED (0x0 << 5) |
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#define | ADF5902_MAX_VCO_FREQ 24250000000ull |
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#define | ADF5902_MIN_VCO_FREQ 24000000000ull |
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#define | ADF5902_MIN_REFIN_FREQ 10000000 |
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#define | ADF5902_MAX_REFIN_FREQ 260000000 |
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#define | ADF5902_MAX_FREQ_PFD 110000000 |
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#define | ADF5902_MAX_SLOPE_NO 4 |
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#define | ADF5902_MAX_DELAY_WORD_NO 4 |
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#define | ADF5902_MAX_CLK2_DIV_NO 4 |
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#define | ADF5902_VLSB 0.00733f |
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#define | ADF5902_VOFF 0.699f |
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#define | ADF5902_VGAIN 0.0064f |
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#define | ADF5902_SPI_DUMMY_DATA 0x0 |
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#define | ADF5902_FREQ_CAL_DIV_100KHZ 100000 |
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#define | ADF5902_CLK1_DIV_25KHZ 25000 |
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#define | ADF5902_ADC_CLK_DIV_1MHZ 1000000 |
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#define | ADF5902_BUFF_SIZE_BYTES 4 |
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#define | ADF5902_FRAC_MSB_MSK 0xFFF |
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#define | ADF5902_FRAC_LSB_MSK 0x1FFF |
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