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adf7023.h File Reference

Header file of ADF7023 Driver. More...

#include <stdint.h>
#include "no_os_spi.h"
#include "no_os_gpio.h"
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Go to the source code of this file.

Classes

struct  adf7023_bbram
 
struct  adf7023_dev
 
struct  adf7023_init_param
 

Macros

#define STATUS_SPI_READY   (0x1 << 7)
 
#define STATUS_IRQ_STATUS   (0x1 << 6)
 
#define STATUS_CMD_READY   (0x1 << 5)
 
#define STATUS_FW_STATE   (0x1F << 0)
 
#define FW_STATE_INIT   0x0F
 
#define FW_STATE_BUSY   0x00
 
#define FW_STATE_PHY_OFF   0x11
 
#define FW_STATE_PHY_ON   0x12
 
#define FW_STATE_PHY_RX   0x13
 
#define FW_STATE_PHY_TX   0x14
 
#define FW_STATE_PHY_SLEEP   0x06
 
#define FW_STATE_GET_RSSI   0x05
 
#define FW_STATE_IR_CAL   0x07
 
#define FW_STATE_AES_DECRYPT_INIT   0x08
 
#define FW_STATE_AES_DECRYPT   0x09
 
#define FW_STATE_AES_ENCRYPT   0x0A
 
#define SPI_MEM_WR   0x18
 
#define SPI_MEM_RD   0x38
 
#define SPI_MEMR_WR   0x08
 
#define SPI_MEMR_RD   0x28
 
#define SPI_NOP   0xFF
 
#define CMD_SYNC   0xA2
 
#define CMD_PHY_OFF   0xB0
 
#define CMD_PHY_ON   0xB1
 
#define CMD_PHY_RX   0xB2
 
#define CMD_PHY_TX   0xB5
 
#define CMD_PHY_SLEEP   0xBA
 
#define CMD_CONFIG_DEV   0xBB
 
#define CMD_GET_RSSI   0xBC
 
#define CMD_BB_CAL   0xBE
 
#define CMD_HW_RESET   0xC8
 
#define CMD_RAM_LOAD_INIT   0xBF
 
#define CMD_RAM_LOAD_DONE   0xC7
 
#define CMD_IR_CAL   0xBD
 
#define CMD_AES_ENCRYPT   0xD0
 
#define CMD_AES_DECRYPT   0xD2
 
#define CMD_AES_DECRYPT_INIT   0xD1
 
#define CMD_RS_ENCODE_INIT   0xD1
 
#define CMD_RS_ENCODE   0xD0
 
#define CMD_RS_DECODE   0xD2
 
#define BBRAM_REG_INTERRUPT_MASK_0   0x100
 
#define BBRAM_REG_INTERRUPT_MASK_1   0x101
 
#define BBRAM_REG_NUMBER_OF_WAKEUPS_0   0x102
 
#define BBRAM_REG_NUMBER_OF_WAKEUPS_1   0x103
 
#define BBRAM_REG_NUMBER_OF_WAKEUPS_IRQ_THRESHOLD_0   0x104
 
#define BBRAM_REG_NUMBER_OF_WAKEUPS_IRQ_THRESHOLD_1   0x105
 
#define BBRAM_REG_RX_DWELL_TIME   0x106
 
#define BBRAM_REG_PARMTIME_DIVIDER   0x107
 
#define BBRAM_REG_SWM_RSSI_THRESH   0x108
 
#define BBRAM_REG_CHANNEL_FREQ_0   0x109
 
#define BBRAM_REG_CHANNEL_FREQ_1   0x10A
 
#define BBRAM_REG_CHANNEL_FREQ_2   0x10B
 
#define BBRAM_REG_RADIO_CFG_0   0x10C
 
#define BBRAM_REG_RADIO_CFG_1   0x10D
 
#define BBRAM_REG_RADIO_CFG_2   0x10E
 
#define BBRAM_REG_RADIO_CFG_3   0x10F
 
#define BBRAM_REG_RADIO_CFG_4   0x110
 
#define BBRAM_REG_RADIO_CFG_5   0x111
 
#define BBRAM_REG_RADIO_CFG_6   0x112
 
#define BBRAM_REG_RADIO_CFG_7   0x113
 
#define BBRAM_REG_RADIO_CFG_8   0x114
 
#define BBRAM_REG_RADIO_CFG_9   0x115
 
#define BBRAM_REG_RADIO_CFG_10   0x116
 
#define BBRAM_REG_RADIO_CFG_11   0x117
 
#define BBRAM_REG_IMAGE_REJECT_CAL_PHASE   0x118
 
#define BBRAM_REG_IMAGE_REJECT_CAL_AMPLITUDE   0x119
 
#define BBRAM_REG_MODE_CONTROL   0x11A
 
#define BBRAM_REG_PREAMBLE_MATCH   0x11B
 
#define BBRAM_REG_SYMBOL_MODE   0x11C
 
#define BBRAM_REG_PREAMBLE_LEN   0x11D
 
#define BBRAM_REG_CRC_POLY_0   0x11E
 
#define BBRAM_REG_CRC_POLY_1   0x11F
 
#define BBRAM_REG_SYNC_CONTROL   0x120
 
#define BBRAM_REG_SYNC_BYTE_0   0x121
 
#define BBRAM_REG_SYNC_BYTE_1   0x122
 
#define BBRAM_REG_SYNC_BYTE_2   0x123
 
#define BBRAM_REG_TX_BASE_ADR   0x124
 
#define BBRAM_REG_RX_BASE_ADR   0x125
 
#define BBRAM_REG_PACKET_LENGTH_CONTROL   0x126
 
#define BBRAM_REG_PACKET_LENGTH_MAX   0x127
 
#define BBRAM_REG_STATIC_REG_FIX   0x128
 
#define BBRAM_REG_ADDRESS_MATCH_OFFSET   0x129
 
#define BBRAM_REG_ADDRESS_LENGTH   0x12A
 
#define BBRAM_REG_ADDRESS_FILTERING_0   0x12B
 
#define BBRAM_REG_ADDRESS_FILTERING_1   0x12C
 
#define BBRAM_REG_ADDRESS_FILTERING_2   0x12D
 
#define BBRAM_REG_ADDRESS_FILTERING_3   0x12E
 
#define BBRAM_REG_ADDRESS_FILTERING_4   0x12F
 
#define BBRAM_REG_ADDRESS_FILTERING_5   0x130
 
#define BBRAM_REG_ADDRESS_FILTERING_6   0x131
 
#define BBRAM_REG_ADDRESS_FILTERING_7   0x132
 
#define BBRAM_REG_ADDRESS_FILTERING_8   0x133
 
#define BBRAM_REG_ADDRESS_FILTERING_9   0x134
 
#define BBRAM_REG_ADDRESS_FILTERING_10   0x135
 
#define BBRAM_REG_ADDRESS_FILTERING_11   0x136
 
#define BBRAM_REG_ADDRESS_FILTERING_12   0x137
 
#define BBRAM_REG_RSSI_WAIT_TIME   0x138
 
#define BBRAM_REG_TESTMODES   0x139
 
#define BBRAM_REG_TRANSITION_CLOCK_DIV   0x13A
 
#define BBRAM_REG_RESERVED_0   0x13B
 
#define BBRAM_REG_RESERVED_1   0x13C
 
#define BBRAM_REG_RESERVED_2   0x13D
 
#define BBRAM_REG_RX_SYNTH_LOCK_TIME   0x13E
 
#define BBRAM_REG_TX_SYNTH_LOCK_TIME   0x13F
 
#define BBRAM_INTERRUPT_MASK_0_INTERRUPT_NUM_WAKEUPS   (0x1 << 7)
 
#define BBRAM_INTERRUPT_MASK_0_INTERRUPT_SWM_RSSI_DET   (0x1 << 6)
 
#define BBRAM_INTERRUPT_MASK_0_INTERRUPT_AES_DONE   (0x1 << 5)
 
#define BBRAM_INTERRUPT_MASK_0_INTERRUPT_TX_EOF   (0x1 << 4)
 
#define BBRAM_INTERRUPT_MASK_0_INTERRUPT_ADDRESS_MATCH   (0x1 << 3)
 
#define BBRAM_INTERRUPT_MASK_0_INTERRUPT_CRC_CORRECT   (0x1 << 2)
 
#define BBRAM_INTERRUPT_MASK_0_INTERRUPT_SYNC_DETECT   (0x1 << 1)
 
#define BBRAM_INTERRUPT_MASK_0_INTERRUPT_PREMABLE_DETECT   (0x1 << 0)
 
#define BBRAM_INTERRUPT_MASK_1_BATTERY_ALARM   (0x1 << 7)
 
#define BBRAM_INTERRUPT_MASK_1_CMD_READY   (0x1 << 6)
 
#define BBRAM_INTERRUPT_MASK_1_WUC_TIMEOUT   (0x1 << 4)
 
#define BBRAM_INTERRUPT_MASK_1_SPI_READY   (0x1 << 1)
 
#define BBRAM_INTERRUPT_MASK_1_CMD_FINISHED   (0x1 << 0)
 
#define BBRAM_RADIO_CFG_0_DATA_RATE_7_0(x)
 
#define BBRAM_RADIO_CFG_1_FREQ_DEVIATION_11_8(x)
 
#define BBRAM_RADIO_CFG_1_DATA_RATE_11_8(x)
 
#define BBRAM_RADIO_CFG_2_FREQ_DEVIATION_7_0(x)
 
#define BBRAM_RADIO_CFG_6_SYNTH_LUT_CONFIG_0(x)
 
#define BBRAM_RADIO_CFG_6_DISCRIM_PHASE(x)
 
#define BBRAM_RADIO_CFG_7_AGC_LOCK_MODE(x)
 
#define BBRAM_RADIO_CFG_7_SYNTH_LUT_CONTROL(x)
 
#define BBRAM_RADIO_CFG_7_SYNTH_LUT_CONFIG_1(x)
 
#define BBRAM_RADIO_CFG_8_PA_SINGLE_DIFF_SEL   (0x1 << 7)
 
#define BBRAM_RADIO_CFG_8_PA_LEVEL(x)
 
#define BBRAM_RADIO_CFG_8_PA_RAMP(x)
 
#define BBRAM_RADIO_CFG_9_IFBW(x)
 
#define BBRAM_RADIO_CFG_9_MOD_SCHEME(x)
 
#define BBRAM_RADIO_CFG_9_DEMOD_SCHEME(x)
 
#define BBRAM_RADIO_CFG_10_AFC_POLARITY   (0x0 << 4)
 
#define BBRAM_RADIO_CFG_10_AFC_SCHEME(x)
 
#define BBRAM_RADIO_CFG_10_AFC_LOCK_MODE(x)
 
#define BBRAM_RADIO_CFG_11_AFC_KP(x)
 
#define BBRAM_RADIO_CFG_11_AFC_KI(x)
 
#define BBRAM_MODE_CONTROL_SWM_EN   (0x1 << 7)
 
#define BBRAM_MODE_CONTROL_BB_CAL   (0x1 << 6)
 
#define BBRAM_MODE_CONTROL_SWM_RSSI_QUAL   (0x1 << 5)
 
#define BBRAM_MODE_CONTROL_TX_TO_RX_AUTO_TURNAROUND   (0x1 << 4)
 
#define BBRAM_MODE_CONTROL_RX_TO_TX_AUTO_TURNAROUND   (0x1 << 3)
 
#define BBRAM_MODE_CONTROL_CUSTOM_TRX_SYNTH_LOCK_TIME_EN   (0x1 << 2)
 
#define BBRAM_MODE_CONTROL_EXT_LNA_EN   (0x1 << 1)
 
#define BBRAM_MODE_CONTROL_EXT_PA_EN   (0x1 << 0)
 
#define BBRAM_SYMBOL_MODE_MANCHESTER_ENC   (0x1 << 6)
 
#define BBRAM_SYMBOL_MODE_PROG_CRC_EN   (0x1 << 5)
 
#define BBRAM_SYMBOL_MODE_EIGHT_TEN_ENC   (0x1 << 4)
 
#define BBRAM_SYMBOL_MODE_DATA_WHITENING   (0x1 << 3)
 
#define BBRAM_SYMBOL_MODE_SYMBOL_LENGTH(x)
 
#define BBRAM_SYNC_CONTROL_SYNC_ERROR_TOL(x)
 
#define BBRAM_SYNC_CONTROL_SYNC_WORD_LENGTH(x)
 
#define BBRAM_PACKET_LENGTH_CONTROL_DATA_BYTE   (0x1 << 7)
 
#define BBRAM_PACKET_LENGTH_CONTROL_PACKET_LEN   (0x1 << 6)
 
#define BBRAM_PACKET_LENGTH_CONTROL_CRC_EN   (0x1 << 5)
 
#define BBRAM_PACKET_LENGTH_CONTROL_DATA_MODE(x)
 
#define BBRAM_PACKET_LENGTH_CONTROL_LENGTH_OFFSET(x)
 
#define BBRAM_TESTMODES_EXT_PA_LNA_ATB_CONFIG   (0x1 << 7)
 
#define BBRAM_TESTMODES_PER_IRQ_SELF_CLEAR   (0x1 << 3)
 
#define BBRAM_TESTMODES_PER_ENABLE   (0x1 << 2)
 
#define BBRAM_TESTMODES_CONTINUOUS_TX   (0x1 << 1)
 
#define BBRAM_TESTMODES_CONTINUOUS_RX   (0x1 << 0)
 
#define MCR_REG_PA_LEVEL_MCR   0x307
 
#define MCR_REG_WUC_CONFIG_HIGH   0x30C
 
#define MCR_REG_WUC_CONFIG_LOW   0x30D
 
#define MCR_REG_WUC_VALUE_HIGH   0x30E
 
#define MCR_REG_WUC_VALUE_LOW   0x30F
 
#define MCR_REG_WUC_FLAG_RESET   0x310
 
#define MCR_REG_WUC_STATUS   0x311
 
#define MCR_REG_RSSI_READBACK   0x312
 
#define MCR_REG_MAX_AFC_RANGE   0x315
 
#define MCR_REG_IMAGE_REJECT_CAL_CONFIG   0x319
 
#define MCR_REG_CHIP_SHUTDOWN   0x322
 
#define MCR_REG_POWERDOWN_RX   0x324
 
#define MCR_REG_POWERDOWN_AUX   0x325
 
#define MCR_REG_ADC_READBACK_HIGH   0x327
 
#define MCR_REG_ADC_READBACK_LOW   0x328
 
#define MCR_REG_BATTERY_MONITOR_THRESHOLD_VOLTAGE   0x32D
 
#define MCR_REG_EXT_UC_CLK_DIVIDE   0x32E
 
#define MCR_REG_AGC_CLK_DIVIDE   0x32F
 
#define MCR_REG_INTERRUPT_SOURCE_0   0x336
 
#define MCR_REG_INTERRUPT_SOURCE_1   0x337
 
#define MCR_REG_CALIBRATION_CONTROL   0x338
 
#define MCR_REG_CALIBRATION_STATUS   0x339
 
#define MCR_REG_RXBB_CAL_CALWRD_READBACK   0x345
 
#define MCR_REG_RXBB_CAL_CALWRD_OVERWRITE   0x346
 
#define MCR_REG_RCOSC_CAL_READBACK_HIGH   0x34F
 
#define MCR_REG_RCOSC_CAL_READBACK_LOW   0x350
 
#define MCR_REG_ADC_CONFIG_LOW   0x359
 
#define MCR_REG_ADC_CONFIG_HIGH   0x35A
 
#define MCR_REG_AGC_OOK_CONTROL   0x35B
 
#define MCR_REG_AGC_CONFIG   0x35C
 
#define MCR_REG_AGC_MODE   0x35D
 
#define MCR_REG_AGC_LOW_THRESHOLD   0x35E
 
#define MCR_REG_AGC_HIGH_THRESHOLD   0x35F
 
#define MCR_REG_AGC_GAIN_STATUS   0x360
 
#define MCR_REG_AGC_ADC_WORD   0x361
 
#define MCR_REG_FREQUENCY_ERROR_READBACK   0x372
 
#define MCR_REG_VCO_BAND_OVRW_VAL   0x3CB
 
#define MCR_REG_VCO_AMPL_OVRW_VAL   0x3CC
 
#define MCR_REG_VCO_OVRW_EN   0x3CD
 
#define MCR_REG_VCO_CAL_CFG   0x3D0
 
#define MCR_REG_OSC_CONFIG   0x3D2
 
#define MCR_REG_VCO_BAND_READBACK   0x3DA
 
#define MCR_REG_VCO_AMPL_READBACK   0x3DB
 
#define MCR_REG_ANALOG_TEST_BUS   0x3F8
 
#define MCR_REG_RSSI_TSTMUX_SEL   0x3F9
 
#define MCR_REG_GPIO_CONFIGURE   0x3FA
 
#define MCR_REG_TEST_DAC_GAIN   0x3FD
 
#define ADF7023_TX_BASE_ADR   0x10
 
#define ADF7023_RX_BASE_ADR   0x10
 

Functions

int32_t adf7023_init (struct adf7023_dev **device, struct adf7023_init_param init_param)
 Initializes the ADF7023.
 
int32_t adf7023_remove (struct adf7023_dev *dev)
 Free the resources allocated by adf7023_init().
 
void adf7023_get_status (struct adf7023_dev *dev, uint8_t *status)
 Reads the status word of the ADF7023.
 
void adf7023_set_command (struct adf7023_dev *dev, uint8_t command)
 Initiates a command.
 
void adf7023_set_fw_state (struct adf7023_dev *dev, uint8_t fw_state)
 Sets a FW state and waits until the device enters in that state.
 
void adf7023_get_ram (struct adf7023_dev *dev, uint32_t address, uint32_t length, uint8_t *data)
 Reads data from the RAM.
 
void adf7023_set_ram (struct adf7023_dev *dev, uint32_t address, uint32_t length, uint8_t *data)
 Writes data to RAM.
 
void adf7023_receive_packet (struct adf7023_dev *dev, uint8_t *packet, uint8_t *length)
 Receives one packet.
 
void adf7023_transmit_packet (struct adf7023_dev *dev, uint8_t *packet, uint8_t length)
 Transmits one packet.
 
void adf7023_set_channel_frequency (struct adf7023_dev *dev, uint32_t ch_freq)
 Sets the channel frequency.
 
void adf7023_set_data_rate (struct adf7023_dev *dev, uint32_t data_rate)
 Sets the data rate.
 
void adf7023_set_frequency_deviation (struct adf7023_dev *dev, uint32_t freq_dev)
 Sets the frequency deviation.
 

Detailed Description

Header file of ADF7023 Driver.

Author
DBogdan (Drago.nosp@m.s.Bo.nosp@m.gdan@.nosp@m.anal.nosp@m.og.co.nosp@m.m)

Copyright 2013(c) Analog Devices, Inc.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

  1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
  2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
  3. Neither the name of Analog Devices, Inc. nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Macro Definition Documentation

◆ ADF7023_RX_BASE_ADR

#define ADF7023_RX_BASE_ADR   0x10

◆ ADF7023_TX_BASE_ADR

#define ADF7023_TX_BASE_ADR   0x10

◆ BBRAM_INTERRUPT_MASK_0_INTERRUPT_ADDRESS_MATCH

#define BBRAM_INTERRUPT_MASK_0_INTERRUPT_ADDRESS_MATCH   (0x1 << 3)

◆ BBRAM_INTERRUPT_MASK_0_INTERRUPT_AES_DONE

#define BBRAM_INTERRUPT_MASK_0_INTERRUPT_AES_DONE   (0x1 << 5)

◆ BBRAM_INTERRUPT_MASK_0_INTERRUPT_CRC_CORRECT

#define BBRAM_INTERRUPT_MASK_0_INTERRUPT_CRC_CORRECT   (0x1 << 2)

◆ BBRAM_INTERRUPT_MASK_0_INTERRUPT_NUM_WAKEUPS

#define BBRAM_INTERRUPT_MASK_0_INTERRUPT_NUM_WAKEUPS   (0x1 << 7)

◆ BBRAM_INTERRUPT_MASK_0_INTERRUPT_PREMABLE_DETECT

#define BBRAM_INTERRUPT_MASK_0_INTERRUPT_PREMABLE_DETECT   (0x1 << 0)

◆ BBRAM_INTERRUPT_MASK_0_INTERRUPT_SWM_RSSI_DET

#define BBRAM_INTERRUPT_MASK_0_INTERRUPT_SWM_RSSI_DET   (0x1 << 6)

◆ BBRAM_INTERRUPT_MASK_0_INTERRUPT_SYNC_DETECT

#define BBRAM_INTERRUPT_MASK_0_INTERRUPT_SYNC_DETECT   (0x1 << 1)

◆ BBRAM_INTERRUPT_MASK_0_INTERRUPT_TX_EOF

#define BBRAM_INTERRUPT_MASK_0_INTERRUPT_TX_EOF   (0x1 << 4)

◆ BBRAM_INTERRUPT_MASK_1_BATTERY_ALARM

#define BBRAM_INTERRUPT_MASK_1_BATTERY_ALARM   (0x1 << 7)

◆ BBRAM_INTERRUPT_MASK_1_CMD_FINISHED

#define BBRAM_INTERRUPT_MASK_1_CMD_FINISHED   (0x1 << 0)

◆ BBRAM_INTERRUPT_MASK_1_CMD_READY

#define BBRAM_INTERRUPT_MASK_1_CMD_READY   (0x1 << 6)

◆ BBRAM_INTERRUPT_MASK_1_SPI_READY

#define BBRAM_INTERRUPT_MASK_1_SPI_READY   (0x1 << 1)

◆ BBRAM_INTERRUPT_MASK_1_WUC_TIMEOUT

#define BBRAM_INTERRUPT_MASK_1_WUC_TIMEOUT   (0x1 << 4)

◆ BBRAM_MODE_CONTROL_BB_CAL

#define BBRAM_MODE_CONTROL_BB_CAL   (0x1 << 6)

◆ BBRAM_MODE_CONTROL_CUSTOM_TRX_SYNTH_LOCK_TIME_EN

#define BBRAM_MODE_CONTROL_CUSTOM_TRX_SYNTH_LOCK_TIME_EN   (0x1 << 2)

◆ BBRAM_MODE_CONTROL_EXT_LNA_EN

#define BBRAM_MODE_CONTROL_EXT_LNA_EN   (0x1 << 1)

◆ BBRAM_MODE_CONTROL_EXT_PA_EN

#define BBRAM_MODE_CONTROL_EXT_PA_EN   (0x1 << 0)

◆ BBRAM_MODE_CONTROL_RX_TO_TX_AUTO_TURNAROUND

#define BBRAM_MODE_CONTROL_RX_TO_TX_AUTO_TURNAROUND   (0x1 << 3)

◆ BBRAM_MODE_CONTROL_SWM_EN

#define BBRAM_MODE_CONTROL_SWM_EN   (0x1 << 7)

◆ BBRAM_MODE_CONTROL_SWM_RSSI_QUAL

#define BBRAM_MODE_CONTROL_SWM_RSSI_QUAL   (0x1 << 5)

◆ BBRAM_MODE_CONTROL_TX_TO_RX_AUTO_TURNAROUND

#define BBRAM_MODE_CONTROL_TX_TO_RX_AUTO_TURNAROUND   (0x1 << 4)

◆ BBRAM_PACKET_LENGTH_CONTROL_CRC_EN

#define BBRAM_PACKET_LENGTH_CONTROL_CRC_EN   (0x1 << 5)

◆ BBRAM_PACKET_LENGTH_CONTROL_DATA_BYTE

#define BBRAM_PACKET_LENGTH_CONTROL_DATA_BYTE   (0x1 << 7)

◆ BBRAM_PACKET_LENGTH_CONTROL_DATA_MODE

#define BBRAM_PACKET_LENGTH_CONTROL_DATA_MODE ( x)
Value:
((x & 0x3) << 3)

◆ BBRAM_PACKET_LENGTH_CONTROL_LENGTH_OFFSET

#define BBRAM_PACKET_LENGTH_CONTROL_LENGTH_OFFSET ( x)
Value:
((x & 0x7) << 0)

◆ BBRAM_PACKET_LENGTH_CONTROL_PACKET_LEN

#define BBRAM_PACKET_LENGTH_CONTROL_PACKET_LEN   (0x1 << 6)

◆ BBRAM_RADIO_CFG_0_DATA_RATE_7_0

#define BBRAM_RADIO_CFG_0_DATA_RATE_7_0 ( x)
Value:
((x & 0xFF) << 0)

◆ BBRAM_RADIO_CFG_10_AFC_LOCK_MODE

#define BBRAM_RADIO_CFG_10_AFC_LOCK_MODE ( x)
Value:
((x & 0x3) << 0)

◆ BBRAM_RADIO_CFG_10_AFC_POLARITY

#define BBRAM_RADIO_CFG_10_AFC_POLARITY   (0x0 << 4)

◆ BBRAM_RADIO_CFG_10_AFC_SCHEME

#define BBRAM_RADIO_CFG_10_AFC_SCHEME ( x)
Value:
((x & 0x3) << 2)

◆ BBRAM_RADIO_CFG_11_AFC_KI

#define BBRAM_RADIO_CFG_11_AFC_KI ( x)
Value:
((x & 0xF) << 0)

◆ BBRAM_RADIO_CFG_11_AFC_KP

#define BBRAM_RADIO_CFG_11_AFC_KP ( x)
Value:
((x & 0xF) << 4)

◆ BBRAM_RADIO_CFG_1_DATA_RATE_11_8

#define BBRAM_RADIO_CFG_1_DATA_RATE_11_8 ( x)
Value:
((x & 0xF) << 0)

◆ BBRAM_RADIO_CFG_1_FREQ_DEVIATION_11_8

#define BBRAM_RADIO_CFG_1_FREQ_DEVIATION_11_8 ( x)
Value:
((x & 0xF) << 4)

◆ BBRAM_RADIO_CFG_2_FREQ_DEVIATION_7_0

#define BBRAM_RADIO_CFG_2_FREQ_DEVIATION_7_0 ( x)
Value:
((x & 0xFF) << 0)

◆ BBRAM_RADIO_CFG_6_DISCRIM_PHASE

#define BBRAM_RADIO_CFG_6_DISCRIM_PHASE ( x)
Value:
((x & 0x3) << 0)

◆ BBRAM_RADIO_CFG_6_SYNTH_LUT_CONFIG_0

#define BBRAM_RADIO_CFG_6_SYNTH_LUT_CONFIG_0 ( x)
Value:
((x & 0x3F) << 2)

◆ BBRAM_RADIO_CFG_7_AGC_LOCK_MODE

#define BBRAM_RADIO_CFG_7_AGC_LOCK_MODE ( x)
Value:
((x & 0x3) << 6)

◆ BBRAM_RADIO_CFG_7_SYNTH_LUT_CONFIG_1

#define BBRAM_RADIO_CFG_7_SYNTH_LUT_CONFIG_1 ( x)
Value:
((x & 0xF) << 0)

◆ BBRAM_RADIO_CFG_7_SYNTH_LUT_CONTROL

#define BBRAM_RADIO_CFG_7_SYNTH_LUT_CONTROL ( x)
Value:
((x & 0x3) << 4)

◆ BBRAM_RADIO_CFG_8_PA_LEVEL

#define BBRAM_RADIO_CFG_8_PA_LEVEL ( x)
Value:
((x & 0xF) << 3)

◆ BBRAM_RADIO_CFG_8_PA_RAMP

#define BBRAM_RADIO_CFG_8_PA_RAMP ( x)
Value:
((x & 0x7) << 0)

◆ BBRAM_RADIO_CFG_8_PA_SINGLE_DIFF_SEL

#define BBRAM_RADIO_CFG_8_PA_SINGLE_DIFF_SEL   (0x1 << 7)

◆ BBRAM_RADIO_CFG_9_DEMOD_SCHEME

#define BBRAM_RADIO_CFG_9_DEMOD_SCHEME ( x)
Value:
((x & 0x7) << 0)

◆ BBRAM_RADIO_CFG_9_IFBW

#define BBRAM_RADIO_CFG_9_IFBW ( x)
Value:
((x & 0x3) << 6)

◆ BBRAM_RADIO_CFG_9_MOD_SCHEME

#define BBRAM_RADIO_CFG_9_MOD_SCHEME ( x)
Value:
((x & 0x7) << 3)

◆ BBRAM_REG_ADDRESS_FILTERING_0

#define BBRAM_REG_ADDRESS_FILTERING_0   0x12B

◆ BBRAM_REG_ADDRESS_FILTERING_1

#define BBRAM_REG_ADDRESS_FILTERING_1   0x12C

◆ BBRAM_REG_ADDRESS_FILTERING_10

#define BBRAM_REG_ADDRESS_FILTERING_10   0x135

◆ BBRAM_REG_ADDRESS_FILTERING_11

#define BBRAM_REG_ADDRESS_FILTERING_11   0x136

◆ BBRAM_REG_ADDRESS_FILTERING_12

#define BBRAM_REG_ADDRESS_FILTERING_12   0x137

◆ BBRAM_REG_ADDRESS_FILTERING_2

#define BBRAM_REG_ADDRESS_FILTERING_2   0x12D

◆ BBRAM_REG_ADDRESS_FILTERING_3

#define BBRAM_REG_ADDRESS_FILTERING_3   0x12E

◆ BBRAM_REG_ADDRESS_FILTERING_4

#define BBRAM_REG_ADDRESS_FILTERING_4   0x12F

◆ BBRAM_REG_ADDRESS_FILTERING_5

#define BBRAM_REG_ADDRESS_FILTERING_5   0x130

◆ BBRAM_REG_ADDRESS_FILTERING_6

#define BBRAM_REG_ADDRESS_FILTERING_6   0x131

◆ BBRAM_REG_ADDRESS_FILTERING_7

#define BBRAM_REG_ADDRESS_FILTERING_7   0x132

◆ BBRAM_REG_ADDRESS_FILTERING_8

#define BBRAM_REG_ADDRESS_FILTERING_8   0x133

◆ BBRAM_REG_ADDRESS_FILTERING_9

#define BBRAM_REG_ADDRESS_FILTERING_9   0x134

◆ BBRAM_REG_ADDRESS_LENGTH

#define BBRAM_REG_ADDRESS_LENGTH   0x12A

◆ BBRAM_REG_ADDRESS_MATCH_OFFSET

#define BBRAM_REG_ADDRESS_MATCH_OFFSET   0x129

◆ BBRAM_REG_CHANNEL_FREQ_0

#define BBRAM_REG_CHANNEL_FREQ_0   0x109

◆ BBRAM_REG_CHANNEL_FREQ_1

#define BBRAM_REG_CHANNEL_FREQ_1   0x10A

◆ BBRAM_REG_CHANNEL_FREQ_2

#define BBRAM_REG_CHANNEL_FREQ_2   0x10B

◆ BBRAM_REG_CRC_POLY_0

#define BBRAM_REG_CRC_POLY_0   0x11E

◆ BBRAM_REG_CRC_POLY_1

#define BBRAM_REG_CRC_POLY_1   0x11F

◆ BBRAM_REG_IMAGE_REJECT_CAL_AMPLITUDE

#define BBRAM_REG_IMAGE_REJECT_CAL_AMPLITUDE   0x119

◆ BBRAM_REG_IMAGE_REJECT_CAL_PHASE

#define BBRAM_REG_IMAGE_REJECT_CAL_PHASE   0x118

◆ BBRAM_REG_INTERRUPT_MASK_0

#define BBRAM_REG_INTERRUPT_MASK_0   0x100

◆ BBRAM_REG_INTERRUPT_MASK_1

#define BBRAM_REG_INTERRUPT_MASK_1   0x101

◆ BBRAM_REG_MODE_CONTROL

#define BBRAM_REG_MODE_CONTROL   0x11A

◆ BBRAM_REG_NUMBER_OF_WAKEUPS_0

#define BBRAM_REG_NUMBER_OF_WAKEUPS_0   0x102

◆ BBRAM_REG_NUMBER_OF_WAKEUPS_1

#define BBRAM_REG_NUMBER_OF_WAKEUPS_1   0x103

◆ BBRAM_REG_NUMBER_OF_WAKEUPS_IRQ_THRESHOLD_0

#define BBRAM_REG_NUMBER_OF_WAKEUPS_IRQ_THRESHOLD_0   0x104

◆ BBRAM_REG_NUMBER_OF_WAKEUPS_IRQ_THRESHOLD_1

#define BBRAM_REG_NUMBER_OF_WAKEUPS_IRQ_THRESHOLD_1   0x105

◆ BBRAM_REG_PACKET_LENGTH_CONTROL

#define BBRAM_REG_PACKET_LENGTH_CONTROL   0x126

◆ BBRAM_REG_PACKET_LENGTH_MAX

#define BBRAM_REG_PACKET_LENGTH_MAX   0x127

◆ BBRAM_REG_PARMTIME_DIVIDER

#define BBRAM_REG_PARMTIME_DIVIDER   0x107

◆ BBRAM_REG_PREAMBLE_LEN

#define BBRAM_REG_PREAMBLE_LEN   0x11D

◆ BBRAM_REG_PREAMBLE_MATCH

#define BBRAM_REG_PREAMBLE_MATCH   0x11B

◆ BBRAM_REG_RADIO_CFG_0

#define BBRAM_REG_RADIO_CFG_0   0x10C

◆ BBRAM_REG_RADIO_CFG_1

#define BBRAM_REG_RADIO_CFG_1   0x10D

◆ BBRAM_REG_RADIO_CFG_10

#define BBRAM_REG_RADIO_CFG_10   0x116

◆ BBRAM_REG_RADIO_CFG_11

#define BBRAM_REG_RADIO_CFG_11   0x117

◆ BBRAM_REG_RADIO_CFG_2

#define BBRAM_REG_RADIO_CFG_2   0x10E

◆ BBRAM_REG_RADIO_CFG_3

#define BBRAM_REG_RADIO_CFG_3   0x10F

◆ BBRAM_REG_RADIO_CFG_4

#define BBRAM_REG_RADIO_CFG_4   0x110

◆ BBRAM_REG_RADIO_CFG_5

#define BBRAM_REG_RADIO_CFG_5   0x111

◆ BBRAM_REG_RADIO_CFG_6

#define BBRAM_REG_RADIO_CFG_6   0x112

◆ BBRAM_REG_RADIO_CFG_7

#define BBRAM_REG_RADIO_CFG_7   0x113

◆ BBRAM_REG_RADIO_CFG_8

#define BBRAM_REG_RADIO_CFG_8   0x114

◆ BBRAM_REG_RADIO_CFG_9

#define BBRAM_REG_RADIO_CFG_9   0x115

◆ BBRAM_REG_RESERVED_0

#define BBRAM_REG_RESERVED_0   0x13B

◆ BBRAM_REG_RESERVED_1

#define BBRAM_REG_RESERVED_1   0x13C

◆ BBRAM_REG_RESERVED_2

#define BBRAM_REG_RESERVED_2   0x13D

◆ BBRAM_REG_RSSI_WAIT_TIME

#define BBRAM_REG_RSSI_WAIT_TIME   0x138

◆ BBRAM_REG_RX_BASE_ADR

#define BBRAM_REG_RX_BASE_ADR   0x125

◆ BBRAM_REG_RX_DWELL_TIME

#define BBRAM_REG_RX_DWELL_TIME   0x106

◆ BBRAM_REG_RX_SYNTH_LOCK_TIME

#define BBRAM_REG_RX_SYNTH_LOCK_TIME   0x13E

◆ BBRAM_REG_STATIC_REG_FIX

#define BBRAM_REG_STATIC_REG_FIX   0x128

◆ BBRAM_REG_SWM_RSSI_THRESH

#define BBRAM_REG_SWM_RSSI_THRESH   0x108

◆ BBRAM_REG_SYMBOL_MODE

#define BBRAM_REG_SYMBOL_MODE   0x11C

◆ BBRAM_REG_SYNC_BYTE_0

#define BBRAM_REG_SYNC_BYTE_0   0x121

◆ BBRAM_REG_SYNC_BYTE_1

#define BBRAM_REG_SYNC_BYTE_1   0x122

◆ BBRAM_REG_SYNC_BYTE_2

#define BBRAM_REG_SYNC_BYTE_2   0x123

◆ BBRAM_REG_SYNC_CONTROL

#define BBRAM_REG_SYNC_CONTROL   0x120

◆ BBRAM_REG_TESTMODES

#define BBRAM_REG_TESTMODES   0x139

◆ BBRAM_REG_TRANSITION_CLOCK_DIV

#define BBRAM_REG_TRANSITION_CLOCK_DIV   0x13A

◆ BBRAM_REG_TX_BASE_ADR

#define BBRAM_REG_TX_BASE_ADR   0x124

◆ BBRAM_REG_TX_SYNTH_LOCK_TIME

#define BBRAM_REG_TX_SYNTH_LOCK_TIME   0x13F

◆ BBRAM_SYMBOL_MODE_DATA_WHITENING

#define BBRAM_SYMBOL_MODE_DATA_WHITENING   (0x1 << 3)

◆ BBRAM_SYMBOL_MODE_EIGHT_TEN_ENC

#define BBRAM_SYMBOL_MODE_EIGHT_TEN_ENC   (0x1 << 4)

◆ BBRAM_SYMBOL_MODE_MANCHESTER_ENC

#define BBRAM_SYMBOL_MODE_MANCHESTER_ENC   (0x1 << 6)

◆ BBRAM_SYMBOL_MODE_PROG_CRC_EN

#define BBRAM_SYMBOL_MODE_PROG_CRC_EN   (0x1 << 5)

◆ BBRAM_SYMBOL_MODE_SYMBOL_LENGTH

#define BBRAM_SYMBOL_MODE_SYMBOL_LENGTH ( x)
Value:
((x & 0x7) << 0)

◆ BBRAM_SYNC_CONTROL_SYNC_ERROR_TOL

#define BBRAM_SYNC_CONTROL_SYNC_ERROR_TOL ( x)
Value:
((x & 0x3) << 6)

◆ BBRAM_SYNC_CONTROL_SYNC_WORD_LENGTH

#define BBRAM_SYNC_CONTROL_SYNC_WORD_LENGTH ( x)
Value:
((x & 0x1F) << 0)

◆ BBRAM_TESTMODES_CONTINUOUS_RX

#define BBRAM_TESTMODES_CONTINUOUS_RX   (0x1 << 0)

◆ BBRAM_TESTMODES_CONTINUOUS_TX

#define BBRAM_TESTMODES_CONTINUOUS_TX   (0x1 << 1)

◆ BBRAM_TESTMODES_EXT_PA_LNA_ATB_CONFIG

#define BBRAM_TESTMODES_EXT_PA_LNA_ATB_CONFIG   (0x1 << 7)

◆ BBRAM_TESTMODES_PER_ENABLE

#define BBRAM_TESTMODES_PER_ENABLE   (0x1 << 2)

◆ BBRAM_TESTMODES_PER_IRQ_SELF_CLEAR

#define BBRAM_TESTMODES_PER_IRQ_SELF_CLEAR   (0x1 << 3)

◆ CMD_AES_DECRYPT

#define CMD_AES_DECRYPT   0xD2

◆ CMD_AES_DECRYPT_INIT

#define CMD_AES_DECRYPT_INIT   0xD1

◆ CMD_AES_ENCRYPT

#define CMD_AES_ENCRYPT   0xD0

◆ CMD_BB_CAL

#define CMD_BB_CAL   0xBE

◆ CMD_CONFIG_DEV

#define CMD_CONFIG_DEV   0xBB

◆ CMD_GET_RSSI

#define CMD_GET_RSSI   0xBC

◆ CMD_HW_RESET

#define CMD_HW_RESET   0xC8

◆ CMD_IR_CAL

#define CMD_IR_CAL   0xBD

◆ CMD_PHY_OFF

#define CMD_PHY_OFF   0xB0

◆ CMD_PHY_ON

#define CMD_PHY_ON   0xB1

◆ CMD_PHY_RX

#define CMD_PHY_RX   0xB2

◆ CMD_PHY_SLEEP

#define CMD_PHY_SLEEP   0xBA

◆ CMD_PHY_TX

#define CMD_PHY_TX   0xB5

◆ CMD_RAM_LOAD_DONE

#define CMD_RAM_LOAD_DONE   0xC7

◆ CMD_RAM_LOAD_INIT

#define CMD_RAM_LOAD_INIT   0xBF

◆ CMD_RS_DECODE

#define CMD_RS_DECODE   0xD2

◆ CMD_RS_ENCODE

#define CMD_RS_ENCODE   0xD0

◆ CMD_RS_ENCODE_INIT

#define CMD_RS_ENCODE_INIT   0xD1

◆ CMD_SYNC

#define CMD_SYNC   0xA2

◆ FW_STATE_AES_DECRYPT

#define FW_STATE_AES_DECRYPT   0x09

◆ FW_STATE_AES_DECRYPT_INIT

#define FW_STATE_AES_DECRYPT_INIT   0x08

◆ FW_STATE_AES_ENCRYPT

#define FW_STATE_AES_ENCRYPT   0x0A

◆ FW_STATE_BUSY

#define FW_STATE_BUSY   0x00

◆ FW_STATE_GET_RSSI

#define FW_STATE_GET_RSSI   0x05

◆ FW_STATE_INIT

#define FW_STATE_INIT   0x0F

◆ FW_STATE_IR_CAL

#define FW_STATE_IR_CAL   0x07

◆ FW_STATE_PHY_OFF

#define FW_STATE_PHY_OFF   0x11

◆ FW_STATE_PHY_ON

#define FW_STATE_PHY_ON   0x12

◆ FW_STATE_PHY_RX

#define FW_STATE_PHY_RX   0x13

◆ FW_STATE_PHY_SLEEP

#define FW_STATE_PHY_SLEEP   0x06

◆ FW_STATE_PHY_TX

#define FW_STATE_PHY_TX   0x14

◆ MCR_REG_ADC_CONFIG_HIGH

#define MCR_REG_ADC_CONFIG_HIGH   0x35A

◆ MCR_REG_ADC_CONFIG_LOW

#define MCR_REG_ADC_CONFIG_LOW   0x359

◆ MCR_REG_ADC_READBACK_HIGH

#define MCR_REG_ADC_READBACK_HIGH   0x327

◆ MCR_REG_ADC_READBACK_LOW

#define MCR_REG_ADC_READBACK_LOW   0x328

◆ MCR_REG_AGC_ADC_WORD

#define MCR_REG_AGC_ADC_WORD   0x361

◆ MCR_REG_AGC_CLK_DIVIDE

#define MCR_REG_AGC_CLK_DIVIDE   0x32F

◆ MCR_REG_AGC_CONFIG

#define MCR_REG_AGC_CONFIG   0x35C

◆ MCR_REG_AGC_GAIN_STATUS

#define MCR_REG_AGC_GAIN_STATUS   0x360

◆ MCR_REG_AGC_HIGH_THRESHOLD

#define MCR_REG_AGC_HIGH_THRESHOLD   0x35F

◆ MCR_REG_AGC_LOW_THRESHOLD

#define MCR_REG_AGC_LOW_THRESHOLD   0x35E

◆ MCR_REG_AGC_MODE

#define MCR_REG_AGC_MODE   0x35D

◆ MCR_REG_AGC_OOK_CONTROL

#define MCR_REG_AGC_OOK_CONTROL   0x35B

◆ MCR_REG_ANALOG_TEST_BUS

#define MCR_REG_ANALOG_TEST_BUS   0x3F8

◆ MCR_REG_BATTERY_MONITOR_THRESHOLD_VOLTAGE

#define MCR_REG_BATTERY_MONITOR_THRESHOLD_VOLTAGE   0x32D

◆ MCR_REG_CALIBRATION_CONTROL

#define MCR_REG_CALIBRATION_CONTROL   0x338

◆ MCR_REG_CALIBRATION_STATUS

#define MCR_REG_CALIBRATION_STATUS   0x339

◆ MCR_REG_CHIP_SHUTDOWN

#define MCR_REG_CHIP_SHUTDOWN   0x322

◆ MCR_REG_EXT_UC_CLK_DIVIDE

#define MCR_REG_EXT_UC_CLK_DIVIDE   0x32E

◆ MCR_REG_FREQUENCY_ERROR_READBACK

#define MCR_REG_FREQUENCY_ERROR_READBACK   0x372

◆ MCR_REG_GPIO_CONFIGURE

#define MCR_REG_GPIO_CONFIGURE   0x3FA

◆ MCR_REG_IMAGE_REJECT_CAL_CONFIG

#define MCR_REG_IMAGE_REJECT_CAL_CONFIG   0x319

◆ MCR_REG_INTERRUPT_SOURCE_0

#define MCR_REG_INTERRUPT_SOURCE_0   0x336

◆ MCR_REG_INTERRUPT_SOURCE_1

#define MCR_REG_INTERRUPT_SOURCE_1   0x337

◆ MCR_REG_MAX_AFC_RANGE

#define MCR_REG_MAX_AFC_RANGE   0x315

◆ MCR_REG_OSC_CONFIG

#define MCR_REG_OSC_CONFIG   0x3D2

◆ MCR_REG_PA_LEVEL_MCR

#define MCR_REG_PA_LEVEL_MCR   0x307

◆ MCR_REG_POWERDOWN_AUX

#define MCR_REG_POWERDOWN_AUX   0x325

◆ MCR_REG_POWERDOWN_RX

#define MCR_REG_POWERDOWN_RX   0x324

◆ MCR_REG_RCOSC_CAL_READBACK_HIGH

#define MCR_REG_RCOSC_CAL_READBACK_HIGH   0x34F

◆ MCR_REG_RCOSC_CAL_READBACK_LOW

#define MCR_REG_RCOSC_CAL_READBACK_LOW   0x350

◆ MCR_REG_RSSI_READBACK

#define MCR_REG_RSSI_READBACK   0x312

◆ MCR_REG_RSSI_TSTMUX_SEL

#define MCR_REG_RSSI_TSTMUX_SEL   0x3F9

◆ MCR_REG_RXBB_CAL_CALWRD_OVERWRITE

#define MCR_REG_RXBB_CAL_CALWRD_OVERWRITE   0x346

◆ MCR_REG_RXBB_CAL_CALWRD_READBACK

#define MCR_REG_RXBB_CAL_CALWRD_READBACK   0x345

◆ MCR_REG_TEST_DAC_GAIN

#define MCR_REG_TEST_DAC_GAIN   0x3FD

◆ MCR_REG_VCO_AMPL_OVRW_VAL

#define MCR_REG_VCO_AMPL_OVRW_VAL   0x3CC

◆ MCR_REG_VCO_AMPL_READBACK

#define MCR_REG_VCO_AMPL_READBACK   0x3DB

◆ MCR_REG_VCO_BAND_OVRW_VAL

#define MCR_REG_VCO_BAND_OVRW_VAL   0x3CB

◆ MCR_REG_VCO_BAND_READBACK

#define MCR_REG_VCO_BAND_READBACK   0x3DA

◆ MCR_REG_VCO_CAL_CFG

#define MCR_REG_VCO_CAL_CFG   0x3D0

◆ MCR_REG_VCO_OVRW_EN

#define MCR_REG_VCO_OVRW_EN   0x3CD

◆ MCR_REG_WUC_CONFIG_HIGH

#define MCR_REG_WUC_CONFIG_HIGH   0x30C

◆ MCR_REG_WUC_CONFIG_LOW

#define MCR_REG_WUC_CONFIG_LOW   0x30D

◆ MCR_REG_WUC_FLAG_RESET

#define MCR_REG_WUC_FLAG_RESET   0x310

◆ MCR_REG_WUC_STATUS

#define MCR_REG_WUC_STATUS   0x311

◆ MCR_REG_WUC_VALUE_HIGH

#define MCR_REG_WUC_VALUE_HIGH   0x30E

◆ MCR_REG_WUC_VALUE_LOW

#define MCR_REG_WUC_VALUE_LOW   0x30F

◆ SPI_MEM_RD

#define SPI_MEM_RD   0x38

◆ SPI_MEM_WR

#define SPI_MEM_WR   0x18

◆ SPI_MEMR_RD

#define SPI_MEMR_RD   0x28

◆ SPI_MEMR_WR

#define SPI_MEMR_WR   0x08

◆ SPI_NOP

#define SPI_NOP   0xFF

◆ STATUS_CMD_READY

#define STATUS_CMD_READY   (0x1 << 5)

◆ STATUS_FW_STATE

#define STATUS_FW_STATE   (0x1F << 0)

◆ STATUS_IRQ_STATUS

#define STATUS_IRQ_STATUS   (0x1 << 6)

◆ STATUS_SPI_READY

#define STATUS_SPI_READY   (0x1 << 7)

Function Documentation

◆ adf7023_get_ram()

void adf7023_get_ram ( struct adf7023_dev * dev,
uint32_t address,
uint32_t length,
uint8_t * data )

Reads data from the RAM.

Parameters
dev- The device structure.
address- Start address.
length- Number of bytes to write.
data- Read buffer.
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◆ adf7023_get_status()

void adf7023_get_status ( struct adf7023_dev * dev,
uint8_t * status )

Reads the status word of the ADF7023.

Parameters
dev- The device structure.
status- Status word.
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◆ adf7023_init()

int32_t adf7023_init ( struct adf7023_dev ** device,
struct adf7023_init_param init_param )

Initializes the ADF7023.

Parameters
device- The device structure.
init_param- The structure that contains the device initial parameters.
Returns
ret - Result of the initialization procedure. Example: 0 - if initialization was successful; -1 - if initialization was unsuccessful.

◆ adf7023_receive_packet()

void adf7023_receive_packet ( struct adf7023_dev * dev,
uint8_t * packet,
uint8_t * length )

Receives one packet.

Parameters
dev- The device structure.
packet- Data buffer.
length- Number of received bytes.

◆ adf7023_remove()

int32_t adf7023_remove ( struct adf7023_dev * dev)

Free the resources allocated by adf7023_init().

Parameters
dev- The device structure.
Returns
0 in case of success, negative error code otherwise.

◆ adf7023_set_channel_frequency()

void adf7023_set_channel_frequency ( struct adf7023_dev * dev,
uint32_t ch_freq )

Sets the channel frequency.

Parameters
dev- The device structure.
ch_freq- Channel frequency.

◆ adf7023_set_command()

void adf7023_set_command ( struct adf7023_dev * dev,
uint8_t command )

Initiates a command.

Parameters
dev- The device structure.
command- Command.
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◆ adf7023_set_data_rate()

void adf7023_set_data_rate ( struct adf7023_dev * dev,
uint32_t data_rate )

Sets the data rate.

Parameters
dev- The device structure.
data_rate- Data rate.

◆ adf7023_set_frequency_deviation()

void adf7023_set_frequency_deviation ( struct adf7023_dev * dev,
uint32_t freq_dev )

Sets the frequency deviation.

Parameters
dev- The device structure.
freq_dev- Frequency deviation.

◆ adf7023_set_fw_state()

void adf7023_set_fw_state ( struct adf7023_dev * dev,
uint8_t fw_state )

Sets a FW state and waits until the device enters in that state.

Parameters
dev- The device structure.
fw_state- FW state.
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◆ adf7023_set_ram()

void adf7023_set_ram ( struct adf7023_dev * dev,
uint32_t address,
uint32_t length,
uint8_t * data )

Writes data to RAM.

Parameters
dev- The device structure.
address- Start address.
length- Number of bytes to write.
data- Write buffer.
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◆ adf7023_transmit_packet()

void adf7023_transmit_packet ( struct adf7023_dev * dev,
uint8_t * packet,
uint8_t length )

Transmits one packet.

Parameters
dev- The device structure.
packet- Data buffer.
length- Number of bytes to transmit.
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