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#define | ADIN1300_MII_CONTROL 0x0000 |
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#define | ADIN1300_LOOPBACK_MASK NO_OS_BIT(14) |
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#define | ADIN1300_SPEED_SEL_LSB_MASK NO_OS_BIT(13) |
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#define | ADIN1300_AUTONEG_EN_MASK NO_OS_BIT(12) |
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#define | ADIN1300_RESTART_ANEG_MASK NO_OS_BIT(9) |
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#define | ADIN1300_DPLX_MODE_MASK NO_OS_BIT(8) |
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#define | ADIN1300_SPEED_SEL_MSB_MASK NO_OS_BIT(6) |
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#define | ADIN1300_MII_STATUS 0x1 |
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#define | ADIN1300_AUTONEG_DONE_MASK NO_OS_BIT(5) |
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#define | ADIN1300_REM_FLT_LAT_MASK NO_OS_BIT(4) |
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#define | ADIN1300_LINK_STAT_LAT_MASK NO_OS_BIT(2) |
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#define | ADIN1300_JABBER_DET_LAT_MASK NO_OS_BIT(1) |
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#define | ADIN1300_PHY_ID_1 0x2 |
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#define | ADIN1300_PHY_ID_2 0x3 |
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#define | ADIN1300_AUTONEG_ADV 0x04 |
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#define | ADIN1300_FD_100_ADV_MASK NO_OS_BIT(8) |
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#define | ADIN1300_HD_100_ADV_MASK NO_OS_BIT(7) |
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#define | ADIN1300_FD_10_ADV_MASK NO_OS_BIT(6) |
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#define | ADIN1300_HD_10_ADV_MASK NO_OS_BIT(5) |
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#define | ADIN1300_SELECTOR_ADV_MASK NO_OS_GENMASK(4, 0) |
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#define | ADIN1300_MSTR_SLV_CONTROL 0x09 |
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#define | ADIN1300_FD_1000_ADV_MASK NO_OS_BIT(9) |
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#define | ADIN1300_HD_1000_ADV_MASK NO_OS_BIT(8) |
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#define | ADIN1300_PHY_CTRL_1 0x0012 |
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#define | ADIN1300_DIAG_CLK_EN_MASK NO_OS_BIT(2) |
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#define | ADIN1300_PHY_CTRL_STATUS_1 0x0013 |
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#define | ADIN1300_LB_ALL_DIG_SEL_MASK NO_OS_BIT(12) |
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#define | ADIN1300_RX_ERR_CNT 0x0014 |
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#define | ADIN1300_PHY_CTRL_2 0x0016 |
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#define | ADIN1300_DN_SPEED_TO_100_EN_MASK NO_OS_BIT(11) |
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#define | ADIN1300_DN_SPEED_TO_10_EN_MASK NO_OS_BIT(10) |
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#define | ADIN1300_CLK_CNTRL_MASK NO_OS_GENMASK(3, 1) |
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#define | ADIN1300_PHY_CTRL_3 0x0017 |
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#define | ADIN1300_LINK_EN_MASK NO_OS_BIT(13) |
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#define | ADIN1300_IRQ_MASK 0x0018 |
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#define | ADIN1300_IRQ_STATUS 0x0019 |
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#define | ADIN1300_LNK_STAT_CHNG_IRQ_MASK NO_OS_BIT(2) |
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#define | ADIN1300_SPEED_CHG_IRQ_MASK NO_OS_BIT(1) |
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#define | ADIN1300_HW_IRQ_EN_MASK NO_OS_BIT(0) |
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#define | ADIN1300_PHY_STATUS_1 0x001a |
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#define | ADIN1300_HCD_TECH_MASK NO_OS_GENMASK(9, 7) |
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#define | ADIN1300_LINK_STAT_MASK NO_OS_BIT(6) |
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#define | ADIN1300_PHY_STATUS_2 0x001f |
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#define | ADIN1300_FC_EN NO_OS_MDIO_C45_ADDR(0x1e, 0x9403) |
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#define | ADIN1300_FC_EN_MASK NO_OS_BIT(0) |
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#define | ADIN1300_FC_TX_SEL NO_OS_MDIO_C45_ADDR(0x1e, 0x9407) |
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#define | ADIN1300_FC_TX_SEL_MASK NO_OS_BIT(0) |
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#define | ADIN1300_FC_FRM_CNT_H NO_OS_MDIO_C45_ADDR(0x1e, 0x940a) |
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#define | ADIN1300_FC_FRM_CNT_L NO_OS_MDIO_C45_ADDR(0x1e, 0x940b) |
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#define | ADIN1300_FC_LEN_ERR_CNT NO_OS_MDIO_C45_ADDR(0x1e, 0x940c) |
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#define | ADIN1300_FC_ALGN_ERR_CNT NO_OS_MDIO_C45_ADDR(0x1e, 0x940d) |
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#define | ADIN1300_FC_SYMB_ERR_CNT NO_OS_MDIO_C45_ADDR(0x1e, 0x940e) |
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#define | ADIN1300_FC_OSZ_ERR_CNT NO_OS_MDIO_C45_ADDR(0x1e, 0x940f) |
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#define | ADIN1300_FC_USZ_ERR_CNT NO_OS_MDIO_C45_ADDR(0x1e, 0x9410) |
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#define | ADIN1300_FG_EN NO_OS_MDIO_C45_ADDR(0x1e, 0x9415) |
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#define | ADIN1300_FG_EN_MASK NO_OS_BIT(0) |
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#define | ADIN1300_FG_CNTRL_RSTRT NO_OS_MDIO_C45_ADDR(0x1e, 0x9416) |
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#define | ADIN1300_FG_RSTRT_MASK NO_OS_BIT(3) |
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#define | ADIN1300_FG_CNTRL_MASK NO_OS_GENMASK(2, 0) |
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#define | ADIN1300_FG_FRM_LEN NO_OS_MDIO_C45_ADDR(0x1e, 0x941a) |
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#define | ADIN1300_FG_DONE NO_OS_MDIO_C45_ADDR(0x1e, 0x941e) |
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#define | ADIN1300_FG_DONE_MASK NO_OS_BIT(0) |
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#define | ADIN1300_GE_SFT_RST NO_OS_MDIO_C45_ADDR(0x1e, 0xff0c) |
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#define | ADIN1300_GE_SFT_RST_MASK NO_OS_BIT(0) |
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#define | ADIN1300_GE_CLK_CFG NO_OS_MDIO_C45_ADDR(0x1e, 0xff1f) |
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#define | ADIN1300_GE_CLK_RCVR_125_EN_MASK NO_OS_BIT(5) |
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#define | ADIN1300_GE_CLK_FREE_125_EN_MASK NO_OS_BIT(4) |
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#define | ADIN1300_GE_REF_CLK_EN_MASK NO_OS_BIT(3) |
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#define | ADIN1300_GE_CLK_HRT_RCVR_EN_MASK NO_OS_BIT(2) |
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#define | ADIN1300_GE_CLK_HRT_FREE_EN_MASK NO_OS_BIT(1) |
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#define | ADIN1300_GE_CLK_25_EN_MASK NO_OS_BIT(0) |
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#define | ADIN1300_GE_RGMII_CFG NO_OS_MDIO_C45_ADDR(0x1e, 0xff23) |
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#define | ADIN1300_GE_RGMII_100_LOW_LTNCY_EN_MSK NO_OS_BIT(10) |
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#define | ADIN1300_GE_RGMII_10_LOW_LTNCY_EN_MSK NO_OS_BIT(9) |
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#define | ADIN1300_GE_RGMII_RX_SEL_MASK NO_OS_GENMASK(8, 6) |
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#define | ADIN1300_GE_RGMII_GTX_SEL_MASK NO_OS_GENMASK(5, 3) |
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#define | ADIN1300_GE_RGMII_RX_ID_EN_MASK NO_OS_BIT(2) |
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#define | ADIN1300_GE_RGMII_TX_ID_EN_MASK NO_OS_BIT(1) |
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#define | ADIN1300_GE_RGMII_EN_MASK NO_OS_BIT(0) |
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#define | ADIN1300_GE_B10_REGEN_PRE NO_OS_MDIO_C45_ADDR(0x1e, 0xff38) |
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#define | ADIN1300_GE_B10_REGEN_PRE_MSK NO_OS_BIT(0) |
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int | adin1300_init (struct adin1300_desc **dev, struct adin1300_init_param *param) |
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int | adin1300_remove (struct adin1300_desc *dev) |
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int | adin1300_write (struct adin1300_desc *dev, uint32_t addr, uint16_t val) |
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int | adin1300_read (struct adin1300_desc *dev, uint32_t addr, uint16_t *val) |
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int | adin1300_write_bits (struct adin1300_desc *dev, uint32_t addr, uint16_t val, uint16_t bitmask) |
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int | adin1300_soft_reset (struct adin1300_desc *dev) |
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int | adin1300_hard_reset (struct adin1300_desc *dev) |
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int | adin1300_config_rgmii (struct adin1300_desc *dev, struct adin1300_rgmii_config rgmii) |
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int | adin1300_config_gp_clk (struct adin1300_desc *dev, bool on, enum adin1300_gp_clk_source source) |
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int | adin1300_config_clk25_ref (struct adin1300_desc *dev, bool on) |
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int | adin1300_autoneg (struct adin1300_desc *dev, bool on) |
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int | adin1300_config_speed (struct adin1300_desc *dev, enum adin1300_speed speed_cap) |
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enum adin1300_speed | adin1300_resolved_speed (struct adin1300_desc *dev) |
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bool | adin1300_link_is_up (struct adin1300_desc *dev) |
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