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Classes | Macros | Enumerations | Functions
adin1320.h File Reference

Header file of the ADIN1320 driver. More...

#include <stdbool.h>
#include <stdint.h>
#include "no_os_util.h"
#include "no_os_mdio.h"
Include dependency graph for adin1320.h:

Classes

struct  adin1320_rgmii_config
 
struct  adin1320_mii_status
 
struct  adin1320_init_param
 
struct  adin1320_desc
 

Macros

#define ADIN1320_MII_CONTROL   0x0000
 
#define ADIN1320_SFT_RST_MASK   NO_OS_BIT(15)
 
#define ADIN1320_LOOPBACK_MASK   NO_OS_BIT(14)
 
#define ADIN1320_SPEED_SEL_LSB_MASK   NO_OS_BIT(13)
 
#define ADIN1320_AUTONEG_EN_MASK   NO_OS_BIT(12)
 
#define ADIN1320_SFT_PD_MASK   NO_OS_BIT(11)
 
#define ADIN1320_RESTART_ANEG_MASK   NO_OS_BIT(9)
 
#define ADIN1320_DPLX_MODE_MASK   NO_OS_BIT(8)
 
#define ADIN1320_SPEED_SEL_MSB_MASK   NO_OS_BIT(6)
 
#define ADIN1320_MII_STATUS   0x0001
 
#define ADIN1320_AUTONEG_DONE_MASK   NO_OS_BIT(5)
 
#define ADIN1320_REM_FLT_LAT_MASK   NO_OS_BIT(4)
 
#define ADIN1320_LINK_STAT_LAT_MASK   NO_OS_BIT(2)
 
#define ADIN1320_JABBER_DET_LAT_MASK   NO_OS_BIT(1)
 
#define ADIN1320_PHY_ID_1   0x0002
 
#define ADIN1320_PHY_ID_2   0x0003
 
#define ADIN1320_MODEL_NUM_MASK   NO_OS_GENMASK(9, 4)
 
#define ADIN1320_REV_NUM_MASK   NO_OS_GENMASK(3, 0)
 
#define ADIN1320_AUTONEG_ADV   0x0004
 
#define ADIN1320_FD_100_ADV_MASK   NO_OS_BIT(8)
 
#define ADIN1320_HD_100_ADV_MASK   NO_OS_BIT(7)
 
#define ADIN1320_FD_10_ADV_MASK   NO_OS_BIT(6)
 
#define ADIN1320_HD_10_ADV_MASK   NO_OS_BIT(5)
 
#define ADIN1320_SELECTOR_ADV_MASK   NO_OS_GENMASK(4, 0)
 
#define ADIN1320_LP_ABILITY   0x0005
 
#define ADIN1320_AUTONEG_EXP   0x0006
 
#define ADIN1320_TX_NEXT_PAGE   0x0007
 
#define ADIN1320_LP_RX_NEXT_PAGE   0x0008
 
#define ADIN1320_MSTR_SLV_CONTROL   0x0009
 
#define ADIN1320_FD_1000_ADV_MASK   NO_OS_BIT(9)
 
#define ADIN1320_HD_1000_ADV_MASK   NO_OS_BIT(8)
 
#define ADIN1320_MAN_MSTR_ADV_MASK   NO_OS_BIT(11)
 
#define ADIN1320_MAN_MSTR_SLV_EN_ADV_MASK   NO_OS_BIT(12)
 
#define ADIN1320_MSTR_SLV_STATUS   0x000a
 
#define ADIN1320_MSTR_RSLVD_MASK   NO_OS_BIT(14)
 
#define ADIN1320_MSTR_SLV_FLT_MASK   NO_OS_BIT(15)
 
#define ADIN1320_EXT_STATUS   0x000f
 
#define ADIN1320_EXT_REG_PTR   0x0010
 
#define ADIN1320_EXT_REG_DATA   0x0011
 
#define ADIN1320_PHY_CTRL_1   0x0012
 
#define ADIN1320_AUTO_MDI_EN_MASK   NO_OS_BIT(10)
 
#define ADIN1320_MAN_MDIX_MASK   NO_OS_BIT(9)
 
#define ADIN1320_DIAG_CLK_EN_MASK   NO_OS_BIT(2)
 
#define ADIN1320_PHY_CTRL_STATUS_1   0x0013
 
#define ADIN1320_LB_ALL_DIG_SEL_MASK   NO_OS_BIT(12)
 
#define ADIN1320_PHY_CTRL_STATUS_2   0x0015
 
#define ADIN1320_PHY_IN_NRG_PD_MASK   NO_OS_BIT(1)
 
#define ADIN1320_NRG_PD_TX_EN_MASK   NO_OS_BIT(2)
 
#define ADIN1320_NRG_PD_EN_MASK   NO_OS_BIT(3)
 
#define ADIN1320_PHY_CTRL_2   0x0016
 
#define ADIN1320_DN_SPEED_TO_100_EN_MASK   NO_OS_BIT(11)
 
#define ADIN1320_DN_SPEED_TO_10_EN_MASK   NO_OS_BIT(10)
 
#define ADIN1320_CLK_CNTRL_MASK   NO_OS_GENMASK(3, 1)
 
#define ADIN1320_PHY_CTRL_3   0x0017
 
#define ADIN1320_NUM_SPEED_RETRY_MASK   NO_OS_GENMASK(12, 10)
 
#define ADIN1320_LINK_EN_MASK   NO_OS_BIT(13)
 
#define ADIN1320_IRQ_MASK   0x0018
 
#define ADIN1320_CBL_DIAG_IRQ_EN_MASK   NO_OS_BIT(10)
 
#define ADIN1320_MDIO_SYNC_IRQ_EN_MASK   NO_OS_BIT(9)
 
#define ADIN1320_AN_STAT_CHNG_IRQ_EN_MASK   NO_OS_BIT(8)
 
#define ADIN1320_FC_FG_IRQ_EN_MASK   NO_OS_BIT(7)
 
#define ADIN1320_PAGE_RX_IRQ_EN_MASK   NO_OS_BIT(6)
 
#define ADIN1320_IDLE_ERR_CNT_IRQ_EN_MASK   NO_OS_BIT(5)
 
#define ADIN1320_FIFO_OU_IRQ_EN_MASK   NO_OS_BIT(4)
 
#define ADIN1320_RX_STAT_CHNG_IRQ_EN_MASK   NO_OS_BIT(3)
 
#define ADIN1320_LNK_STAT_CHNG_IRQ_EN_MASK   NO_OS_BIT(2)
 
#define ADIN1320_SPEED_CHG_IRQ_EN_MASK   NO_OS_BIT(1)
 
#define ADIN1320_HW_IRQ_EN_MASK   NO_OS_BIT(0)
 
#define ADIN1320_IRQ_STATUS   0x0019
 
#define ADIN1320_CBL_DIAG_IRQ_STAT_MASK   NO_OS_BIT(10)
 
#define ADIN1320_MDIO_SYNC_IRQ_STAT_MASK   NO_OS_BIT(9)
 
#define ADIN1320_AN_STAT_CHNG_IRQ_STAT_MASK   NO_OS_BIT(8)
 
#define ADIN1320_FC_FG_IRQ_STAT_MASK   NO_OS_BIT(7)
 
#define ADIN1320_PAGE_RX_IRQ_STAT_MASK   NO_OS_BIT(6)
 
#define ADIN1320_IDLE_ERR_CNT_IRQ_STAT_MASK   NO_OS_BIT(5)
 
#define ADIN1320_FIFO_OU_IRQ_STAT_MASK   NO_OS_BIT(4)
 
#define ADIN1320_RX_STAT_CHNG_IRQ_STAT_MASK   NO_OS_BIT(3)
 
#define ADIN1320_LNK_STAT_CHNG_IRQ_STAT_MASK   NO_OS_BIT(2)
 
#define ADIN1320_SPEED_CHNG_IRQ_STAT_MASK   NO_OS_BIT(1)
 
#define ADIN1320_IRQ_PENDING_MASK   NO_OS_BIT(0)
 
#define ADIN1320_PHY_STATUS_1   0x001a
 
#define ADIN1320_HCD_TECH_MASK   NO_OS_GENMASK(9, 7)
 
#define ADIN1320_LINK_STAT_MASK   NO_OS_BIT(6)
 
#define ADIN1320_LED_CTRL_1   0x001b
 
#define ADIN1320_LED_3_EXT_CFG_EN_MASK   NO_OS_BIT(13)
 
#define ADIN1320_LED_2_EXT_CFG_EN_MASK   NO_OS_BIT(12)
 
#define ADIN1320_LED_1_EXT_CFG_EN_MASK   NO_OS_BIT(11)
 
#define ADIN1320_LED_0_EXT_CFG_EN_MASK   NO_OS_BIT(10)
 
#define ADIN1320_LED_PAT_PAUSE_DUR_MASK   NO_OS_GENMASK(7, 4)
 
#define ADIN1320_LED_PUL_STR_DUR_SEL_MASK   NO_OS_GENMASK(3, 2)
 
#define ADIN1320_LED_OE_N_MASK   NO_OS_BIT(1)
 
#define ADIN1320_LED_PUL_STR_EN_MASK   NO_OS_BIT(0)
 
#define ADIN1320_LED_CTRL_2   0x001c
 
#define ADIN1320_LED_0_CFG_MASK   NO_OS_GENMASK(3, 0)
 
#define ADIN1320_LED_1_CFG_MASK   NO_OS_GENMASK(7, 4)
 
#define ADIN1320_LED_2_CFG_MASK   NO_OS_GENMASK(11, 8)
 
#define ADIN1320_LED_3_CFG_MASK   NO_OS_GENMASK(15, 12)
 
#define ADIN1320_LED_CTRL_3   0x001d
 
#define ADIN1320_LED_PAT_SEL_MASK   NO_OS_GENMASK(15, 14)
 
#define ADIN1320_LED_PAT_TICK_DUR_MASK   NO_OS_GENMASK(13, 8)
 
#define ADIN1320_LED_PAT_MASK   NO_OS_GENMASK(7, 0)
 
#define ADIN1320_PHY_STATUS_2   0x001f
 
#define ADIN1320_EEE_ADV   NO_OS_MDIO_C45_ADDR(0x1e, 0x8001)
 
#define ADIN1320_EEE_1000_KX_ADV_MASK   NO_OS_BIT(4)
 
#define ADIN1320_EEE_1000_ADV_MASK   NO_OS_BIT(2)
 
#define ADIN1320_EEE_100_ADV_MASK   NO_OS_BIT(1)
 
#define ADIN1320_SD_CONTROL   NO_OS_MDIO_C45_ADDR(0x1e, 0xfc00)
 
#define ADIN1320_SD_RESTART_ANEG_MASK   NO_OS_BIT(9)
 
#define ADIN1320_SD_STATUS   NO_OS_MDIO_C45_ADDR(0x1e, 0xfc01)
 
#define ADIN1320_SD_AN_DONE_MASK   NO_OS_BIT(5)
 
#define ADIN1320_SD_REM_FLT_LH_MASK   NO_OS_BIT(4)
 
#define ADIN1320_SD_LINK_STAT_OK_LL_MASK   NO_OS_BIT(2)
 
#define ADIN1320_SD_JABBER_DET_LH_MASK   NO_OS_BIT(1)
 
#define ADIN1320_SD_AUTONEG_ADV   NO_OS_MDIO_C45_ADDR(0x1e, 0xfc04)
 
#define ADIN1320_SD_HD_1000ADV_MASK   NO_OS_BIT(6)
 
#define ADIN1320_SD_FD_1000ADV_MASK   NO_OS_BIT(5)
 
#define ADIN1320_SD_IRQ_MASK   NO_OS_MDIO_C45_ADDR(0x1e, 0xfc18)
 
#define ADIN1320_SD_OS_RX_PLL_LCK_LOST_IRQ_EN_MASK   NO_OS_BIT(10)
 
#define ADIN1320_SD_RX_PLL_LCK_LOST_IRQ_EN_MASK   NO_OS_BIT(9)
 
#define ADIN1320_SD_TX_PLL_LCK_LOST_IRQ_EN_MASK   NO_OS_BIT(8)
 
#define ADIN1320_SD_AN_STAT_CHG_IRQ_EN_MASK   NO_OS_BIT(7)
 
#define ADIN1320_SD_FC_FG_IRQ_EN_MASK   NO_OS_BIT(6)
 
#define ADIN1320_SD_PAGE_RX_IRQ_EN_MASK   NO_OS_BIT(5)
 
#define ADIN1320_SD_FIFO_OU_IRQ_EN_MASK   NO_OS_BIT(4)
 
#define ADIN1320_SD_LINK_STAT_CHG_IRQ_EN_MASK   NO_OS_BIT(1)
 
#define ADIN1320_SD_MDIO_ERR_IRQ_EN_MASK   NO_OS_BIT(0)
 
#define ADIN1320_SD_IRQ_STATUS   NO_OS_MDIO_C45_ADDR(0x1e, 0xfc19)
 
#define ADIN1320_SD_OS_RX_PLL_LCK_LOST_IRQ_LH_MASK   NO_OS_BIT(10)
 
#define ADIN1320_SD_RX_PLL_LCK_LOST_IRQ_LH_MASK   NO_OS_BIT(9)
 
#define ADIN1320_SD_TX_PLL_LCK_LOST_IRQ_LH_MASK   NO_OS_BIT(8)
 
#define ADIN1320_SD_AN_CHG_IRQ_LH_MASK   NO_OS_BIT(7)
 
#define ADIN1320_SD_FC_FG_IRQ_LH_MASK   NO_OS_BIT(6)
 
#define ADIN1320_SD_PAGE_RX_IRQ_LH_MASK   NO_OS_BIT(5)
 
#define ADIN1320_SD_FIFO_OU_IRQ_LH_MASK   NO_OS_BIT(4)
 
#define ADIN1320_SD_LINK_STAT_CHG_LH_MASK   NO_OS_BIT(1)
 
#define ADIN1320_SD_MDIO_ERR_LH_MASK   NO_OS_BIT(0)
 
#define ADIN1320_SD_FIB_LED_CFG_0   NO_OS_MDIO_C45_ADDR(0x1e, 0xfcaa)
 
#define ADIN1320_SD_FIB_LED_CFG_0_MASK   NO_OS_GENMASK(3, 0)
 
#define ADIN1320_SD_FIB_LED_CFG_1   NO_OS_MDIO_C45_ADDR(0x1e, 0xfcab)
 
#define ADIN1320_SD_FIB_LED_CFG_1_MASK   NO_OS_GENMASK(3, 0)
 
#define ADIN1320_SD_FIB_LED_CFG_2   NO_OS_MDIO_C45_ADDR(0x1e, 0xfcac)
 
#define ADIN1320_SD_FIB_LED_CFG_2_MASK   NO_OS_GENMASK(3, 0)
 
#define ADIN1320_SD_FIB_LED_CFG_3   NO_OS_MDIO_C45_ADDR(0x1e, 0xfcad)
 
#define ADIN1320_SD_FIB_LED_CFG_3_MASK   NO_OS_GENMASK(3, 0)
 
#define ADIN1320_GE_PHY_ID_1   NO_OS_MDIO_C45_ADDR(0x1e, 0xff00)
 
#define ADIN1320_GE_PHY_ID_1_RESET   0x0283
 
#define ADIN1320_GE_PHY_ID_2   NO_OS_MDIO_C45_ADDR(0x1e, 0xff01)
 
#define ADIN1320_GE_MODEL_NUM_MASK   NO_OS_GENMASK(9, 4)
 
#define ADIN1320_GE_REV_NUM_MASK   NO_OS_GENMASK(3, 0)
 
#define ADIN1320_GE_SFT_RST   NO_OS_MDIO_C45_ADDR(0x1e, 0xff0c)
 
#define ADIN1320_GE_SFT_RST_MASK   NO_OS_BIT(0)
 
#define ADIN1320_GE_SFT_RST_CFG_EN   NO_OS_MDIO_C45_ADDR(0x1e, 0xff0d)
 
#define ADIN1320_GE_SFT_RST_CFG_EN_MASK   NO_OS_BIT(0)
 
#define ADIN1320_GE_IRQ_EN   NO_OS_MDIO_C45_ADDR(0x1e, 0xff1d)
 
#define ADIN1320_GE_WOL_WAKE_IRQ_EN_MASK   NO_OS_BIT(7)
 
#define ADIN1320_GE_IRQ_LAT   NO_OS_MDIO_C45_ADDR(0x1e, 0xff1e)
 
#define ADIN1320_GE_WOL_WAKE_IRQ_LH_MASK   NO_OS_BIT(7)
 
#define ADIN1320_GE_CLK_CFG   NO_OS_MDIO_C45_ADDR(0x1e, 0xff1f)
 
#define ADIN1320_SD_RX_CLK_125_EN_MASK   NO_OS_BIT(10)
 
#define ADIN1320_SD_TX_CLK_125_EN_MASK   NO_OS_BIT(9)
 
#define ADIN1320_SD_RX_CLK_HRT_EN_MASK   NO_OS_BIT(8)
 
#define ADIN1320_SD_TX_CLK_HRT_EN_MASK   NO_OS_BIT(7)
 
#define ADIN1320_GE_CLK_RCVR_125_EN_MASK   NO_OS_BIT(5)
 
#define ADIN1320_GE_CLK_FREE_125_EN_MASK   NO_OS_BIT(4)
 
#define ADIN1320_GE_REF_CLK_EN_MASK   NO_OS_BIT(3)
 
#define ADIN1320_GE_CLK_HRT_RCVR_EN_MASK   NO_OS_BIT(2)
 
#define ADIN1320_GE_CLK_HRT_FREE_EN_MASK   NO_OS_BIT(1)
 
#define ADIN1320_GE_CLK_25_EN_MASK   NO_OS_BIT(0)
 
#define ADIN1320_GE_RGMII_CFG   NO_OS_MDIO_C45_ADDR(0x1e, 0xff23)
 
#define ADIN1320_GE_RGMII_CFG_RESERVED_MASK   NO_OS_GENMASK(15, 11)
 
#define ADIN1320_GE_RGMII_100_LOW_LTNCY_EN_MASK   NO_OS_BIT(10)
 
#define ADIN1320_GE_RGMII_10_LOW_LTNCY_EN_MASK   NO_OS_BIT(9)
 
#define ADIN1320_GE_RGMII_RX_SEL_MASK   NO_OS_GENMASK(8, 6)
 
#define ADIN1320_GE_RGMII_GTX_SEL_MASK   NO_OS_GENMASK(5, 3)
 
#define ADIN1320_GE_RGMII_RX_ID_EN_MASK   NO_OS_BIT(2)
 
#define ADIN1320_GE_RGMII_TX_ID_EN_MASK   NO_OS_BIT(1)
 
#define ADIN1320_GE_RGMII_EN_MASK   NO_OS_BIT(0)
 
#define ADIN1320_GE_RMII_CFG   NO_OS_MDIO_C45_ADDR(0x1e, 0xff24)
 
#define ADIN1320_GE_RMII_EN_MASK   NO_OS_BIT(0)
 
#define ADIN1320_GE_RMII_FIFO_RST_MASK   NO_OS_BIT(7)
 
#define ADIN1320_GE_PHY_LED_CFG   NO_OS_MDIO_C45_ADDR(0x1e, 0xff29)
 
#define ADIN1320_LED_D_INV_EN_MASK   NO_OS_BIT(6)
 
#define ADIN1320_LED_C_INV_EN_MASK   NO_OS_BIT(5)
 
#define ADIN1320_LED_B_INV_EN_MASK   NO_OS_BIT(4)
 
#define ADIN1320_LED_A_INV_EN_MASK   NO_OS_BIT(3)
 
#define ADIN1320_GE_B10_REGEN_PRE   NO_OS_MDIO_C45_ADDR(0x1e, 0xff38)
 
#define ADIN1320_GE_B10_REGEN_PRE_MASK   NO_OS_BIT(0)
 
#define ADIN1320_GE_SD_CFG   NO_OS_MDIO_C45_ADDR(0x1e, 0xff53)
 
#define ADIN1320_SD_LINK_TYPE_CFG_MASK   NO_OS_GENMASK(7, 5)
 
#define ADIN1320_SD_AUTONEG_EN_CFG_MASK   NO_OS_BIT(2)
 
#define ADIN1320_SD_SGMII_EN_MASK   NO_OS_BIT(0)
 
#define ADIN1320_GE_MSEL_AUTO_STAT   NO_OS_MDIO_C45_ADDR(0x1e, 0xff57)
 
#define ADIN1320_GE_MSEL_AUTO_SD_MASK   NO_OS_BIT(1)
 
#define ADIN1320_GE_MSEL_AUTO_GE_MASK   NO_OS_BIT(0)
 
#define ADIN1320_GE_WOL_SYS_CNTRL   NO_OS_MDIO_C45_ADDR(0x1e, 0xff78)
 
#define ADIN1320_GE_WOL_WAKE_INV_EN_MASK   NO_OS_BIT(1)
 
#define ADIN1320_GE_WOL_2_PHY_SD_SEL_MASK   NO_OS_BIT(0)
 
#define ADIN1320_GE_WOL_EN   NO_OS_MDIO_C45_ADDR(0x1e, 0xff79)
 
#define ADIN1320_GE_WOL_EN_MASK   NO_OS_BIT(0)
 
#define ADIN1320_GE_WOL_WAKE_CNTRL   NO_OS_MDIO_C45_ADDR(0x1e, 0xff7a)
 
#define ADIN1320_GE_WOL_KEY_ERR_WAKE_EN_MASK   NO_OS_BIT(1)
 
#define ADIN1320_GE_WOL_LS_CHG_WAKE_EN_MASK   NO_OS_BIT(0)
 
#define ADIN1320_GE_WOL_SIG_CNTRL   NO_OS_MDIO_C45_ADDR(0x1e, 0xff7b)
 
#define ADIN1320_GE_WOL_PUL_LENM_1_MASK   NO_OS_GENMASK(11, 8)
 
#define ADIN1320_GE_WOL_PUL_EN_MASK   NO_OS_BIT(0)
 
#define ADIN1320_GE_WOL_STA_0_AD_01   NO_OS_MDIO_C45_ADDR(0x1e, 0xff7c)
 
#define ADIN1320_GE_WOL_STA_0_AD_1_MASK   NO_OS_GENMASK(15, 8)
 
#define ADIN1320_GE_WOL_STA_0_AD_0_MASK   NO_OS_GENMASK(7, 0)
 
#define ADIN1320_GE_WOL_STA_0_AD_23   NO_OS_MDIO_C45_ADDR(0x1e, 0xff7d)
 
#define ADIN1320_GE_WOL_STA_0_AD_3_MASK   NO_OS_GENMASK(15, 8)
 
#define ADIN1320_GE_WOL_STA_0_AD_2_MASK   NO_OS_GENMASK(7, 0)
 
#define ADIN1320_GE_WOL_STA_0_AD_45   NO_OS_MDIO_C45_ADDR(0x1e, 0xff7e)
 
#define ADIN1320_GE_WOL_STA_0_AD_5_MASK   NO_OS_GENMASK(15, 8)
 
#define ADIN1320_GE_WOL_STA_0_AD_4_MASK   NO_OS_GENMASK(7, 0)
 
#define ADIN1320_GE_MGC_0_CNTRL   NO_OS_MDIO_C45_ADDR(0x1e, 0xff80)
 
#define ADIN1320_GE_MGC_0_KEY_4BY_EN_MASK   NO_OS_BIT(8)
 
#define ADIN1320_GE_MGC_0_KEY_CHK_EN_MASK   NO_OS_BIT(7)
 
#define ADIN1320_GE_MGC_0_LEN_CHK_EN_MASK   NO_OS_BIT(6)
 
#define ADIN1320_GE_MGC_0_CRC_CHK_EN_MASK   NO_OS_BIT(5)
 
#define ADIN1320_GE_MGC_0_DA_BC_AD_EN_MASK   NO_OS_BIT(4)
 
#define ADIN1320_GE_MGC_0_DA_MC_AD_EN_MASK   NO_OS_BIT(3)
 
#define ADIN1320_GE_MGC_0_DA_UC_AD_EN_MASK   NO_OS_BIT(2)
 
#define ADIN1320_GE_MGC_0_DA_STA_0_AD_EN_MASK   NO_OS_BIT(1)
 
#define ADIN1320_GE_MGC_0_EN_MASK   NO_OS_BIT(0)
 
#define ADIN1320_GE_MGC_0_KEY_01   NO_OS_MDIO_C45_ADDR(0x1e, 0xff81)
 
#define ADIN1320_GE_MGC_0_KEY_1_MASK   NO_OS_GENMASK(15, 8)
 
#define ADIN1320_GE_MGC_0_KEY_0_MASK   NO_OS_GENMASK(7, 0)
 
#define ADIN1320_GE_MGC_0_KEY_23   NO_OS_MDIO_C45_ADDR(0x1e, 0xff82)
 
#define ADIN1320_GE_MGC_0_KEY_3_MASK   NO_OS_GENMASK(15, 8)
 
#define ADIN1320_GE_MGC_0_KEY_2_MASK   NO_OS_GENMASK(7, 0)
 
#define ADIN1320_GE_MGC_0_KEY_45   NO_OS_MDIO_C45_ADDR(0x1e, 0xff83)
 
#define ADIN1320_GE_MGC_0_KEY_5_MASK   NO_OS_GENMASK(15, 8)
 
#define ADIN1320_GE_MGC_0_KEY_4_MASK   NO_OS_GENMASK(7, 0)
 
#define ADIN1320_GE_WOL_STAT   NO_OS_MDIO_C45_ADDR(0x1e, 0xff85)
 
#define ADIN1320_GE_MGC_0_KEY_ERR_MASK   NO_OS_BIT(2)
 
#define ADIN1320_GE_MGC_0_FRM_MATCH_MASK   NO_OS_BIT(1)
 
#define ADIN1320_GE_WOL_LS_CHG_MASK   NO_OS_BIT(0)
 
#define ADIN1320_LED_EXT_CFG_EN_VAL   NO_OS_BIT(4)
 
#define ADIN1320_LED_CFG_VAL   NO_OS_GENMASK(3, 0)
 
#define ADIN1320_DOWNSPEED_CFG_MAX   0x04
 
#define ADIN1320_SET_DOWNSPEED_RETRIES_MAX   0x08
 
#define ADIN1320_CU_LED_CTRL_LED_PAUSE_MAX   0x10
 
#define ADIN1320_WOL_SIG_CFG_PUL_LEN_MAX   0x10
 
#define ADIN1320_MII_STATUS_STRUCT_INIT   {0, 0, 0, 0, 0}
 
#define ADIN1320_STATION_ADDRESS_MAX_BYTE   6
 
#define ADIN1320_BITMASK_RESET   0x0000
 
#define ADIN1320_DISABLE   0
 
#define ADIN1320_ENABLE   1
 
#define ADIN1320_DEVICE_ID1_HIGH_BIT   31
 
#define ADIN1320_DEVICE_ID1_LOW_BIT   16
 
#define ADIN1320_DEVICE_ID2_HIGH_BIT   15
 
#define ADIN1320_DEVICE_ID2_LOW_BIT   0
 
#define ADIN1320_PHY_ID   0x6
 

Enumerations

enum  adin1320_gp_clk_source {
  ADIN1320_GP_CLK_MIN = -1 ,
  ADIN1320_GP_CLK_REFERENCE ,
  ADIN1320_GP_CLK_HEARTBEAT_FREE ,
  ADIN1320_GP_CLK_HEARTBEAT_RECOVERED ,
  ADIN1320_GP_CLK_FREE = 4 ,
  ADIN1320_GP_CLK_RECOVERED ,
  ADIN1320_GP_CLK_TX_HEARTBEAT = 7 ,
  ADIN1320_GP_CLK_RX_HEARTBEAT ,
  ADIN1320_GP_CLK_TX_FREE ,
  ADIN1320_GP_CLK_RX_RECOVERED ,
  ADIN1320_GP_CLK_DISABLE ,
  ADIN1320_GP_CLK_MAX
}
 
enum  adin1320_clk25_ref_enable {
  ADIN1320_CLK25_REF_DISABLE ,
  ADIN1320_CLK25_REF_ENABLE
}
 
enum  adin1320_rgmii_idelay_enable {
  ADIN1320_RGMII_IDELAY_DISABLE = 0 ,
  ADIN1320_RGMII_IDELAY_ENABLE
}
 
enum  adin1320_rgmii_idelay {
  ADIN1320_RGMII_2_00_NS ,
  ADIN1320_RGMII_1_60_NS ,
  ADIN1320_RGMII_1_80_NS ,
  ADIN1320_RGMII_2_20_NS = 6 ,
  ADIN1320_RGMII_2_40_NS
}
 
enum  adin1320_soft_reset_option {
  ADIN1320_RESET_GE_SUBSYS = 0 ,
  ADIN1320_RESET_GE_SUBSYS_PIN
}
 
enum  adin1320_software_powerdown {
  ADIN1320_SOFTWARE_POWERUP = 0 ,
  ADIN1320_SOFTWARE_POWERDOWN
}
 
enum  adin1320_mac_interface {
  ADIN1320_RGMII_MAC_INTERFACE = 0 ,
  ADIN1320_RMII_MAC_INTERFACE ,
  ADIN1320_MII_MAC_INTERFACE ,
  ADIN1320_SGMII_MAC_INTERFACE
}
 
enum  adin1320_autoneg_enable {
  ADIN1320_AUTONEG_DISABLE = 0 ,
  ADIN1320_AUTONEG_ENABLE
}
 
enum  adin1320_link_stat {
  ADIN1320_LINK_STAT_MIN = -1 ,
  ADIN1320_LINK_STAT_NO_CHECK ,
  ADIN1320_LINK_STAT_LINKDOWN ,
  ADIN1320_LINK_STAT_LINKUP ,
  ADIN1320_LINK_STAT_MAX
}
 
enum  adin1320_autoneg_stat {
  ADIN1320_AUTONEG_STAT_MIN = -1 ,
  ADIN1320_AUTONEG_STAT_NO_CHECK ,
  ADIN1320_AUTONEG_STAT_NOT_DONE ,
  ADIN1320_AUTONEG_STAT_DONE ,
  ADIN1320_AUTONEG_STAT_MAX
}
 
enum  adin1320_lat_jabber_det {
  ADIN1320_LAT_JABBER_DET_MIN = -1 ,
  ADIN1320_LAT_JABBER_DET_NO_CHECK ,
  ADIN1320_LAT_JABBER_DET_NONE_DETECTED ,
  ADIN1320_LAT_JABBER_DET_DETECTED ,
  ADIN1320_LAT_JABBER_DET_MAX
}
 
enum  adin1320_lat_link_stat {
  ADIN1320_LAT_LINK_STAT_MIN = -1 ,
  ADIN1320_LAT_LINK_STAT_NO_CHECK ,
  ADIN1320_LAT_LINK_STAT_NO_LINK_DROP ,
  ADIN1320_LAT_LINK_STAT_LINK_DROPPED ,
  ADIN1320_LAT_LINK_STAT_MAX
}
 
enum  adin1320_lat_rem_flt {
  ADIN1320_LAT_REM_FLT_MIN = -1 ,
  ADIN1320_LAT_REM_FLT_NO_CHECK ,
  ADIN1320_LAT_REM_FLT_NONE_DETECTED ,
  ADIN1320_LAT_REM_FLT_DETECTED ,
  ADIN1320_LAT_REM_FLT_MAX
}
 
enum  adin1320_link_cfg_enable {
  ADIN1320_LINK_CFG_DISABLE = ADIN1320_DISABLE ,
  ADIN1320_LINK_CFG_ENABLE = ADIN1320_ENABLE
}
 
enum  adin1320_cu_speed {
  ADIN1320_CU_SPEED_10BASE_T_HD = NO_OS_BIT(0) ,
  ADIN1320_CU_SPEED_10BASE_T_FD = NO_OS_BIT(1) ,
  ADIN1320_CU_SPEED_100BASE_TX_HD = NO_OS_BIT(2) ,
  ADIN1320_CU_SPEED_100BASE_TX_FD = NO_OS_BIT(3) ,
  ADIN1320_CU_SPEED_1000BASE_T_HD = NO_OS_BIT(4) ,
  ADIN1320_CU_SPEED_1000BASE_T_FD = NO_OS_BIT(5) ,
  ADIN1320_CU_SPEED_MAX = NO_OS_BIT(6)
}
 
enum  adin1320_sd_speed {
  ADIN1320_SD_SPEED_NO_BASE_X = NO_OS_BIT(0) ,
  ADIN1320_SD_SPEED_100BASE_FX_HD = NO_OS_BIT(2) ,
  ADIN1320_SD_SPEED_100BASE_FX_FD = NO_OS_BIT(3) ,
  ADIN1320_SD_SPEED_1000BASE_KX = NO_OS_BIT(4) ,
  ADIN1320_SD_SPEED_1000BASE_X_FD = NO_OS_BIT(5) ,
  ADIN1320_SD_SPEED_1000BASE_X_HD = NO_OS_BIT(6) ,
  ADIN1320_SD_SPEED_1000BASE_X_HDFD = NO_OS_BIT(7)
}
 
enum  adin1320_auto_mdix {
  ADIN1320_MANUAL_MDI = 0 ,
  ADIN1320_MANUAL_MDIX ,
  ADIN1320_AUTO_MDIX_PREFER_MDIX ,
  ADIN1320_AUTO_MDIX_PREFER_MDI
}
 
enum  adin1320_energy_detect_pwd {
  ADIN1320_NRG_PD_DIS = 0 ,
  ADIN1320_NRG_PD_EN ,
  ADIN1320_NRG_PD_TX_EN ,
  ADIN1320_NRG_PD_TX_DIS
}
 
enum  adin1320_edpd_stat {
  ADIN1320_NOT_IN_NRG_PD_MODE = 0 ,
  ADIN1320_IN_NRG_PD_MODE
}
 
enum  adin1320_downspeed {
  ADIN1320_DOWNSPEED_TO_10 = NO_OS_BIT(0) ,
  ADIN1320_DOWNSPEED_TO_100 = NO_OS_BIT(1)
}
 
enum  adin1320_eee_speeds {
  ADIN1320_EEE_100_ADV = NO_OS_BIT(0) ,
  ADIN1320_EEE_1000_ADV = NO_OS_BIT(1) ,
  ADIN1320_EEE_1000_KX_ADV = NO_OS_BIT(2) ,
  ADIN1320_EEE_MAX = NO_OS_BIT(3)
}
 
enum  adin1320_master_slave_status {
  ADIN1320_RESOLVED_TO_SLAVE = 0 ,
  ADIN1320_RESOLVED_TO_MASTER ,
  ADIN1320_MAST_SLAVE_FAULT_DETECT
}
 
enum  adin1320_adv_master_slave_cfg {
  ADIN1320_MAN_ADV_MASTER = 0 ,
  ADIN1320_MAN_ADV_SLAVE ,
  ADIN1320_MAN_MSTR_SLV_DIS
}
 
enum  adin1320_wol_enable {
  ADIN1320_WOL_DISABLE = ADIN1320_DISABLE ,
  ADIN1320_WOL_ENABLE = ADIN1320_ENABLE
}
 
enum  adin1320_wol_fi_en {
  ADIN1320_WOL_FI_DIS = ADIN1320_DISABLE ,
  ADIN1320_WOL_FI_EN = ADIN1320_ENABLE
}
 
enum  adin1320_wol_inv {
  ADIN1320_WOL_INV_ACTIVE_HIGH = 0 ,
  ADIN1320_WOL_INV_ACTIVE_LOW
}
 
enum  adin1320_wol_sig {
  ADIN1320_WOL_SIG_LEVEL = 0 ,
  ADIN1320_WOL_SIG_PULSE
}
 
enum  adin1320_wol_wake_key_enable {
  ADIN1320_WOL_WAKE_KEY_DISABLE = ADIN1320_DISABLE ,
  ADIN1320_WOL_WAKE_KEY_ENABLE = ADIN1320_ENABLE
}
 
enum  adin1320_wol_wake_link_enable {
  ADIN1320_WOL_WAKE_LINK_DISABLE = ADIN1320_DISABLE ,
  ADIN1320_WOL_WAKE_LINK_ENABLE = ADIN1320_ENABLE
}
 
enum  adin1320_mgc_chk_en {
  ADIN1320_MGC_CHK_EN_CRC = NO_OS_BIT(0) ,
  ADIN1320_MGC_CHK_EN_LEN = NO_OS_BIT(1) ,
  ADIN1320_MGC_CHK_EN_KEY = NO_OS_BIT(2) ,
  ADIN1320_MGC_CHK_EN_MAX = NO_OS_BIT(3)
}
 
enum  adin1320_mgc_match_en {
  ADIN1320_MGC_MATCH_EN_ST = NO_OS_BIT(0) ,
  ADIN1320_MGC_MATCH_EN_UC = NO_OS_BIT(1) ,
  ADIN1320_MGC_MATCH_EN_MC = NO_OS_BIT(2) ,
  ADIN1320_MGC_MATCH_EN_BC = NO_OS_BIT(3) ,
  ADIN1320_MGC_MATCH_EN_MAX = NO_OS_BIT(4)
}
 
enum  adin1320_mgc_key_byte {
  ADIN1320_MGC_KEY_BYTE_6 = 0 ,
  ADIN1320_MGC_KEY_BYTE_4
}
 
enum  adin1320_led_output_enable {
  ADIN1320_LED_OUTPUT_DISABLE = ADIN1320_DISABLE ,
  ADIN1320_LED_OUTPUT_ENABLE = ADIN1320_ENABLE
}
 
enum  adin1320_led_pul_str_dur_select {
  ADIN1320_LED_PUL_STR_DUR_SELECT_MIN = -1 ,
  ADIN1320_LED_PUL_STR_DUR_SELECT_32 ,
  ADIN1320_LED_PUL_STR_DUR_SELECT_64 ,
  ADIN1320_LED_PUL_STR_DUR_SELECT_102 ,
  ADIN1320_LED_PUL_STR_DUR_SELECT_PROG ,
  ADIN1320_LED_PUL_STR_DISABLE ,
  ADIN1320_LED_PUL_STR_DUR_SELECT_MAX
}
 
enum  adin1320_led_sel {
  ADIN1320_LED_SEL_MIN = -1 ,
  ADIN1320_LED_SEL_0 ,
  ADIN1320_LED_SEL_1 ,
  ADIN1320_LED_SEL_2 ,
  ADIN1320_LED_SEL_3 ,
  ADIN1320_LED_SEL_MAX
}
 
enum  adin1320_cu_led_cfg {
  ADIN1320_CU_LED_CFG_MIN = -1 ,
  ADIN1320_CU_LED_CFG_ON_1000 ,
  ADIN1320_CU_LED_CFG_ON_100 ,
  ADIN1320_CU_LED_CFG_ON_10 ,
  ADIN1320_CU_LED_CFG_ON_1000_BLNK_100 ,
  ADIN1320_CU_LED_CFG_ON_LINK ,
  ADIN1320_CU_LED_CFG_ON_TX ,
  ADIN1320_CU_LED_CFG_ON_RX ,
  ADIN1320_CU_LED_CFG_ON_TX_RX ,
  ADIN1320_CU_LED_CFG_ON_LINK_FD ,
  ADIN1320_CU_LED_CFG_ON_COL ,
  ADIN1320_CU_LED_CFG_ON_LINK_BLNK_TX_RX ,
  ADIN1320_CU_LED_CFG_ON_LINK_BLNK_RX ,
  ADIN1320_CU_LED_CFG_ON_LINK_FD_BLNK_COL ,
  ADIN1320_CU_LED_CFG_BLNK ,
  ADIN1320_CU_LED_CFG_ON ,
  ADIN1320_CU_LED_CFG_OFF ,
  ADIN1320_CU_LED_CFG_ON_10_100 ,
  ADIN1320_CU_LED_CFG_ON_100_1000 ,
  ADIN1320_CU_LED_CFG_ON_10_BLNK_TX_RX ,
  ADIN1320_CU_LED_CFG_ON_100_BLNK_TX_RX ,
  ADIN1320_CU_LED_CFG_ON_1000_BLNK_TX_RX ,
  ADIN1320_CU_LED_CFG_ON_10_100_BLNK_TX_RX ,
  ADIN1320_CU_LED_CFG_ON_100_1000_BLNK_TX_RX ,
  ADIN1320_CU_LED_CFG_ON_10_1000 ,
  ADIN1320_CU_LED_CFG_ON_10_1000_BLNK_TX_RX ,
  ADIN1320_CU_LED_CFG_BLNK_TX_RX ,
  ADIN1320_CU_LED_CFG_BLNK_TX ,
  ADIN1320_CU_LED_CFG_ON_1000_BLNK_10 ,
  ADIN1320_CU_LED_CFG_ON_100_BLNK_1000 ,
  ADIN1320_CU_LED_CFG_ON_100_BLNK_10 ,
  ADIN1320_CU_LED_CFG_ON_10_BLNK_1000 ,
  ADIN1320_CU_LED_CFG_ON_10_BLNK_100 ,
  ADIN1320_CU_LED_CFG_MAX
}
 
enum  adin1320_sd_led_cfg {
  ADIN1320_SD_LED_CFG_MIN = -1 ,
  ADIN1320_SD_LED_CFG_ON_1000 ,
  ADIN1320_SD_LED_CFG_ON_100 ,
  ADIN1320_SD_LED_CFG_LINK ,
  ADIN1320_SD_LED_CFG_BLNK_TX ,
  ADIN1320_SD_LED_CFG_BLNK_RX ,
  ADIN1320_SD_LED_CFG_BLNK_TX_RX ,
  ADIN1320_SD_LED_CFG_LINK_BLNK_TX ,
  ADIN1320_SD_LED_CFG_LINK_BLNK_RX ,
  ADIN1320_SD_LED_CFG_LINK_BLNK_TX_RX ,
  ADIN1320_SD_LED_CFG_BLNK ,
  ADIN1320_SD_LED_CFG_ON ,
  ADIN1320_SD_LED_CFG_OFF ,
  ADIN1320_SD_LED_CFG_MAX
}
 
enum  adin1320_led_inv_state {
  ADIN1320_LED_INV_STATE_ACTIVE_HIGH = 0 ,
  ADIN1320_LED_INV_STATE_ACTIVE_LOW
}
 
enum  adin1320_active_media {
  ADIN1320_ACTIVE_MEDIA_NULL = 0 ,
  ADIN1320_ACTIVE_MEDIA_CU ,
  ADIN1320_ACTIVE_MEDIA_SD
}
 

Functions

int adin1320_init (struct adin1320_desc **dev, struct adin1320_init_param *param)
 Initialize the Device.
 
int adin1320_hard_reset (struct adin1320_desc *dev)
 Perform Device Hard Reset.
 
int adin1320_remove (struct adin1320_desc *dev)
 Remove Initialization of the Device.
 
int adin1320_write (struct adin1320_desc *dev, uint32_t addr, uint16_t val)
 MDIO Write with Clause22 or Clause45.
 
int adin1320_read (struct adin1320_desc *dev, uint32_t addr, uint16_t *val)
 MDIO Read with Clause22 or Clause45.
 
int adin1320_write_bits (struct adin1320_desc *dev, uint32_t addr, uint16_t val, uint16_t bitmask)
 MDIO Write with Clause22 or Clause45 on a Specific Bit.
 
int adin1320_config_rgmii (struct adin1320_desc *dev, struct adin1320_rgmii_config rgmii)
 Configure RGMII Tx and Rx Delays.
 
int adin1320_config_gp_clk (struct adin1320_desc *dev, enum adin1320_gp_clk_source source)
 Configure GP Clock.
 
int adin1320_config_clk25_ref (struct adin1320_desc *dev, enum adin1320_clk25_ref_enable enable)
 Enable/disable GE Clock 25MHz Reference.
 
int adin1320_cu_autoneg (struct adin1320_desc *dev, enum adin1320_autoneg_enable enable)
 Enable/disable and Reset Autonegotiation for Copper Media.
 
int adin1320_sd_autoneg (struct adin1320_desc *dev, enum adin1320_autoneg_enable enable)
 Enable/disable and Reset Autonegotiation for SerDes Media.
 
int adin1320_cu_resolved_speed (struct adin1320_desc *dev, enum adin1320_cu_speed *resolved_speed)
 Get Resolved Speed for Copper Media.
 
int adin1320_sd_resolved_speed (struct adin1320_desc *dev, enum adin1320_sd_speed *resolved_speed)
 Get Resolved Speed for SerDes Media.
 
int adin1320_soft_reset (struct adin1320_desc *dev, enum adin1320_soft_reset_option reset_cfg)
 Select and Perform Device Reset.
 
int adin1320_cu_read_irq_status (struct adin1320_desc *dev, bool *val_irq_pending, uint16_t *val_irq_status)
 Read interrupt status for copper media.
 
int adin1320_sd_read_irq_status (struct adin1320_desc *dev, bool *val_irq_pending, uint16_t *val_irq_status)
 Read interrupt status for serdes media.
 
int adin1320_set_software_powerdown (struct adin1320_desc *dev, enum adin1320_software_powerdown val)
 Enter/exit Software Powerdown.
 
int adin1320_get_software_powerdown (struct adin1320_desc *dev, enum adin1320_software_powerdown *val)
 Get Software Powerdown Status.
 
int adin1320_get_device_id (struct adin1320_desc *dev, uint32_t *device_id)
 Get Device ID.
 
int adin1320_reset_rmii_fifo (struct adin1320_desc *dev)
 Allows the RMII FIFO to be Reset.
 
int adin1320_select_mac_interface (struct adin1320_desc *dev, enum adin1320_mac_interface val)
 MAC Interface Configuration.
 
int adin1320_cu_link_cfg (struct adin1320_desc *dev, enum adin1320_link_cfg_enable val)
 Enables/Disables the Link.
 
int adin1320_cu_get_mii_status (struct adin1320_desc *dev, struct adin1320_mii_status *mii_status)
 Get Different Status from Copper Media MII Status Register.
 
int adin1320_sd_get_mii_status (struct adin1320_desc *dev, struct adin1320_mii_status *mii_status)
 Get Different Status from SerDes Media MII Status Register.
 
int adin1320_cu_autoneg_adv_cfg (struct adin1320_desc *dev, uint16_t autoneg_adv_speeds)
 Configure Autonegotiation Advertisement Speeds for Copper Media.
 
int adin1320_sd_autoneg_adv_cfg (struct adin1320_desc *dev, uint16_t autoneg_adv_speeds)
 Configure Autonegotiation Advertisement Speeds for SerDes Media.
 
int adin1320_cu_get_autoneg_adv (struct adin1320_desc *dev, uint16_t *autoneg_adv_speeds)
 Get Enabled Autonegotiation Advertised Speeds for Copper Media.
 
int adin1320_sd_get_autoneg_adv (struct adin1320_desc *dev, uint16_t *autoneg_adv_speeds)
 Get Enabled Autonegotiation Advertised Speeds for SerDes Media.
 
int adin1320_auto_mdix_cfg (struct adin1320_desc *dev, enum adin1320_auto_mdix val)
 Auto MDIX Config.
 
int adin1320_energy_detect_pwd_cfg (struct adin1320_desc *dev, enum adin1320_energy_detect_pwd val)
 Energy Detect Power Down mode Config.
 
int adin1320_get_energy_detect_pwd_stat (struct adin1320_desc *dev, enum adin1320_edpd_stat *val)
 Get Energy Detect Power Down mode Status.
 
int adin1320_downspeed_cfg (struct adin1320_desc *dev, uint8_t downspeeds)
 Configure Downspeed.
 
int adin1320_set_downspeed_retries (struct adin1320_desc *dev, uint16_t val)
 Downspeed - Number of retries.
 
int adin1320_cu_forced_speed (struct adin1320_desc *dev, enum adin1320_cu_speed val)
 Set Force Speed for Copper Media.
 
int adin1320_sd_forced_speed (struct adin1320_desc *dev, enum adin1320_sd_speed forced_speed)
 Set Force Speed for SerDes Media.
 
int adin1320_set_eee (struct adin1320_desc *dev, uint8_t eee_speeds)
 Set Energy Efficient Ethernet speeds.
 
int adin1320_get_eee (struct adin1320_desc *dev, uint8_t *eee_speeds)
 Get Energy Efficient Ethernet Status.
 
int adin1320_get_master_slave_status (struct adin1320_desc *dev, enum adin1320_master_slave_status *val)
 Get Master Slave Status.
 
int adin1320_master_slave_config (struct adin1320_desc *dev, enum adin1320_adv_master_slave_cfg val)
 Configure PHY as Master or Slave for 1 Gb speed only.
 
int adin1320_cu_config_interrupt (struct adin1320_desc *dev, uint32_t callback_events)
 Configure the interrupt mask register for copper media.
 
int adin1320_sd_config_interrupt (struct adin1320_desc *dev, uint32_t callback_events)
 Configure the interrupt mask register for serdes media.
 
int adin1320_led_cfg (struct adin1320_desc *dev, enum adin1320_led_output_enable enable_led_output, enum adin1320_led_pul_str_dur_select pulse_stretch)
 Configure general LED settings.
 
int adin1320_cu_led_ctrl (struct adin1320_desc *dev, enum adin1320_led_sel led_sel, uint8_t led_pat, uint8_t led_pause, enum adin1320_cu_led_cfg led_cfg, enum adin1320_led_inv_state led_inv_state)
 Configure LED settings for Copper Media.
 
int adin1320_sd_led_ctrl (struct adin1320_desc *dev, enum adin1320_led_sel led_sel, enum adin1320_sd_led_cfg led_cfg, enum adin1320_led_inv_state led_inv_state)
 Configure LED settings for SerDes Media.
 
int adin1320_mgc_match_cfg (struct adin1320_desc *dev, uint16_t enabled_matches)
 Configure Magic Packet Address Matchings.
 
int adin1320_mgc_check_cfg (struct adin1320_desc *dev, uint16_t enabled_checks)
 Configure Magic Packet Checks.
 
int adin1320_mgc_key_cfg (struct adin1320_desc *dev, enum adin1320_mgc_key_byte key_byte, uint8_t key[6])
 Configure Magic Packet SecureOn Key.
 
int adin1320_wol_address (struct adin1320_desc *dev, uint8_t mac_address[6])
 Configure Wake-on-LAN Station Address.
 
int adin1320_wol_sys_cfg (struct adin1320_desc *dev, enum adin1320_wol_fi_en enable_fi, enum adin1320_wol_inv active_signal)
 Configure Wake-on-LAN System Settings.
 
int adin1320_wol_sig_cfg (struct adin1320_desc *dev, enum adin1320_wol_sig signal_type, uint8_t pulse_length)
 Configure Wake-on-LAN Signal Settings.
 
int adin1320_wol_wake_cfg (struct adin1320_desc *dev, enum adin1320_wol_wake_key_enable wake_on_key, enum adin1320_wol_wake_link_enable wake_on_link_change)
 Configure Wake-on-LAN Wake-up Events.
 
int adin1320_wol_en_cfg (struct adin1320_desc *dev, enum adin1320_wol_enable enable)
 Enable/Disable Wake-on-LAN.
 
int adin1320_get_active_media (struct adin1320_desc *dev, enum adin1320_active_media *media)
 Get Auto Media Selected as Active Media.
 

Detailed Description

Header file of the ADIN1320 driver.

Author
Johnson Ralph Perez (Johns.nosp@m.onra.nosp@m.lph.P.nosp@m.erez.nosp@m.@anal.nosp@m.og.c.nosp@m.om)

Copyright 2026(c) Analog Devices, Inc.

SPDX-License-Identifier: BSD-3-Clause

Macro Definition Documentation

◆ ADIN1320_AN_STAT_CHNG_IRQ_EN_MASK

#define ADIN1320_AN_STAT_CHNG_IRQ_EN_MASK   NO_OS_BIT(8)

◆ ADIN1320_AN_STAT_CHNG_IRQ_STAT_MASK

#define ADIN1320_AN_STAT_CHNG_IRQ_STAT_MASK   NO_OS_BIT(8)

◆ ADIN1320_AUTO_MDI_EN_MASK

#define ADIN1320_AUTO_MDI_EN_MASK   NO_OS_BIT(10)

◆ ADIN1320_AUTONEG_ADV

#define ADIN1320_AUTONEG_ADV   0x0004

◆ ADIN1320_AUTONEG_DONE_MASK

#define ADIN1320_AUTONEG_DONE_MASK   NO_OS_BIT(5)

◆ ADIN1320_AUTONEG_EN_MASK

#define ADIN1320_AUTONEG_EN_MASK   NO_OS_BIT(12)

◆ ADIN1320_AUTONEG_EXP

#define ADIN1320_AUTONEG_EXP   0x0006

◆ ADIN1320_BITMASK_RESET

#define ADIN1320_BITMASK_RESET   0x0000

◆ ADIN1320_CBL_DIAG_IRQ_EN_MASK

#define ADIN1320_CBL_DIAG_IRQ_EN_MASK   NO_OS_BIT(10)

◆ ADIN1320_CBL_DIAG_IRQ_STAT_MASK

#define ADIN1320_CBL_DIAG_IRQ_STAT_MASK   NO_OS_BIT(10)

◆ ADIN1320_CLK_CNTRL_MASK

#define ADIN1320_CLK_CNTRL_MASK   NO_OS_GENMASK(3, 1)

◆ ADIN1320_CU_LED_CTRL_LED_PAUSE_MAX

#define ADIN1320_CU_LED_CTRL_LED_PAUSE_MAX   0x10

◆ ADIN1320_DEVICE_ID1_HIGH_BIT

#define ADIN1320_DEVICE_ID1_HIGH_BIT   31

Device ID field positions for combining PHY_ID_1 and PHY_ID_2 into 32-bit ID

◆ ADIN1320_DEVICE_ID1_LOW_BIT

#define ADIN1320_DEVICE_ID1_LOW_BIT   16

◆ ADIN1320_DEVICE_ID2_HIGH_BIT

#define ADIN1320_DEVICE_ID2_HIGH_BIT   15

◆ ADIN1320_DEVICE_ID2_LOW_BIT

#define ADIN1320_DEVICE_ID2_LOW_BIT   0

◆ ADIN1320_DIAG_CLK_EN_MASK

#define ADIN1320_DIAG_CLK_EN_MASK   NO_OS_BIT(2)

◆ ADIN1320_DISABLE

#define ADIN1320_DISABLE   0

◆ ADIN1320_DN_SPEED_TO_100_EN_MASK

#define ADIN1320_DN_SPEED_TO_100_EN_MASK   NO_OS_BIT(11)

◆ ADIN1320_DN_SPEED_TO_10_EN_MASK

#define ADIN1320_DN_SPEED_TO_10_EN_MASK   NO_OS_BIT(10)

◆ ADIN1320_DOWNSPEED_CFG_MAX

#define ADIN1320_DOWNSPEED_CFG_MAX   0x04

Bitrange Max Values

◆ ADIN1320_DPLX_MODE_MASK

#define ADIN1320_DPLX_MODE_MASK   NO_OS_BIT(8)

◆ ADIN1320_EEE_1000_ADV_MASK

#define ADIN1320_EEE_1000_ADV_MASK   NO_OS_BIT(2)

◆ ADIN1320_EEE_1000_KX_ADV_MASK

#define ADIN1320_EEE_1000_KX_ADV_MASK   NO_OS_BIT(4)

◆ ADIN1320_EEE_100_ADV_MASK

#define ADIN1320_EEE_100_ADV_MASK   NO_OS_BIT(1)

◆ ADIN1320_EEE_ADV

#define ADIN1320_EEE_ADV   NO_OS_MDIO_C45_ADDR(0x1e, 0x8001)

◆ ADIN1320_ENABLE

#define ADIN1320_ENABLE   1

◆ ADIN1320_EXT_REG_DATA

#define ADIN1320_EXT_REG_DATA   0x0011

◆ ADIN1320_EXT_REG_PTR

#define ADIN1320_EXT_REG_PTR   0x0010

◆ ADIN1320_EXT_STATUS

#define ADIN1320_EXT_STATUS   0x000f

◆ ADIN1320_FC_FG_IRQ_EN_MASK

#define ADIN1320_FC_FG_IRQ_EN_MASK   NO_OS_BIT(7)

◆ ADIN1320_FC_FG_IRQ_STAT_MASK

#define ADIN1320_FC_FG_IRQ_STAT_MASK   NO_OS_BIT(7)

◆ ADIN1320_FD_1000_ADV_MASK

#define ADIN1320_FD_1000_ADV_MASK   NO_OS_BIT(9)

◆ ADIN1320_FD_100_ADV_MASK

#define ADIN1320_FD_100_ADV_MASK   NO_OS_BIT(8)

◆ ADIN1320_FD_10_ADV_MASK

#define ADIN1320_FD_10_ADV_MASK   NO_OS_BIT(6)

◆ ADIN1320_FIFO_OU_IRQ_EN_MASK

#define ADIN1320_FIFO_OU_IRQ_EN_MASK   NO_OS_BIT(4)

◆ ADIN1320_FIFO_OU_IRQ_STAT_MASK

#define ADIN1320_FIFO_OU_IRQ_STAT_MASK   NO_OS_BIT(4)

◆ ADIN1320_GE_B10_REGEN_PRE

#define ADIN1320_GE_B10_REGEN_PRE   NO_OS_MDIO_C45_ADDR(0x1e, 0xff38)

◆ ADIN1320_GE_B10_REGEN_PRE_MASK

#define ADIN1320_GE_B10_REGEN_PRE_MASK   NO_OS_BIT(0)

◆ ADIN1320_GE_CLK_25_EN_MASK

#define ADIN1320_GE_CLK_25_EN_MASK   NO_OS_BIT(0)

◆ ADIN1320_GE_CLK_CFG

#define ADIN1320_GE_CLK_CFG   NO_OS_MDIO_C45_ADDR(0x1e, 0xff1f)

◆ ADIN1320_GE_CLK_FREE_125_EN_MASK

#define ADIN1320_GE_CLK_FREE_125_EN_MASK   NO_OS_BIT(4)

◆ ADIN1320_GE_CLK_HRT_FREE_EN_MASK

#define ADIN1320_GE_CLK_HRT_FREE_EN_MASK   NO_OS_BIT(1)

◆ ADIN1320_GE_CLK_HRT_RCVR_EN_MASK

#define ADIN1320_GE_CLK_HRT_RCVR_EN_MASK   NO_OS_BIT(2)

◆ ADIN1320_GE_CLK_RCVR_125_EN_MASK

#define ADIN1320_GE_CLK_RCVR_125_EN_MASK   NO_OS_BIT(5)

◆ ADIN1320_GE_IRQ_EN

#define ADIN1320_GE_IRQ_EN   NO_OS_MDIO_C45_ADDR(0x1e, 0xff1d)

◆ ADIN1320_GE_IRQ_LAT

#define ADIN1320_GE_IRQ_LAT   NO_OS_MDIO_C45_ADDR(0x1e, 0xff1e)

◆ ADIN1320_GE_MGC_0_CNTRL

#define ADIN1320_GE_MGC_0_CNTRL   NO_OS_MDIO_C45_ADDR(0x1e, 0xff80)

◆ ADIN1320_GE_MGC_0_CRC_CHK_EN_MASK

#define ADIN1320_GE_MGC_0_CRC_CHK_EN_MASK   NO_OS_BIT(5)

◆ ADIN1320_GE_MGC_0_DA_BC_AD_EN_MASK

#define ADIN1320_GE_MGC_0_DA_BC_AD_EN_MASK   NO_OS_BIT(4)

◆ ADIN1320_GE_MGC_0_DA_MC_AD_EN_MASK

#define ADIN1320_GE_MGC_0_DA_MC_AD_EN_MASK   NO_OS_BIT(3)

◆ ADIN1320_GE_MGC_0_DA_STA_0_AD_EN_MASK

#define ADIN1320_GE_MGC_0_DA_STA_0_AD_EN_MASK   NO_OS_BIT(1)

◆ ADIN1320_GE_MGC_0_DA_UC_AD_EN_MASK

#define ADIN1320_GE_MGC_0_DA_UC_AD_EN_MASK   NO_OS_BIT(2)

◆ ADIN1320_GE_MGC_0_EN_MASK

#define ADIN1320_GE_MGC_0_EN_MASK   NO_OS_BIT(0)

◆ ADIN1320_GE_MGC_0_FRM_MATCH_MASK

#define ADIN1320_GE_MGC_0_FRM_MATCH_MASK   NO_OS_BIT(1)

◆ ADIN1320_GE_MGC_0_KEY_01

#define ADIN1320_GE_MGC_0_KEY_01   NO_OS_MDIO_C45_ADDR(0x1e, 0xff81)

◆ ADIN1320_GE_MGC_0_KEY_0_MASK

#define ADIN1320_GE_MGC_0_KEY_0_MASK   NO_OS_GENMASK(7, 0)

◆ ADIN1320_GE_MGC_0_KEY_1_MASK

#define ADIN1320_GE_MGC_0_KEY_1_MASK   NO_OS_GENMASK(15, 8)

◆ ADIN1320_GE_MGC_0_KEY_23

#define ADIN1320_GE_MGC_0_KEY_23   NO_OS_MDIO_C45_ADDR(0x1e, 0xff82)

◆ ADIN1320_GE_MGC_0_KEY_2_MASK

#define ADIN1320_GE_MGC_0_KEY_2_MASK   NO_OS_GENMASK(7, 0)

◆ ADIN1320_GE_MGC_0_KEY_3_MASK

#define ADIN1320_GE_MGC_0_KEY_3_MASK   NO_OS_GENMASK(15, 8)

◆ ADIN1320_GE_MGC_0_KEY_45

#define ADIN1320_GE_MGC_0_KEY_45   NO_OS_MDIO_C45_ADDR(0x1e, 0xff83)

◆ ADIN1320_GE_MGC_0_KEY_4_MASK

#define ADIN1320_GE_MGC_0_KEY_4_MASK   NO_OS_GENMASK(7, 0)

◆ ADIN1320_GE_MGC_0_KEY_4BY_EN_MASK

#define ADIN1320_GE_MGC_0_KEY_4BY_EN_MASK   NO_OS_BIT(8)

◆ ADIN1320_GE_MGC_0_KEY_5_MASK

#define ADIN1320_GE_MGC_0_KEY_5_MASK   NO_OS_GENMASK(15, 8)

◆ ADIN1320_GE_MGC_0_KEY_CHK_EN_MASK

#define ADIN1320_GE_MGC_0_KEY_CHK_EN_MASK   NO_OS_BIT(7)

◆ ADIN1320_GE_MGC_0_KEY_ERR_MASK

#define ADIN1320_GE_MGC_0_KEY_ERR_MASK   NO_OS_BIT(2)

◆ ADIN1320_GE_MGC_0_LEN_CHK_EN_MASK

#define ADIN1320_GE_MGC_0_LEN_CHK_EN_MASK   NO_OS_BIT(6)

◆ ADIN1320_GE_MODEL_NUM_MASK

#define ADIN1320_GE_MODEL_NUM_MASK   NO_OS_GENMASK(9, 4)

◆ ADIN1320_GE_MSEL_AUTO_GE_MASK

#define ADIN1320_GE_MSEL_AUTO_GE_MASK   NO_OS_BIT(0)

◆ ADIN1320_GE_MSEL_AUTO_SD_MASK

#define ADIN1320_GE_MSEL_AUTO_SD_MASK   NO_OS_BIT(1)

◆ ADIN1320_GE_MSEL_AUTO_STAT

#define ADIN1320_GE_MSEL_AUTO_STAT   NO_OS_MDIO_C45_ADDR(0x1e, 0xff57)

◆ ADIN1320_GE_PHY_ID_1

#define ADIN1320_GE_PHY_ID_1   NO_OS_MDIO_C45_ADDR(0x1e, 0xff00)

◆ ADIN1320_GE_PHY_ID_1_RESET

#define ADIN1320_GE_PHY_ID_1_RESET   0x0283

◆ ADIN1320_GE_PHY_ID_2

#define ADIN1320_GE_PHY_ID_2   NO_OS_MDIO_C45_ADDR(0x1e, 0xff01)

◆ ADIN1320_GE_PHY_LED_CFG

#define ADIN1320_GE_PHY_LED_CFG   NO_OS_MDIO_C45_ADDR(0x1e, 0xff29)

◆ ADIN1320_GE_REF_CLK_EN_MASK

#define ADIN1320_GE_REF_CLK_EN_MASK   NO_OS_BIT(3)

◆ ADIN1320_GE_REV_NUM_MASK

#define ADIN1320_GE_REV_NUM_MASK   NO_OS_GENMASK(3, 0)

◆ ADIN1320_GE_RGMII_100_LOW_LTNCY_EN_MASK

#define ADIN1320_GE_RGMII_100_LOW_LTNCY_EN_MASK   NO_OS_BIT(10)

◆ ADIN1320_GE_RGMII_10_LOW_LTNCY_EN_MASK

#define ADIN1320_GE_RGMII_10_LOW_LTNCY_EN_MASK   NO_OS_BIT(9)

◆ ADIN1320_GE_RGMII_CFG

#define ADIN1320_GE_RGMII_CFG   NO_OS_MDIO_C45_ADDR(0x1e, 0xff23)

◆ ADIN1320_GE_RGMII_CFG_RESERVED_MASK

#define ADIN1320_GE_RGMII_CFG_RESERVED_MASK   NO_OS_GENMASK(15, 11)

◆ ADIN1320_GE_RGMII_EN_MASK

#define ADIN1320_GE_RGMII_EN_MASK   NO_OS_BIT(0)

◆ ADIN1320_GE_RGMII_GTX_SEL_MASK

#define ADIN1320_GE_RGMII_GTX_SEL_MASK   NO_OS_GENMASK(5, 3)

◆ ADIN1320_GE_RGMII_RX_ID_EN_MASK

#define ADIN1320_GE_RGMII_RX_ID_EN_MASK   NO_OS_BIT(2)

◆ ADIN1320_GE_RGMII_RX_SEL_MASK

#define ADIN1320_GE_RGMII_RX_SEL_MASK   NO_OS_GENMASK(8, 6)

◆ ADIN1320_GE_RGMII_TX_ID_EN_MASK

#define ADIN1320_GE_RGMII_TX_ID_EN_MASK   NO_OS_BIT(1)

◆ ADIN1320_GE_RMII_CFG

#define ADIN1320_GE_RMII_CFG   NO_OS_MDIO_C45_ADDR(0x1e, 0xff24)

◆ ADIN1320_GE_RMII_EN_MASK

#define ADIN1320_GE_RMII_EN_MASK   NO_OS_BIT(0)

◆ ADIN1320_GE_RMII_FIFO_RST_MASK

#define ADIN1320_GE_RMII_FIFO_RST_MASK   NO_OS_BIT(7)

◆ ADIN1320_GE_SD_CFG

#define ADIN1320_GE_SD_CFG   NO_OS_MDIO_C45_ADDR(0x1e, 0xff53)

◆ ADIN1320_GE_SFT_RST

#define ADIN1320_GE_SFT_RST   NO_OS_MDIO_C45_ADDR(0x1e, 0xff0c)

◆ ADIN1320_GE_SFT_RST_CFG_EN

#define ADIN1320_GE_SFT_RST_CFG_EN   NO_OS_MDIO_C45_ADDR(0x1e, 0xff0d)

◆ ADIN1320_GE_SFT_RST_CFG_EN_MASK

#define ADIN1320_GE_SFT_RST_CFG_EN_MASK   NO_OS_BIT(0)

◆ ADIN1320_GE_SFT_RST_MASK

#define ADIN1320_GE_SFT_RST_MASK   NO_OS_BIT(0)

◆ ADIN1320_GE_WOL_2_PHY_SD_SEL_MASK

#define ADIN1320_GE_WOL_2_PHY_SD_SEL_MASK   NO_OS_BIT(0)

◆ ADIN1320_GE_WOL_EN

#define ADIN1320_GE_WOL_EN   NO_OS_MDIO_C45_ADDR(0x1e, 0xff79)

◆ ADIN1320_GE_WOL_EN_MASK

#define ADIN1320_GE_WOL_EN_MASK   NO_OS_BIT(0)

◆ ADIN1320_GE_WOL_KEY_ERR_WAKE_EN_MASK

#define ADIN1320_GE_WOL_KEY_ERR_WAKE_EN_MASK   NO_OS_BIT(1)

◆ ADIN1320_GE_WOL_LS_CHG_MASK

#define ADIN1320_GE_WOL_LS_CHG_MASK   NO_OS_BIT(0)

◆ ADIN1320_GE_WOL_LS_CHG_WAKE_EN_MASK

#define ADIN1320_GE_WOL_LS_CHG_WAKE_EN_MASK   NO_OS_BIT(0)

◆ ADIN1320_GE_WOL_PUL_EN_MASK

#define ADIN1320_GE_WOL_PUL_EN_MASK   NO_OS_BIT(0)

◆ ADIN1320_GE_WOL_PUL_LENM_1_MASK

#define ADIN1320_GE_WOL_PUL_LENM_1_MASK   NO_OS_GENMASK(11, 8)

◆ ADIN1320_GE_WOL_SIG_CNTRL

#define ADIN1320_GE_WOL_SIG_CNTRL   NO_OS_MDIO_C45_ADDR(0x1e, 0xff7b)

◆ ADIN1320_GE_WOL_STA_0_AD_01

#define ADIN1320_GE_WOL_STA_0_AD_01   NO_OS_MDIO_C45_ADDR(0x1e, 0xff7c)

◆ ADIN1320_GE_WOL_STA_0_AD_0_MASK

#define ADIN1320_GE_WOL_STA_0_AD_0_MASK   NO_OS_GENMASK(7, 0)

◆ ADIN1320_GE_WOL_STA_0_AD_1_MASK

#define ADIN1320_GE_WOL_STA_0_AD_1_MASK   NO_OS_GENMASK(15, 8)

◆ ADIN1320_GE_WOL_STA_0_AD_23

#define ADIN1320_GE_WOL_STA_0_AD_23   NO_OS_MDIO_C45_ADDR(0x1e, 0xff7d)

◆ ADIN1320_GE_WOL_STA_0_AD_2_MASK

#define ADIN1320_GE_WOL_STA_0_AD_2_MASK   NO_OS_GENMASK(7, 0)

◆ ADIN1320_GE_WOL_STA_0_AD_3_MASK

#define ADIN1320_GE_WOL_STA_0_AD_3_MASK   NO_OS_GENMASK(15, 8)

◆ ADIN1320_GE_WOL_STA_0_AD_45

#define ADIN1320_GE_WOL_STA_0_AD_45   NO_OS_MDIO_C45_ADDR(0x1e, 0xff7e)

◆ ADIN1320_GE_WOL_STA_0_AD_4_MASK

#define ADIN1320_GE_WOL_STA_0_AD_4_MASK   NO_OS_GENMASK(7, 0)

◆ ADIN1320_GE_WOL_STA_0_AD_5_MASK

#define ADIN1320_GE_WOL_STA_0_AD_5_MASK   NO_OS_GENMASK(15, 8)

◆ ADIN1320_GE_WOL_STAT

#define ADIN1320_GE_WOL_STAT   NO_OS_MDIO_C45_ADDR(0x1e, 0xff85)

◆ ADIN1320_GE_WOL_SYS_CNTRL

#define ADIN1320_GE_WOL_SYS_CNTRL   NO_OS_MDIO_C45_ADDR(0x1e, 0xff78)

◆ ADIN1320_GE_WOL_WAKE_CNTRL

#define ADIN1320_GE_WOL_WAKE_CNTRL   NO_OS_MDIO_C45_ADDR(0x1e, 0xff7a)

◆ ADIN1320_GE_WOL_WAKE_INV_EN_MASK

#define ADIN1320_GE_WOL_WAKE_INV_EN_MASK   NO_OS_BIT(1)

◆ ADIN1320_GE_WOL_WAKE_IRQ_EN_MASK

#define ADIN1320_GE_WOL_WAKE_IRQ_EN_MASK   NO_OS_BIT(7)

◆ ADIN1320_GE_WOL_WAKE_IRQ_LH_MASK

#define ADIN1320_GE_WOL_WAKE_IRQ_LH_MASK   NO_OS_BIT(7)

◆ ADIN1320_HCD_TECH_MASK

#define ADIN1320_HCD_TECH_MASK   NO_OS_GENMASK(9, 7)

◆ ADIN1320_HD_1000_ADV_MASK

#define ADIN1320_HD_1000_ADV_MASK   NO_OS_BIT(8)

◆ ADIN1320_HD_100_ADV_MASK

#define ADIN1320_HD_100_ADV_MASK   NO_OS_BIT(7)

◆ ADIN1320_HD_10_ADV_MASK

#define ADIN1320_HD_10_ADV_MASK   NO_OS_BIT(5)

◆ ADIN1320_HW_IRQ_EN_MASK

#define ADIN1320_HW_IRQ_EN_MASK   NO_OS_BIT(0)

◆ ADIN1320_IDLE_ERR_CNT_IRQ_EN_MASK

#define ADIN1320_IDLE_ERR_CNT_IRQ_EN_MASK   NO_OS_BIT(5)

◆ ADIN1320_IDLE_ERR_CNT_IRQ_STAT_MASK

#define ADIN1320_IDLE_ERR_CNT_IRQ_STAT_MASK   NO_OS_BIT(5)

◆ ADIN1320_IRQ_MASK

#define ADIN1320_IRQ_MASK   0x0018

◆ ADIN1320_IRQ_PENDING_MASK

#define ADIN1320_IRQ_PENDING_MASK   NO_OS_BIT(0)

◆ ADIN1320_IRQ_STATUS

#define ADIN1320_IRQ_STATUS   0x0019

◆ ADIN1320_JABBER_DET_LAT_MASK

#define ADIN1320_JABBER_DET_LAT_MASK   NO_OS_BIT(1)

◆ ADIN1320_LB_ALL_DIG_SEL_MASK

#define ADIN1320_LB_ALL_DIG_SEL_MASK   NO_OS_BIT(12)

◆ ADIN1320_LED_0_CFG_MASK

#define ADIN1320_LED_0_CFG_MASK   NO_OS_GENMASK(3, 0)

◆ ADIN1320_LED_0_EXT_CFG_EN_MASK

#define ADIN1320_LED_0_EXT_CFG_EN_MASK   NO_OS_BIT(10)

◆ ADIN1320_LED_1_CFG_MASK

#define ADIN1320_LED_1_CFG_MASK   NO_OS_GENMASK(7, 4)

◆ ADIN1320_LED_1_EXT_CFG_EN_MASK

#define ADIN1320_LED_1_EXT_CFG_EN_MASK   NO_OS_BIT(11)

◆ ADIN1320_LED_2_CFG_MASK

#define ADIN1320_LED_2_CFG_MASK   NO_OS_GENMASK(11, 8)

◆ ADIN1320_LED_2_EXT_CFG_EN_MASK

#define ADIN1320_LED_2_EXT_CFG_EN_MASK   NO_OS_BIT(12)

◆ ADIN1320_LED_3_CFG_MASK

#define ADIN1320_LED_3_CFG_MASK   NO_OS_GENMASK(15, 12)

◆ ADIN1320_LED_3_EXT_CFG_EN_MASK

#define ADIN1320_LED_3_EXT_CFG_EN_MASK   NO_OS_BIT(13)

◆ ADIN1320_LED_A_INV_EN_MASK

#define ADIN1320_LED_A_INV_EN_MASK   NO_OS_BIT(3)

◆ ADIN1320_LED_B_INV_EN_MASK

#define ADIN1320_LED_B_INV_EN_MASK   NO_OS_BIT(4)

◆ ADIN1320_LED_C_INV_EN_MASK

#define ADIN1320_LED_C_INV_EN_MASK   NO_OS_BIT(5)

◆ ADIN1320_LED_CFG_VAL

#define ADIN1320_LED_CFG_VAL   NO_OS_GENMASK(3, 0)

◆ ADIN1320_LED_CTRL_1

#define ADIN1320_LED_CTRL_1   0x001b

◆ ADIN1320_LED_CTRL_2

#define ADIN1320_LED_CTRL_2   0x001c

◆ ADIN1320_LED_CTRL_3

#define ADIN1320_LED_CTRL_3   0x001d

◆ ADIN1320_LED_D_INV_EN_MASK

#define ADIN1320_LED_D_INV_EN_MASK   NO_OS_BIT(6)

◆ ADIN1320_LED_EXT_CFG_EN_VAL

#define ADIN1320_LED_EXT_CFG_EN_VAL   NO_OS_BIT(4)

LED config value extraction: Bit 4 maps to LED_x_EXT_CFG_EN, Bits [3:0] map to LED_x_CFG

◆ ADIN1320_LED_OE_N_MASK

#define ADIN1320_LED_OE_N_MASK   NO_OS_BIT(1)

◆ ADIN1320_LED_PAT_MASK

#define ADIN1320_LED_PAT_MASK   NO_OS_GENMASK(7, 0)

◆ ADIN1320_LED_PAT_PAUSE_DUR_MASK

#define ADIN1320_LED_PAT_PAUSE_DUR_MASK   NO_OS_GENMASK(7, 4)

◆ ADIN1320_LED_PAT_SEL_MASK

#define ADIN1320_LED_PAT_SEL_MASK   NO_OS_GENMASK(15, 14)

◆ ADIN1320_LED_PAT_TICK_DUR_MASK

#define ADIN1320_LED_PAT_TICK_DUR_MASK   NO_OS_GENMASK(13, 8)

◆ ADIN1320_LED_PUL_STR_DUR_SEL_MASK

#define ADIN1320_LED_PUL_STR_DUR_SEL_MASK   NO_OS_GENMASK(3, 2)

◆ ADIN1320_LED_PUL_STR_EN_MASK

#define ADIN1320_LED_PUL_STR_EN_MASK   NO_OS_BIT(0)

◆ ADIN1320_LINK_EN_MASK

#define ADIN1320_LINK_EN_MASK   NO_OS_BIT(13)

◆ ADIN1320_LINK_STAT_LAT_MASK

#define ADIN1320_LINK_STAT_LAT_MASK   NO_OS_BIT(2)

◆ ADIN1320_LINK_STAT_MASK

#define ADIN1320_LINK_STAT_MASK   NO_OS_BIT(6)

◆ ADIN1320_LNK_STAT_CHNG_IRQ_EN_MASK

#define ADIN1320_LNK_STAT_CHNG_IRQ_EN_MASK   NO_OS_BIT(2)

◆ ADIN1320_LNK_STAT_CHNG_IRQ_STAT_MASK

#define ADIN1320_LNK_STAT_CHNG_IRQ_STAT_MASK   NO_OS_BIT(2)

◆ ADIN1320_LOOPBACK_MASK

#define ADIN1320_LOOPBACK_MASK   NO_OS_BIT(14)

◆ ADIN1320_LP_ABILITY

#define ADIN1320_LP_ABILITY   0x0005

◆ ADIN1320_LP_RX_NEXT_PAGE

#define ADIN1320_LP_RX_NEXT_PAGE   0x0008

◆ ADIN1320_MAN_MDIX_MASK

#define ADIN1320_MAN_MDIX_MASK   NO_OS_BIT(9)

◆ ADIN1320_MAN_MSTR_ADV_MASK

#define ADIN1320_MAN_MSTR_ADV_MASK   NO_OS_BIT(11)

◆ ADIN1320_MAN_MSTR_SLV_EN_ADV_MASK

#define ADIN1320_MAN_MSTR_SLV_EN_ADV_MASK   NO_OS_BIT(12)

◆ ADIN1320_MDIO_SYNC_IRQ_EN_MASK

#define ADIN1320_MDIO_SYNC_IRQ_EN_MASK   NO_OS_BIT(9)

◆ ADIN1320_MDIO_SYNC_IRQ_STAT_MASK

#define ADIN1320_MDIO_SYNC_IRQ_STAT_MASK   NO_OS_BIT(9)

◆ ADIN1320_MII_CONTROL

#define ADIN1320_MII_CONTROL   0x0000

ADIN1320 Register Map

◆ ADIN1320_MII_STATUS

#define ADIN1320_MII_STATUS   0x0001

◆ ADIN1320_MII_STATUS_STRUCT_INIT

#define ADIN1320_MII_STATUS_STRUCT_INIT   {0, 0, 0, 0, 0}

Driver Macros

◆ ADIN1320_MODEL_NUM_MASK

#define ADIN1320_MODEL_NUM_MASK   NO_OS_GENMASK(9, 4)

◆ ADIN1320_MSTR_RSLVD_MASK

#define ADIN1320_MSTR_RSLVD_MASK   NO_OS_BIT(14)

◆ ADIN1320_MSTR_SLV_CONTROL

#define ADIN1320_MSTR_SLV_CONTROL   0x0009

◆ ADIN1320_MSTR_SLV_FLT_MASK

#define ADIN1320_MSTR_SLV_FLT_MASK   NO_OS_BIT(15)

◆ ADIN1320_MSTR_SLV_STATUS

#define ADIN1320_MSTR_SLV_STATUS   0x000a

◆ ADIN1320_NRG_PD_EN_MASK

#define ADIN1320_NRG_PD_EN_MASK   NO_OS_BIT(3)

◆ ADIN1320_NRG_PD_TX_EN_MASK

#define ADIN1320_NRG_PD_TX_EN_MASK   NO_OS_BIT(2)

◆ ADIN1320_NUM_SPEED_RETRY_MASK

#define ADIN1320_NUM_SPEED_RETRY_MASK   NO_OS_GENMASK(12, 10)

◆ ADIN1320_PAGE_RX_IRQ_EN_MASK

#define ADIN1320_PAGE_RX_IRQ_EN_MASK   NO_OS_BIT(6)

◆ ADIN1320_PAGE_RX_IRQ_STAT_MASK

#define ADIN1320_PAGE_RX_IRQ_STAT_MASK   NO_OS_BIT(6)

◆ ADIN1320_PHY_CTRL_1

#define ADIN1320_PHY_CTRL_1   0x0012

◆ ADIN1320_PHY_CTRL_2

#define ADIN1320_PHY_CTRL_2   0x0016

◆ ADIN1320_PHY_CTRL_3

#define ADIN1320_PHY_CTRL_3   0x0017

◆ ADIN1320_PHY_CTRL_STATUS_1

#define ADIN1320_PHY_CTRL_STATUS_1   0x0013

◆ ADIN1320_PHY_CTRL_STATUS_2

#define ADIN1320_PHY_CTRL_STATUS_2   0x0015

◆ ADIN1320_PHY_ID

#define ADIN1320_PHY_ID   0x6

ADIN1320 PHY ID

◆ ADIN1320_PHY_ID_1

#define ADIN1320_PHY_ID_1   0x0002

◆ ADIN1320_PHY_ID_2

#define ADIN1320_PHY_ID_2   0x0003

◆ ADIN1320_PHY_IN_NRG_PD_MASK

#define ADIN1320_PHY_IN_NRG_PD_MASK   NO_OS_BIT(1)

◆ ADIN1320_PHY_STATUS_1

#define ADIN1320_PHY_STATUS_1   0x001a

◆ ADIN1320_PHY_STATUS_2

#define ADIN1320_PHY_STATUS_2   0x001f

◆ ADIN1320_REM_FLT_LAT_MASK

#define ADIN1320_REM_FLT_LAT_MASK   NO_OS_BIT(4)

◆ ADIN1320_RESTART_ANEG_MASK

#define ADIN1320_RESTART_ANEG_MASK   NO_OS_BIT(9)

◆ ADIN1320_REV_NUM_MASK

#define ADIN1320_REV_NUM_MASK   NO_OS_GENMASK(3, 0)

◆ ADIN1320_RX_STAT_CHNG_IRQ_EN_MASK

#define ADIN1320_RX_STAT_CHNG_IRQ_EN_MASK   NO_OS_BIT(3)

◆ ADIN1320_RX_STAT_CHNG_IRQ_STAT_MASK

#define ADIN1320_RX_STAT_CHNG_IRQ_STAT_MASK   NO_OS_BIT(3)

◆ ADIN1320_SD_AN_CHG_IRQ_LH_MASK

#define ADIN1320_SD_AN_CHG_IRQ_LH_MASK   NO_OS_BIT(7)

◆ ADIN1320_SD_AN_DONE_MASK

#define ADIN1320_SD_AN_DONE_MASK   NO_OS_BIT(5)

◆ ADIN1320_SD_AN_STAT_CHG_IRQ_EN_MASK

#define ADIN1320_SD_AN_STAT_CHG_IRQ_EN_MASK   NO_OS_BIT(7)

◆ ADIN1320_SD_AUTONEG_ADV

#define ADIN1320_SD_AUTONEG_ADV   NO_OS_MDIO_C45_ADDR(0x1e, 0xfc04)

◆ ADIN1320_SD_AUTONEG_EN_CFG_MASK

#define ADIN1320_SD_AUTONEG_EN_CFG_MASK   NO_OS_BIT(2)

◆ ADIN1320_SD_CONTROL

#define ADIN1320_SD_CONTROL   NO_OS_MDIO_C45_ADDR(0x1e, 0xfc00)

◆ ADIN1320_SD_FC_FG_IRQ_EN_MASK

#define ADIN1320_SD_FC_FG_IRQ_EN_MASK   NO_OS_BIT(6)

◆ ADIN1320_SD_FC_FG_IRQ_LH_MASK

#define ADIN1320_SD_FC_FG_IRQ_LH_MASK   NO_OS_BIT(6)

◆ ADIN1320_SD_FD_1000ADV_MASK

#define ADIN1320_SD_FD_1000ADV_MASK   NO_OS_BIT(5)

◆ ADIN1320_SD_FIB_LED_CFG_0

#define ADIN1320_SD_FIB_LED_CFG_0   NO_OS_MDIO_C45_ADDR(0x1e, 0xfcaa)

◆ ADIN1320_SD_FIB_LED_CFG_0_MASK

#define ADIN1320_SD_FIB_LED_CFG_0_MASK   NO_OS_GENMASK(3, 0)

◆ ADIN1320_SD_FIB_LED_CFG_1

#define ADIN1320_SD_FIB_LED_CFG_1   NO_OS_MDIO_C45_ADDR(0x1e, 0xfcab)

◆ ADIN1320_SD_FIB_LED_CFG_1_MASK

#define ADIN1320_SD_FIB_LED_CFG_1_MASK   NO_OS_GENMASK(3, 0)

◆ ADIN1320_SD_FIB_LED_CFG_2

#define ADIN1320_SD_FIB_LED_CFG_2   NO_OS_MDIO_C45_ADDR(0x1e, 0xfcac)

◆ ADIN1320_SD_FIB_LED_CFG_2_MASK

#define ADIN1320_SD_FIB_LED_CFG_2_MASK   NO_OS_GENMASK(3, 0)

◆ ADIN1320_SD_FIB_LED_CFG_3

#define ADIN1320_SD_FIB_LED_CFG_3   NO_OS_MDIO_C45_ADDR(0x1e, 0xfcad)

◆ ADIN1320_SD_FIB_LED_CFG_3_MASK

#define ADIN1320_SD_FIB_LED_CFG_3_MASK   NO_OS_GENMASK(3, 0)

◆ ADIN1320_SD_FIFO_OU_IRQ_EN_MASK

#define ADIN1320_SD_FIFO_OU_IRQ_EN_MASK   NO_OS_BIT(4)

◆ ADIN1320_SD_FIFO_OU_IRQ_LH_MASK

#define ADIN1320_SD_FIFO_OU_IRQ_LH_MASK   NO_OS_BIT(4)

◆ ADIN1320_SD_HD_1000ADV_MASK

#define ADIN1320_SD_HD_1000ADV_MASK   NO_OS_BIT(6)

◆ ADIN1320_SD_IRQ_MASK

#define ADIN1320_SD_IRQ_MASK   NO_OS_MDIO_C45_ADDR(0x1e, 0xfc18)

◆ ADIN1320_SD_IRQ_STATUS

#define ADIN1320_SD_IRQ_STATUS   NO_OS_MDIO_C45_ADDR(0x1e, 0xfc19)

◆ ADIN1320_SD_JABBER_DET_LH_MASK

#define ADIN1320_SD_JABBER_DET_LH_MASK   NO_OS_BIT(1)

◆ ADIN1320_SD_LINK_STAT_CHG_IRQ_EN_MASK

#define ADIN1320_SD_LINK_STAT_CHG_IRQ_EN_MASK   NO_OS_BIT(1)

◆ ADIN1320_SD_LINK_STAT_CHG_LH_MASK

#define ADIN1320_SD_LINK_STAT_CHG_LH_MASK   NO_OS_BIT(1)

◆ ADIN1320_SD_LINK_STAT_OK_LL_MASK

#define ADIN1320_SD_LINK_STAT_OK_LL_MASK   NO_OS_BIT(2)

◆ ADIN1320_SD_LINK_TYPE_CFG_MASK

#define ADIN1320_SD_LINK_TYPE_CFG_MASK   NO_OS_GENMASK(7, 5)

◆ ADIN1320_SD_MDIO_ERR_IRQ_EN_MASK

#define ADIN1320_SD_MDIO_ERR_IRQ_EN_MASK   NO_OS_BIT(0)

◆ ADIN1320_SD_MDIO_ERR_LH_MASK

#define ADIN1320_SD_MDIO_ERR_LH_MASK   NO_OS_BIT(0)

◆ ADIN1320_SD_OS_RX_PLL_LCK_LOST_IRQ_EN_MASK

#define ADIN1320_SD_OS_RX_PLL_LCK_LOST_IRQ_EN_MASK   NO_OS_BIT(10)

◆ ADIN1320_SD_OS_RX_PLL_LCK_LOST_IRQ_LH_MASK

#define ADIN1320_SD_OS_RX_PLL_LCK_LOST_IRQ_LH_MASK   NO_OS_BIT(10)

◆ ADIN1320_SD_PAGE_RX_IRQ_EN_MASK

#define ADIN1320_SD_PAGE_RX_IRQ_EN_MASK   NO_OS_BIT(5)

◆ ADIN1320_SD_PAGE_RX_IRQ_LH_MASK

#define ADIN1320_SD_PAGE_RX_IRQ_LH_MASK   NO_OS_BIT(5)

◆ ADIN1320_SD_REM_FLT_LH_MASK

#define ADIN1320_SD_REM_FLT_LH_MASK   NO_OS_BIT(4)

◆ ADIN1320_SD_RESTART_ANEG_MASK

#define ADIN1320_SD_RESTART_ANEG_MASK   NO_OS_BIT(9)

◆ ADIN1320_SD_RX_CLK_125_EN_MASK

#define ADIN1320_SD_RX_CLK_125_EN_MASK   NO_OS_BIT(10)

◆ ADIN1320_SD_RX_CLK_HRT_EN_MASK

#define ADIN1320_SD_RX_CLK_HRT_EN_MASK   NO_OS_BIT(8)

◆ ADIN1320_SD_RX_PLL_LCK_LOST_IRQ_EN_MASK

#define ADIN1320_SD_RX_PLL_LCK_LOST_IRQ_EN_MASK   NO_OS_BIT(9)

◆ ADIN1320_SD_RX_PLL_LCK_LOST_IRQ_LH_MASK

#define ADIN1320_SD_RX_PLL_LCK_LOST_IRQ_LH_MASK   NO_OS_BIT(9)

◆ ADIN1320_SD_SGMII_EN_MASK

#define ADIN1320_SD_SGMII_EN_MASK   NO_OS_BIT(0)

◆ ADIN1320_SD_STATUS

#define ADIN1320_SD_STATUS   NO_OS_MDIO_C45_ADDR(0x1e, 0xfc01)

◆ ADIN1320_SD_TX_CLK_125_EN_MASK

#define ADIN1320_SD_TX_CLK_125_EN_MASK   NO_OS_BIT(9)

◆ ADIN1320_SD_TX_CLK_HRT_EN_MASK

#define ADIN1320_SD_TX_CLK_HRT_EN_MASK   NO_OS_BIT(7)

◆ ADIN1320_SD_TX_PLL_LCK_LOST_IRQ_EN_MASK

#define ADIN1320_SD_TX_PLL_LCK_LOST_IRQ_EN_MASK   NO_OS_BIT(8)

◆ ADIN1320_SD_TX_PLL_LCK_LOST_IRQ_LH_MASK

#define ADIN1320_SD_TX_PLL_LCK_LOST_IRQ_LH_MASK   NO_OS_BIT(8)

◆ ADIN1320_SELECTOR_ADV_MASK

#define ADIN1320_SELECTOR_ADV_MASK   NO_OS_GENMASK(4, 0)

◆ ADIN1320_SET_DOWNSPEED_RETRIES_MAX

#define ADIN1320_SET_DOWNSPEED_RETRIES_MAX   0x08

◆ ADIN1320_SFT_PD_MASK

#define ADIN1320_SFT_PD_MASK   NO_OS_BIT(11)

◆ ADIN1320_SFT_RST_MASK

#define ADIN1320_SFT_RST_MASK   NO_OS_BIT(15)

◆ ADIN1320_SPEED_CHG_IRQ_EN_MASK

#define ADIN1320_SPEED_CHG_IRQ_EN_MASK   NO_OS_BIT(1)

◆ ADIN1320_SPEED_CHNG_IRQ_STAT_MASK

#define ADIN1320_SPEED_CHNG_IRQ_STAT_MASK   NO_OS_BIT(1)

◆ ADIN1320_SPEED_SEL_LSB_MASK

#define ADIN1320_SPEED_SEL_LSB_MASK   NO_OS_BIT(13)

◆ ADIN1320_SPEED_SEL_MSB_MASK

#define ADIN1320_SPEED_SEL_MSB_MASK   NO_OS_BIT(6)

◆ ADIN1320_STATION_ADDRESS_MAX_BYTE

#define ADIN1320_STATION_ADDRESS_MAX_BYTE   6

◆ ADIN1320_TX_NEXT_PAGE

#define ADIN1320_TX_NEXT_PAGE   0x0007

◆ ADIN1320_WOL_SIG_CFG_PUL_LEN_MAX

#define ADIN1320_WOL_SIG_CFG_PUL_LEN_MAX   0x10

Enumeration Type Documentation

◆ adin1320_active_media

enum adin1320_active_media
Enumerator
ADIN1320_ACTIVE_MEDIA_NULL 
ADIN1320_ACTIVE_MEDIA_CU 
ADIN1320_ACTIVE_MEDIA_SD 

◆ adin1320_adv_master_slave_cfg

enum adin1320_adv_master_slave_cfg
Enumerator
ADIN1320_MAN_ADV_MASTER 
ADIN1320_MAN_ADV_SLAVE 
ADIN1320_MAN_MSTR_SLV_DIS 

◆ adin1320_auto_mdix

enum adin1320_auto_mdix
Enumerator
ADIN1320_MANUAL_MDI 
ADIN1320_MANUAL_MDIX 
ADIN1320_AUTO_MDIX_PREFER_MDIX 
ADIN1320_AUTO_MDIX_PREFER_MDI 

◆ adin1320_autoneg_enable

enum adin1320_autoneg_enable
Enumerator
ADIN1320_AUTONEG_DISABLE 
ADIN1320_AUTONEG_ENABLE 

◆ adin1320_autoneg_stat

enum adin1320_autoneg_stat
Enumerator
ADIN1320_AUTONEG_STAT_MIN 
ADIN1320_AUTONEG_STAT_NO_CHECK 
ADIN1320_AUTONEG_STAT_NOT_DONE 
ADIN1320_AUTONEG_STAT_DONE 
ADIN1320_AUTONEG_STAT_MAX 

◆ adin1320_clk25_ref_enable

enum adin1320_clk25_ref_enable
Enumerator
ADIN1320_CLK25_REF_DISABLE 
ADIN1320_CLK25_REF_ENABLE 

◆ adin1320_cu_led_cfg

enum adin1320_cu_led_cfg
Enumerator
ADIN1320_CU_LED_CFG_MIN 
ADIN1320_CU_LED_CFG_ON_1000 

On if 1000BASE-T link

ADIN1320_CU_LED_CFG_ON_100 

On if 100BASE-TX link

ADIN1320_CU_LED_CFG_ON_10 

On if 10BASE-T link

ADIN1320_CU_LED_CFG_ON_1000_BLNK_100 

On if 1000BASE-T link, blink if 100BASE-TX

ADIN1320_CU_LED_CFG_ON_LINK 

On if link up

ADIN1320_CU_LED_CFG_ON_TX 

On if transmitting

ADIN1320_CU_LED_CFG_ON_RX 

On if receiving

ADIN1320_CU_LED_CFG_ON_TX_RX 

On if activity (transmitting or receiving)

ADIN1320_CU_LED_CFG_ON_LINK_FD 

On if full duplex link

ADIN1320_CU_LED_CFG_ON_COL 

On if collision

ADIN1320_CU_LED_CFG_ON_LINK_BLNK_TX_RX 

On if link, blink on activity

ADIN1320_CU_LED_CFG_ON_LINK_BLNK_RX 

On if link, blink if receiving

ADIN1320_CU_LED_CFG_ON_LINK_FD_BLNK_COL 

On if full duplex link, blink on collision

ADIN1320_CU_LED_CFG_BLNK 

Blink

ADIN1320_CU_LED_CFG_ON 

ON

ADIN1320_CU_LED_CFG_OFF 

OFF

ADIN1320_CU_LED_CFG_ON_10_100 

On if 10BASE-T or 100BASE-TX link

ADIN1320_CU_LED_CFG_ON_100_1000 

On if 100BASE-TX or 1000BASE-T link

ADIN1320_CU_LED_CFG_ON_10_BLNK_TX_RX 

On if 10BASE-T link, blink on activity

ADIN1320_CU_LED_CFG_ON_100_BLNK_TX_RX 

On if 100BASE-TX link, blink on activity

ADIN1320_CU_LED_CFG_ON_1000_BLNK_TX_RX 

On if 1000BASE-T link, blink on activity

ADIN1320_CU_LED_CFG_ON_10_100_BLNK_TX_RX 

On if 10BASE-T or 100BASE-TX link, blink on activity

ADIN1320_CU_LED_CFG_ON_100_1000_BLNK_TX_RX 

On if 100BASE-TX or 1000BASE-T link, blink on activity

ADIN1320_CU_LED_CFG_ON_10_1000 

On if 10BASE-T or 1000BASE-T link

ADIN1320_CU_LED_CFG_ON_10_1000_BLNK_TX_RX 

On if 10BASE-T or 1000BASE-T link, blink on activity

ADIN1320_CU_LED_CFG_BLNK_TX_RX 

Blink on activity

ADIN1320_CU_LED_CFG_BLNK_TX 

Blink if transmitting

ADIN1320_CU_LED_CFG_ON_1000_BLNK_10 

On if 1000BASE-T link, blink if 10BASE-T link

ADIN1320_CU_LED_CFG_ON_100_BLNK_1000 

On if 100BASE-TX link, blink if 1000BASE-T link

ADIN1320_CU_LED_CFG_ON_100_BLNK_10 

On if 100BASE-TX link, blink if 10BASE-T link

ADIN1320_CU_LED_CFG_ON_10_BLNK_1000 

On if 10BASE-T link, blink if 1000BASE-T link

ADIN1320_CU_LED_CFG_ON_10_BLNK_100 

On if 10BASE-T link, blink if 100BASE-TX link

ADIN1320_CU_LED_CFG_MAX 

◆ adin1320_cu_speed

enum adin1320_cu_speed
Enumerator
ADIN1320_CU_SPEED_10BASE_T_HD 
ADIN1320_CU_SPEED_10BASE_T_FD 
ADIN1320_CU_SPEED_100BASE_TX_HD 
ADIN1320_CU_SPEED_100BASE_TX_FD 
ADIN1320_CU_SPEED_1000BASE_T_HD 
ADIN1320_CU_SPEED_1000BASE_T_FD 
ADIN1320_CU_SPEED_MAX 

◆ adin1320_downspeed

enum adin1320_downspeed
Enumerator
ADIN1320_DOWNSPEED_TO_10 
ADIN1320_DOWNSPEED_TO_100 

◆ adin1320_edpd_stat

enum adin1320_edpd_stat
Enumerator
ADIN1320_NOT_IN_NRG_PD_MODE 
ADIN1320_IN_NRG_PD_MODE 

◆ adin1320_eee_speeds

enum adin1320_eee_speeds
Enumerator
ADIN1320_EEE_100_ADV 
ADIN1320_EEE_1000_ADV 
ADIN1320_EEE_1000_KX_ADV 
ADIN1320_EEE_MAX 

◆ adin1320_energy_detect_pwd

enum adin1320_energy_detect_pwd
Enumerator
ADIN1320_NRG_PD_DIS 
ADIN1320_NRG_PD_EN 
ADIN1320_NRG_PD_TX_EN 
ADIN1320_NRG_PD_TX_DIS 

◆ adin1320_gp_clk_source

enum adin1320_gp_clk_source
Enumerator
ADIN1320_GP_CLK_MIN 
ADIN1320_GP_CLK_REFERENCE 
ADIN1320_GP_CLK_HEARTBEAT_FREE 
ADIN1320_GP_CLK_HEARTBEAT_RECOVERED 
ADIN1320_GP_CLK_FREE 
ADIN1320_GP_CLK_RECOVERED 
ADIN1320_GP_CLK_TX_HEARTBEAT 
ADIN1320_GP_CLK_RX_HEARTBEAT 
ADIN1320_GP_CLK_TX_FREE 
ADIN1320_GP_CLK_RX_RECOVERED 
ADIN1320_GP_CLK_DISABLE 
ADIN1320_GP_CLK_MAX 

◆ adin1320_lat_jabber_det

enum adin1320_lat_jabber_det
Enumerator
ADIN1320_LAT_JABBER_DET_MIN 
ADIN1320_LAT_JABBER_DET_NO_CHECK 
ADIN1320_LAT_JABBER_DET_NONE_DETECTED 
ADIN1320_LAT_JABBER_DET_DETECTED 
ADIN1320_LAT_JABBER_DET_MAX 

◆ adin1320_lat_link_stat

enum adin1320_lat_link_stat
Enumerator
ADIN1320_LAT_LINK_STAT_MIN 
ADIN1320_LAT_LINK_STAT_NO_CHECK 
ADIN1320_LAT_LINK_STAT_NO_LINK_DROP 
ADIN1320_LAT_LINK_STAT_LINK_DROPPED 
ADIN1320_LAT_LINK_STAT_MAX 

◆ adin1320_lat_rem_flt

enum adin1320_lat_rem_flt
Enumerator
ADIN1320_LAT_REM_FLT_MIN 
ADIN1320_LAT_REM_FLT_NO_CHECK 
ADIN1320_LAT_REM_FLT_NONE_DETECTED 
ADIN1320_LAT_REM_FLT_DETECTED 
ADIN1320_LAT_REM_FLT_MAX 

◆ adin1320_led_inv_state

enum adin1320_led_inv_state
Enumerator
ADIN1320_LED_INV_STATE_ACTIVE_HIGH 
ADIN1320_LED_INV_STATE_ACTIVE_LOW 

◆ adin1320_led_output_enable

enum adin1320_led_output_enable
Enumerator
ADIN1320_LED_OUTPUT_DISABLE 
ADIN1320_LED_OUTPUT_ENABLE 

◆ adin1320_led_pul_str_dur_select

enum adin1320_led_pul_str_dur_select
Enumerator
ADIN1320_LED_PUL_STR_DUR_SELECT_MIN 
ADIN1320_LED_PUL_STR_DUR_SELECT_32 
ADIN1320_LED_PUL_STR_DUR_SELECT_64 
ADIN1320_LED_PUL_STR_DUR_SELECT_102 
ADIN1320_LED_PUL_STR_DUR_SELECT_PROG 
ADIN1320_LED_PUL_STR_DISABLE 
ADIN1320_LED_PUL_STR_DUR_SELECT_MAX 

◆ adin1320_led_sel

enum adin1320_led_sel
Enumerator
ADIN1320_LED_SEL_MIN 
ADIN1320_LED_SEL_0 
ADIN1320_LED_SEL_1 
ADIN1320_LED_SEL_2 
ADIN1320_LED_SEL_3 
ADIN1320_LED_SEL_MAX 

◆ adin1320_link_cfg_enable

enum adin1320_link_cfg_enable
Enumerator
ADIN1320_LINK_CFG_DISABLE 
ADIN1320_LINK_CFG_ENABLE 

◆ adin1320_link_stat

enum adin1320_link_stat
Enumerator
ADIN1320_LINK_STAT_MIN 
ADIN1320_LINK_STAT_NO_CHECK 
ADIN1320_LINK_STAT_LINKDOWN 
ADIN1320_LINK_STAT_LINKUP 
ADIN1320_LINK_STAT_MAX 

◆ adin1320_mac_interface

enum adin1320_mac_interface
Enumerator
ADIN1320_RGMII_MAC_INTERFACE 
ADIN1320_RMII_MAC_INTERFACE 
ADIN1320_MII_MAC_INTERFACE 
ADIN1320_SGMII_MAC_INTERFACE 

◆ adin1320_master_slave_status

enum adin1320_master_slave_status
Enumerator
ADIN1320_RESOLVED_TO_SLAVE 
ADIN1320_RESOLVED_TO_MASTER 
ADIN1320_MAST_SLAVE_FAULT_DETECT 

◆ adin1320_mgc_chk_en

enum adin1320_mgc_chk_en
Enumerator
ADIN1320_MGC_CHK_EN_CRC 
ADIN1320_MGC_CHK_EN_LEN 
ADIN1320_MGC_CHK_EN_KEY 
ADIN1320_MGC_CHK_EN_MAX 

◆ adin1320_mgc_key_byte

enum adin1320_mgc_key_byte
Enumerator
ADIN1320_MGC_KEY_BYTE_6 
ADIN1320_MGC_KEY_BYTE_4 

◆ adin1320_mgc_match_en

enum adin1320_mgc_match_en
Enumerator
ADIN1320_MGC_MATCH_EN_ST 
ADIN1320_MGC_MATCH_EN_UC 
ADIN1320_MGC_MATCH_EN_MC 
ADIN1320_MGC_MATCH_EN_BC 
ADIN1320_MGC_MATCH_EN_MAX 

◆ adin1320_rgmii_idelay

enum adin1320_rgmii_idelay
Enumerator
ADIN1320_RGMII_2_00_NS 
ADIN1320_RGMII_1_60_NS 
ADIN1320_RGMII_1_80_NS 
ADIN1320_RGMII_2_20_NS 
ADIN1320_RGMII_2_40_NS 

◆ adin1320_rgmii_idelay_enable

enum adin1320_rgmii_idelay_enable
Enumerator
ADIN1320_RGMII_IDELAY_DISABLE 
ADIN1320_RGMII_IDELAY_ENABLE 

◆ adin1320_sd_led_cfg

enum adin1320_sd_led_cfg
Enumerator
ADIN1320_SD_LED_CFG_MIN 
ADIN1320_SD_LED_CFG_ON_1000 

On if 1000BASE-X link

ADIN1320_SD_LED_CFG_ON_100 

On if 100BASE-FX link

ADIN1320_SD_LED_CFG_LINK 

Link Up

ADIN1320_SD_LED_CFG_BLNK_TX 

Blink on Transmitting

ADIN1320_SD_LED_CFG_BLNK_RX 

Blink on Receiving

ADIN1320_SD_LED_CFG_BLNK_TX_RX 

Blink on Activity

ADIN1320_SD_LED_CFG_LINK_BLNK_TX 

Link / Blink on Transmitting

ADIN1320_SD_LED_CFG_LINK_BLNK_RX 

Link / Blink on Receiving

ADIN1320_SD_LED_CFG_LINK_BLNK_TX_RX 

Link / Blink on Activity

ADIN1320_SD_LED_CFG_BLNK 

Blink

ADIN1320_SD_LED_CFG_ON 

ON

ADIN1320_SD_LED_CFG_OFF 

OFF

ADIN1320_SD_LED_CFG_MAX 

◆ adin1320_sd_speed

enum adin1320_sd_speed
Enumerator
ADIN1320_SD_SPEED_NO_BASE_X 
ADIN1320_SD_SPEED_100BASE_FX_HD 
ADIN1320_SD_SPEED_100BASE_FX_FD 
ADIN1320_SD_SPEED_1000BASE_KX 
ADIN1320_SD_SPEED_1000BASE_X_FD 
ADIN1320_SD_SPEED_1000BASE_X_HD 
ADIN1320_SD_SPEED_1000BASE_X_HDFD 

◆ adin1320_soft_reset_option

enum adin1320_soft_reset_option
Enumerator
ADIN1320_RESET_GE_SUBSYS 
ADIN1320_RESET_GE_SUBSYS_PIN 

◆ adin1320_software_powerdown

enum adin1320_software_powerdown
Enumerator
ADIN1320_SOFTWARE_POWERUP 
ADIN1320_SOFTWARE_POWERDOWN 

◆ adin1320_wol_enable

enum adin1320_wol_enable
Enumerator
ADIN1320_WOL_DISABLE 
ADIN1320_WOL_ENABLE 

◆ adin1320_wol_fi_en

enum adin1320_wol_fi_en
Enumerator
ADIN1320_WOL_FI_DIS 
ADIN1320_WOL_FI_EN 

◆ adin1320_wol_inv

enum adin1320_wol_inv
Enumerator
ADIN1320_WOL_INV_ACTIVE_HIGH 
ADIN1320_WOL_INV_ACTIVE_LOW 

◆ adin1320_wol_sig

enum adin1320_wol_sig
Enumerator
ADIN1320_WOL_SIG_LEVEL 
ADIN1320_WOL_SIG_PULSE 

◆ adin1320_wol_wake_key_enable

enum adin1320_wol_wake_key_enable
Enumerator
ADIN1320_WOL_WAKE_KEY_DISABLE 
ADIN1320_WOL_WAKE_KEY_ENABLE 

◆ adin1320_wol_wake_link_enable

enum adin1320_wol_wake_link_enable
Enumerator
ADIN1320_WOL_WAKE_LINK_DISABLE 
ADIN1320_WOL_WAKE_LINK_ENABLE 

Function Documentation

◆ adin1320_auto_mdix_cfg()

int adin1320_auto_mdix_cfg ( struct adin1320_desc * dev,
enum adin1320_auto_mdix val )

Auto MDIX Config.

Parameters
dev- The device structure
val- MDIX configuration
Returns
0 in case of success, negative code otherwise

◆ adin1320_config_clk25_ref()

int adin1320_config_clk25_ref ( struct adin1320_desc * dev,
enum adin1320_clk25_ref_enable enable )

Enable/disable GE Clock 25MHz Reference.

Parameters
dev- The device structure
enable- Enable/disable 25MHz Ref Clock
Returns
0 in case of success, negative code otherwise

◆ adin1320_config_gp_clk()

int adin1320_config_gp_clk ( struct adin1320_desc * dev,
enum adin1320_gp_clk_source source )

Configure GP Clock.

Parameters
dev- The device structure
source- GP Clock to Select
Returns
0 in case of success, negative code otherwise

◆ adin1320_config_rgmii()

int adin1320_config_rgmii ( struct adin1320_desc * dev,
struct adin1320_rgmii_config rgmii )

Configure RGMII Tx and Rx Delays.

Parameters
dev- The device structure
rgmii- Struct container for RGMII configurations
Returns
0 in case of success, negative code otherwise

◆ adin1320_cu_autoneg()

int adin1320_cu_autoneg ( struct adin1320_desc * dev,
enum adin1320_autoneg_enable enable )

Enable/disable and Reset Autonegotiation for Copper Media.

Parameters
dev- The device structure
enable- Enable and reset autonegotiation, or disable autonegotiation
Returns
0 in case of success, negative code otherwise

◆ adin1320_cu_autoneg_adv_cfg()

int adin1320_cu_autoneg_adv_cfg ( struct adin1320_desc * dev,
uint16_t autoneg_adv_speeds )

Configure Autonegotiation Advertisement Speeds for Copper Media.

Parameters
dev- The device structure
autoneg_adv_speeds- Autoneg Adv speeds to enable (masked with adin1320_cu_speed)
Returns
0 in case of success, negative code otherwise

◆ adin1320_cu_config_interrupt()

int adin1320_cu_config_interrupt ( struct adin1320_desc * dev,
uint32_t callback_events )

Configure the interrupt mask register for copper media.

Parameters
dev- The device structure
callback_events- Bitmask of interrupt events to enable
Returns
0 in case of success, negative code otherwise

◆ adin1320_cu_forced_speed()

int adin1320_cu_forced_speed ( struct adin1320_desc * dev,
enum adin1320_cu_speed val )

Set Force Speed for Copper Media.

Parameters
dev- The device structure
val- Forced speed to select
Returns
0 in case of success, negative code otherwise

◆ adin1320_cu_get_autoneg_adv()

int adin1320_cu_get_autoneg_adv ( struct adin1320_desc * dev,
uint16_t * autoneg_adv_speeds )

Get Enabled Autonegotiation Advertised Speeds for Copper Media.

Parameters
dev- The device structure
autoneg_adv_speeds- Enabled Autoneg Adv speeds (masked with adin1320_cu_speed)
Returns
0 in case of success, negative code otherwise

◆ adin1320_cu_get_mii_status()

int adin1320_cu_get_mii_status ( struct adin1320_desc * dev,
struct adin1320_mii_status * mii_status )

Get Different Status from Copper Media MII Status Register.

Parameters
dev- The device structure
mii_status- Initialized struct container for MII status to be filled
Returns
0 in case of success, negative code otherwise

◆ adin1320_cu_led_ctrl()

int adin1320_cu_led_ctrl ( struct adin1320_desc * dev,
enum adin1320_led_sel led_sel,
uint8_t led_pat,
uint8_t led_pause,
enum adin1320_cu_led_cfg led_cfg,
enum adin1320_led_inv_state led_inv_state )

Configure LED settings for Copper Media.

Parameters
dev- The device structure
led_sel- LED to configure
led_pat- LED pattern selection
led_pause- Pause duration between patterns
led_cfg- LED configuration
led_inv_state- LED invert state
Returns
0 in case of success, negative code otherwise

◆ adin1320_cu_link_cfg()

int adin1320_cu_link_cfg ( struct adin1320_desc * dev,
enum adin1320_link_cfg_enable val )

Enables/Disables the Link.

Parameters
dev- The device structure
val- Enable/disable link
Returns
0 in case of success, negative code otherwise

◆ adin1320_cu_read_irq_status()

int adin1320_cu_read_irq_status ( struct adin1320_desc * dev,
bool * val_irq_pending,
uint16_t * val_irq_status )

Read interrupt status for copper media.

Parameters
dev- The device structure
val_irq_pending- Set to true if any IRQ is pending, false otherwise
val_irq_status- The complete IRQ status register value showing status of all IRQs
Returns
0 in case of success, negative code otherwise

◆ adin1320_cu_resolved_speed()

int adin1320_cu_resolved_speed ( struct adin1320_desc * dev,
enum adin1320_cu_speed * resolved_speed )

Get Resolved Speed for Copper Media.

Parameters
dev- The device structure
resolved_speed- Resolved speed read from HCD_TECH
Returns
0 in case of success, negative code otherwise

◆ adin1320_downspeed_cfg()

int adin1320_downspeed_cfg ( struct adin1320_desc * dev,
uint8_t downspeeds )

Configure Downspeed.

Parameters
dev- The device structure
downspeeds- Downspeeds to enable (masked with adin1320_downspeed)
Returns
0 in case of success, negative code otherwise

◆ adin1320_energy_detect_pwd_cfg()

int adin1320_energy_detect_pwd_cfg ( struct adin1320_desc * dev,
enum adin1320_energy_detect_pwd val )

Energy Detect Power Down mode Config.

Parameters
dev- The device structure
val- Energy power down mode
Returns
0 in case of success, negative code otherwise

◆ adin1320_get_active_media()

int adin1320_get_active_media ( struct adin1320_desc * dev,
enum adin1320_active_media * media )

Get Auto Media Selected as Active Media.

Parameters
dev- The device structure
media- Active media selected
Returns
0 in case of success, negative code otherwise

◆ adin1320_get_device_id()

int adin1320_get_device_id ( struct adin1320_desc * dev,
uint32_t * device_id )

Get Device ID.

Parameters
dev- The device structure
device_id- Combined device ID (upper 16 bits: PHY ID 1, lower 16 bits: PHY ID 2)
Returns
0 in case of success, negative code otherwise

◆ adin1320_get_eee()

int adin1320_get_eee ( struct adin1320_desc * dev,
uint8_t * eee_speeds )

Get Energy Efficient Ethernet Status.

Parameters
dev- The device structure
eee_speeds- Enabled EEE speeds (masked with adin1320_eee_speeds)
Returns
0 in case of success, negative code otherwise

◆ adin1320_get_energy_detect_pwd_stat()

int adin1320_get_energy_detect_pwd_stat ( struct adin1320_desc * dev,
enum adin1320_edpd_stat * val )

Get Energy Detect Power Down mode Status.

Parameters
dev- The device structure
val- Energy Detect Status
Returns
0 in case of success, negative code otherwise

◆ adin1320_get_master_slave_status()

int adin1320_get_master_slave_status ( struct adin1320_desc * dev,
enum adin1320_master_slave_status * val )

Get Master Slave Status.

Parameters
dev- The device structure
val- Master slave status
Returns
0 in case of success, negative code otherwise

◆ adin1320_get_software_powerdown()

int adin1320_get_software_powerdown ( struct adin1320_desc * dev,
enum adin1320_software_powerdown * val )

Get Software Powerdown Status.

Parameters
dev- The device structure
val- Software Powerdown Status
Returns
0 in case of success, negative code otherwise

◆ adin1320_hard_reset()

int adin1320_hard_reset ( struct adin1320_desc * dev)

Perform Device Hard Reset.

Parameters
dev- The device structure
Returns
0 in case of success, negative code otherwise

◆ adin1320_init()

int adin1320_init ( struct adin1320_desc ** dev,
struct adin1320_init_param * param )

Initialize the Device.

Parameters
dev- The device structure
param- Initialization parameter containing information about the device to be initialized.
Returns
0 in case of success, negative code otherwise

◆ adin1320_led_cfg()

int adin1320_led_cfg ( struct adin1320_desc * dev,
enum adin1320_led_output_enable enable_led_output,
enum adin1320_led_pul_str_dur_select pulse_stretch )

Configure general LED settings.

Parameters
dev- The device structure
enable_led_output- Enable/Disable LED output
pulse_stretch- Pulse stretch duration selection
Returns
0 in case of success, negative code otherwise

◆ adin1320_master_slave_config()

int adin1320_master_slave_config ( struct adin1320_desc * dev,
enum adin1320_adv_master_slave_cfg val )

Configure PHY as Master or Slave for 1 Gb speed only.

Parameters
dev- The device structure
val- Config as Master or Slave
Returns
0 in case of success, negative code otherwise

◆ adin1320_mgc_check_cfg()

int adin1320_mgc_check_cfg ( struct adin1320_desc * dev,
uint16_t enabled_checks )

Configure Magic Packet Checks.

Parameters
dev- The device structure
enabled_checks- Magic packet checks to enable (masked with adin1320_mgc_chk_en)
Returns
0 in case of success, negative code otherwise

◆ adin1320_mgc_key_cfg()

int adin1320_mgc_key_cfg ( struct adin1320_desc * dev,
enum adin1320_mgc_key_byte key_byte,
uint8_t key[6] )

Configure Magic Packet SecureOn Key.

Parameters
dev- The device structure
key_byte- Select 6 or 4 byte key
key- Key bytes (array of 6 bytes, only first 4 used for 4-byte key)
Returns
0 in case of success, negative code otherwise

◆ adin1320_mgc_match_cfg()

int adin1320_mgc_match_cfg ( struct adin1320_desc * dev,
uint16_t enabled_matches )

Configure Magic Packet Address Matchings.

Parameters
dev- The device structure
enabled_matches- Magic packet address matchings to enable (masked with adin1320_mgc_match_en)
Returns
0 in case of success, negative code otherwise

◆ adin1320_read()

int adin1320_read ( struct adin1320_desc * dev,
uint32_t addr,
uint16_t * val )

MDIO Read with Clause22 or Clause45.

Parameters
dev- The device structure
addr- Register Address
val- Read value from the register
Returns
0 in case of success, negative code otherwise

◆ adin1320_remove()

int adin1320_remove ( struct adin1320_desc * dev)

Remove Initialization of the Device.

Parameters
dev- The device structure
Returns
0 in case of success, negative code otherwise

◆ adin1320_reset_rmii_fifo()

int adin1320_reset_rmii_fifo ( struct adin1320_desc * dev)

Allows the RMII FIFO to be Reset.

Note
This function places the device in software powerdown. The caller is responsible for calling adin1320_set_software_powerdown(dev, ADIN1320_SOFTWARE_POWERUP) to resume normal operation after the FIFO reset.
Parameters
dev- The device structure
Returns
0 in case of success, negative code otherwise

◆ adin1320_sd_autoneg()

int adin1320_sd_autoneg ( struct adin1320_desc * dev,
enum adin1320_autoneg_enable enable )

Enable/disable and Reset Autonegotiation for SerDes Media.

Parameters
dev- The device structure
enable- Enable and reset autonegotiation, or disable autonegotiation
Returns
0 in case of success, negative code otherwise

◆ adin1320_sd_autoneg_adv_cfg()

int adin1320_sd_autoneg_adv_cfg ( struct adin1320_desc * dev,
uint16_t autoneg_adv_speeds )

Configure Autonegotiation Advertisement Speeds for SerDes Media.

Parameters
dev- The device structure
autoneg_adv_speeds- Autoneg Adv speeds to enable (masked with adin1320_fi_speed)
Returns
0 in case of success, negative code otherwise

◆ adin1320_sd_config_interrupt()

int adin1320_sd_config_interrupt ( struct adin1320_desc * dev,
uint32_t callback_events )

Configure the interrupt mask register for serdes media.

Parameters
dev- The device structure
callback_events- Bitmask of interrupt events to enable
Returns
0 in case of success, negative code otherwise

◆ adin1320_sd_forced_speed()

int adin1320_sd_forced_speed ( struct adin1320_desc * dev,
enum adin1320_sd_speed forced_speed )

Set Force Speed for SerDes Media.

Note
This function places the device in software powerdown. The caller is responsible for calling adin1320_set_software_powerdown(dev, ADIN1320_SOFTWARE_POWERUP) to resume normal operation after the speed is configured.
Parameters
dev- The device structure
forced_speed- Forced speed to select
Returns
0 in case of success, negative code otherwise

◆ adin1320_sd_get_autoneg_adv()

int adin1320_sd_get_autoneg_adv ( struct adin1320_desc * dev,
uint16_t * autoneg_adv_speeds )

Get Enabled Autonegotiation Advertised Speeds for SerDes Media.

Parameters
dev- The device structure
autoneg_adv_speeds- Enabled Autoneg Adv speeds (masked with adin1320_fi_speed)
Returns
0 in case of success, negative code otherwise

◆ adin1320_sd_get_mii_status()

int adin1320_sd_get_mii_status ( struct adin1320_desc * dev,
struct adin1320_mii_status * mii_status )

Get Different Status from SerDes Media MII Status Register.

Parameters
dev- The device structure
mii_status- Initialized struct container for MII status to be filled
Returns
0 in case of success, negative code otherwise

◆ adin1320_sd_led_ctrl()

int adin1320_sd_led_ctrl ( struct adin1320_desc * dev,
enum adin1320_led_sel led_sel,
enum adin1320_sd_led_cfg led_cfg,
enum adin1320_led_inv_state led_inv_state )

Configure LED settings for SerDes Media.

Parameters
dev- The device structure
led_sel- LED to configure
led_cfg- LED configuration
led_inv_state- LED invert state
Returns
0 in case of success, negative code otherwise

◆ adin1320_sd_read_irq_status()

int adin1320_sd_read_irq_status ( struct adin1320_desc * dev,
bool * val_irq_pending,
uint16_t * val_irq_status )

Read interrupt status for serdes media.

Parameters
dev- The device structure
val_irq_pending- Set to true if any IRQ is pending, false otherwise
val_irq_status- The complete IRQ status register value showing status of all IRQs
Returns
0 in case of success, negative code otherwise

◆ adin1320_sd_resolved_speed()

int adin1320_sd_resolved_speed ( struct adin1320_desc * dev,
enum adin1320_sd_speed * resolved_speed )

Get Resolved Speed for SerDes Media.

Parameters
dev- The device structure
resolved_speed- Resolved speed read from SD_LINK_TYPE_CFG
Returns
0 in case of success, negative code otherwise

◆ adin1320_select_mac_interface()

int adin1320_select_mac_interface ( struct adin1320_desc * dev,
enum adin1320_mac_interface val )

MAC Interface Configuration.

Note
This function places the device in software powerdown. The caller is responsible for calling adin1320_set_software_powerdown(dev, ADIN1320_SOFTWARE_POWERUP) to resume normal operation after the interface is configured.
Parameters
dev- The device structure
val- Select MAC Interface
Returns
0 in case of success, negative code otherwise

◆ adin1320_set_downspeed_retries()

int adin1320_set_downspeed_retries ( struct adin1320_desc * dev,
uint16_t val )

Downspeed - Number of retries.

Parameters
dev- The device structure
val- Number of retries
Returns
0 in case of success, negative code otherwise

◆ adin1320_set_eee()

int adin1320_set_eee ( struct adin1320_desc * dev,
uint8_t eee_speeds )

Set Energy Efficient Ethernet speeds.

Parameters
dev- The device structure
eee_speeds- EEE speeds to enable (masked with adin1320_eee_speeds)
Returns
0 in case of success, negative code otherwise

◆ adin1320_set_software_powerdown()

int adin1320_set_software_powerdown ( struct adin1320_desc * dev,
enum adin1320_software_powerdown val )

Enter/exit Software Powerdown.

Parameters
dev- The device structure
val- Enter/exit Software Powerdown
Returns
0 in case of success, negative code otherwise

◆ adin1320_soft_reset()

int adin1320_soft_reset ( struct adin1320_desc * dev,
enum adin1320_soft_reset_option reset_cfg )

Select and Perform Device Reset.

Parameters
dev- The device structure
reset_cfg- Type of soft reset to perform
Returns
0 in case of success, negative code otherwise

◆ adin1320_wol_address()

int adin1320_wol_address ( struct adin1320_desc * dev,
uint8_t mac_address[6] )

Configure Wake-on-LAN Station Address.

Parameters
dev- The device structure
mac_address- Station MAC address (6 bytes)
Returns
0 in case of success, negative code otherwise

◆ adin1320_wol_en_cfg()

int adin1320_wol_en_cfg ( struct adin1320_desc * dev,
enum adin1320_wol_enable enable )

Enable/Disable Wake-on-LAN.

Parameters
dev- The device structure
enable- Enable/disable Wake-on-LAN
Returns
0 in case of success, negative code otherwise

◆ adin1320_wol_sig_cfg()

int adin1320_wol_sig_cfg ( struct adin1320_desc * dev,
enum adin1320_wol_sig signal_type,
uint8_t pulse_length )

Configure Wake-on-LAN Signal Settings.

Parameters
dev- The device structure
signal_type- Select the type of signal for wake-up
pulse_length- Pulse length duration selection
Returns
0 in case of success, negative code otherwise

◆ adin1320_wol_sys_cfg()

int adin1320_wol_sys_cfg ( struct adin1320_desc * dev,
enum adin1320_wol_fi_en enable_fi,
enum adin1320_wol_inv active_signal )

Configure Wake-on-LAN System Settings.

Parameters
dev- The device structure
enable_fi- Enable/disable wake-on-LAN detection from serdes interface
active_signal- Set active signal polarity
Returns
0 in case of success, negative code otherwise

◆ adin1320_wol_wake_cfg()

int adin1320_wol_wake_cfg ( struct adin1320_desc * dev,
enum adin1320_wol_wake_key_enable wake_on_key,
enum adin1320_wol_wake_link_enable wake_on_link_change )

Configure Wake-on-LAN Wake-up Events.

Parameters
dev- The device structure
wake_on_key- Enable/disable wake on Magic Packet key error
wake_on_link_change- Enable/disable wake on link status change
Returns
0 in case of success, negative code otherwise

◆ adin1320_write()

int adin1320_write ( struct adin1320_desc * dev,
uint32_t addr,
uint16_t val )

MDIO Write with Clause22 or Clause45.

Parameters
dev- The device structure
addr- Register Address
val- Value to write in the register
Returns
0 in case of success, negative code otherwise

◆ adin1320_write_bits()

int adin1320_write_bits ( struct adin1320_desc * dev,
uint32_t addr,
uint16_t val,
uint16_t bitmask )

MDIO Write with Clause22 or Clause45 on a Specific Bit.

Parameters
dev- The device structure
addr- Register Address
val- Masked value to write on the bitmask
bitmask- Mask for the bits to be written on
Returns
0 in case of success, negative code otherwise