no-OS
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app_config.h
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1/***************************************************************************/
36#ifndef APP_CONFIG_H_
37#define APP_CONFIG_H_
38
39/******************************************************************************/
40/* UART baud rate for IIO example */
41/******************************************************************************/
42#define UART_BAUDRATE 921600
43
44/******************************************************************************/
45/* SPI bus speeds */
46/******************************************************************************/
47#define AD9528_SPI_SPEED_HZ 10000000u
48#define ADRV903X_SPI_SPEED_HZ 5000000u
49
50/******************************************************************************/
51/* Clock and lane rate configuration */
52/* From profile: ADRV903X_UC101_204B_4T4R1OR_NLS */
53/******************************************************************************/
54#define ADRV903X_DEVICE_CLK_KHZ 245760
55#define ADRV903X_LANE_RATE_KHZ 16220160
56
57/******************************************************************************/
58/* JESD204 framer/deframer parameters */
59/* From profile: ADRV903X_UC101_204B_4T4R1OR_NLS */
60/******************************************************************************/
61#define ADRV903X_TX_JESD_OCTETS_PER_FRAME 4
62#define ADRV903X_TX_JESD_FRAMES_PER_MULTIFRAME 64
63#define ADRV903X_RX_JESD_OCTETS_PER_FRAME 4
64#define ADRV903X_RX_JESD_FRAMES_PER_MULTIFRAME 64
65
66/******************************************************************************/
67/* Firmware and profile file names */
68/* Must match the fopen() mapping in no_os_platform.c */
69/* Source: linux-adi/firmware/ and ADRV9030 customer API package */
70/******************************************************************************/
71#define ADRV903X_CPU_FW_FILE "ADRV9030_FW.bin"
72#define ADRV903X_STREAM_FILE "stream_image.bin"
73#define ADRV903X_PROFILE_FILE "DeviceProfileTest.bin"
74#define ADRV903X_RX_GAIN_TABLE_FILE "RxGainTable.csv"
75
76/******************************************************************************/
77/* Gain table channel mask: bit per RX channel (0xFF = all 8 channels) */
78/******************************************************************************/
79#define ADRV903X_RX_GAIN_TABLE_MASK 0xFF
80
81/******************************************************************************/
82/* ADXCVR and JESD204 configuration */
83/* From profile: ADRV903X_UC101_204B_4T4R1OR_NLS */
84/******************************************************************************/
85#define ADRV903X_ADXCVR_REF_RATE_KHZ 491520 /* AD9528 ch13 REF_CLK0 */
86
87/* TX JESD204 parameters */
88#define ADRV903X_TX_JESD_SUBCLASS 1
89#define ADRV903X_TX_JESD_CONVS_PER_DEVICE 4
90#define ADRV903X_TX_JESD_CONV_RESOLUTION 16
91#define ADRV903X_TX_JESD_BITS_PER_SAMPLE 16
92#define ADRV903X_TX_JESD_HIGH_DENSITY 0
93#define ADRV903X_TX_JESD_CTRL_BITS_PER_SAMPLE 0
94
95/* RX JESD204 parameters */
96#define ADRV903X_RX_JESD_SUBCLASS 1
97
98/******************************************************************************/
99/* AD9528 Clock Synthesizer configuration */
100/* From DTS: zynqmp-zcu102-rev10-adrv9032r-nls.dts */
101/******************************************************************************/
102#define AD9528_VCXO_FREQ_HZ 122880000
103/* PLL1 */
104#define AD9528_PLL1_FEEDBACK_DIV 4
105#define AD9528_PLL1_CHARGE_PUMP_NA 5000
106/* PLL2 */
107#define AD9528_PLL2_VCO_DIV_M1_VAL 4
108#define AD9528_PLL2_R1_DIV_VAL 1
109#define AD9528_PLL2_NDIV_A 3
110#define AD9528_PLL2_NDIV_B 27
111#define AD9528_PLL2_N2_DIV_VAL 4
112#define AD9528_PLL2_CHARGE_PUMP_NA 815000
113/* SYSREF */
114#define AD9528_SYSREF_K_DIV_VAL 512
115/* Output channel dividers */
116#define AD9528_DEV_SYSREF_DIV 4 /* ch0: DEV_SYSREF */
117#define AD9528_DEV_CLK_DIV 4 /* ch1: DEV_CLK → 245.76 MHz */
118#define AD9528_CORE_CLK_DIV 4 /* ch3: CORE_CLK */
119#define AD9528_REF_CLK1_DIV 2 /* ch11: REF_CLK1 */
120#define AD9528_FPGA_SYSREF_DIV 4 /* ch12: FPGA_SYSREF */
121#define AD9528_REF_CLK0_DIV 2 /* ch13: REF_CLK0 */
122
123#endif /* APP_CONFIG_H_ */