app_config.h File Reference

Application configuration parameters for ADRV903X project. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros
#define	UART_BAUDRATE   921600
#define	AD9528_SPI_SPEED_HZ   10000000u
#define	ADRV903X_SPI_SPEED_HZ   5000000u
#define	ADRV903X_DEVICE_CLK_KHZ   245760
#define	ADRV903X_LANE_RATE_KHZ   16220160
#define	ADRV903X_TX_JESD_OCTETS_PER_FRAME   4
#define	ADRV903X_TX_JESD_FRAMES_PER_MULTIFRAME   64
#define	ADRV903X_RX_JESD_OCTETS_PER_FRAME   4
#define	ADRV903X_RX_JESD_FRAMES_PER_MULTIFRAME   64
#define	ADRV903X_CPU_FW_FILE   "ADRV9030_FW.bin"
#define	ADRV903X_STREAM_FILE   "stream_image.bin"
#define	ADRV903X_PROFILE_FILE   "DeviceProfileTest.bin"
#define	ADRV903X_RX_GAIN_TABLE_FILE   "RxGainTable.csv"
#define	ADRV903X_RX_GAIN_TABLE_MASK   0xFF
#define	ADRV903X_ADXCVR_REF_RATE_KHZ   491520 /* AD9528 ch13 REF_CLK0 */
#define	ADRV903X_TX_JESD_SUBCLASS   1
#define	ADRV903X_TX_JESD_CONVS_PER_DEVICE   4
#define	ADRV903X_TX_JESD_CONV_RESOLUTION   16
#define	ADRV903X_TX_JESD_BITS_PER_SAMPLE   16
#define	ADRV903X_TX_JESD_HIGH_DENSITY   0
#define	ADRV903X_TX_JESD_CTRL_BITS_PER_SAMPLE   0
#define	ADRV903X_RX_JESD_SUBCLASS   1
#define	AD9528_VCXO_FREQ_HZ   122880000
#define	AD9528_PLL1_FEEDBACK_DIV   4
#define	AD9528_PLL1_CHARGE_PUMP_NA   5000
#define	AD9528_PLL2_VCO_DIV_M1_VAL   4
#define	AD9528_PLL2_R1_DIV_VAL   1
#define	AD9528_PLL2_NDIV_A   3
#define	AD9528_PLL2_NDIV_B   27
#define	AD9528_PLL2_N2_DIV_VAL   4
#define	AD9528_PLL2_CHARGE_PUMP_NA   815000
#define	AD9528_SYSREF_K_DIV_VAL   512
#define	AD9528_DEV_SYSREF_DIV   4 /* ch0: DEV_SYSREF */
#define	AD9528_DEV_CLK_DIV   4 /* ch1: DEV_CLK → 245.76 MHz */
#define	AD9528_CORE_CLK_DIV   4 /* ch3: CORE_CLK */
#define	AD9528_REF_CLK1_DIV   2 /* ch11: REF_CLK1 */
#define	AD9528_FPGA_SYSREF_DIV   4 /* ch12: FPGA_SYSREF */
#define	AD9528_REF_CLK0_DIV   2 /* ch13: REF_CLK0 */

Detailed Description

Application configuration parameters for ADRV903X project.

Author

Analog Devices Inc.

Copyright 2026(c) Analog Devices, Inc.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

• Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
• Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
• Neither the name of Analog Devices, Inc. nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
• The use of this software may or may not infringe the patent rights of one or more patent holders. This license does not release you from the requirement that you obtain separate licenses from these patent holders to use this software.
• Use of the software either in source or binary form, must be run on or directly connected to an Analog Devices Inc. component.

THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Macro Definition Documentation

AD9528_CORE_CLK_DIV

#define AD9528_CORE_CLK_DIV   4 /* ch3: CORE_CLK */

AD9528_DEV_CLK_DIV

#define AD9528_DEV_CLK_DIV   4 /* ch1: DEV_CLK → 245.76 MHz */

AD9528_DEV_SYSREF_DIV

#define AD9528_DEV_SYSREF_DIV   4 /* ch0: DEV_SYSREF */

AD9528_FPGA_SYSREF_DIV

#define AD9528_FPGA_SYSREF_DIV   4 /* ch12: FPGA_SYSREF */

AD9528_PLL1_CHARGE_PUMP_NA

#define AD9528_PLL1_CHARGE_PUMP_NA   5000

AD9528_PLL1_FEEDBACK_DIV

#define AD9528_PLL1_FEEDBACK_DIV   4

AD9528_PLL2_CHARGE_PUMP_NA

#define AD9528_PLL2_CHARGE_PUMP_NA   815000

AD9528_PLL2_N2_DIV_VAL

#define AD9528_PLL2_N2_DIV_VAL   4

AD9528_PLL2_NDIV_A

#define AD9528_PLL2_NDIV_A   3

AD9528_PLL2_NDIV_B

#define AD9528_PLL2_NDIV_B   27

AD9528_PLL2_R1_DIV_VAL

#define AD9528_PLL2_R1_DIV_VAL   1

AD9528_PLL2_VCO_DIV_M1_VAL

#define AD9528_PLL2_VCO_DIV_M1_VAL   4

AD9528_REF_CLK0_DIV

#define AD9528_REF_CLK0_DIV   2 /* ch13: REF_CLK0 */

AD9528_REF_CLK1_DIV

#define AD9528_REF_CLK1_DIV   2 /* ch11: REF_CLK1 */

AD9528_SPI_SPEED_HZ

#define AD9528_SPI_SPEED_HZ   10000000u

AD9528_SYSREF_K_DIV_VAL

#define AD9528_SYSREF_K_DIV_VAL   512

AD9528_VCXO_FREQ_HZ

#define AD9528_VCXO_FREQ_HZ   122880000

ADRV903X_ADXCVR_REF_RATE_KHZ

#define ADRV903X_ADXCVR_REF_RATE_KHZ   491520 /* AD9528 ch13 REF_CLK0 */

ADRV903X_CPU_FW_FILE

#define ADRV903X_CPU_FW_FILE   "ADRV9030_FW.bin"

ADRV903X_DEVICE_CLK_KHZ

#define ADRV903X_DEVICE_CLK_KHZ   245760

ADRV903X_LANE_RATE_KHZ

#define ADRV903X_LANE_RATE_KHZ   16220160

ADRV903X_PROFILE_FILE

#define ADRV903X_PROFILE_FILE   "DeviceProfileTest.bin"

ADRV903X_RX_GAIN_TABLE_FILE

#define ADRV903X_RX_GAIN_TABLE_FILE   "RxGainTable.csv"

ADRV903X_RX_GAIN_TABLE_MASK

#define ADRV903X_RX_GAIN_TABLE_MASK   0xFF

ADRV903X_RX_JESD_FRAMES_PER_MULTIFRAME

#define ADRV903X_RX_JESD_FRAMES_PER_MULTIFRAME   64

ADRV903X_RX_JESD_OCTETS_PER_FRAME

#define ADRV903X_RX_JESD_OCTETS_PER_FRAME   4

ADRV903X_RX_JESD_SUBCLASS

#define ADRV903X_RX_JESD_SUBCLASS   1

ADRV903X_SPI_SPEED_HZ

#define ADRV903X_SPI_SPEED_HZ   5000000u

ADRV903X_STREAM_FILE

#define ADRV903X_STREAM_FILE   "stream_image.bin"

ADRV903X_TX_JESD_BITS_PER_SAMPLE

#define ADRV903X_TX_JESD_BITS_PER_SAMPLE   16

ADRV903X_TX_JESD_CONV_RESOLUTION

#define ADRV903X_TX_JESD_CONV_RESOLUTION   16

ADRV903X_TX_JESD_CONVS_PER_DEVICE

#define ADRV903X_TX_JESD_CONVS_PER_DEVICE   4

ADRV903X_TX_JESD_CTRL_BITS_PER_SAMPLE

#define ADRV903X_TX_JESD_CTRL_BITS_PER_SAMPLE   0

ADRV903X_TX_JESD_FRAMES_PER_MULTIFRAME

#define ADRV903X_TX_JESD_FRAMES_PER_MULTIFRAME   64

ADRV903X_TX_JESD_HIGH_DENSITY

#define ADRV903X_TX_JESD_HIGH_DENSITY   0

ADRV903X_TX_JESD_OCTETS_PER_FRAME

#define ADRV903X_TX_JESD_OCTETS_PER_FRAME   4

ADRV903X_TX_JESD_SUBCLASS

#define ADRV903X_TX_JESD_SUBCLASS   1

UART_BAUDRATE

#define UART_BAUDRATE   921600