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iio_example.h File Reference

IIO example header for the ADRV903X project. More...

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Functions

int example_main ()
 Basic example main executiont.
 

Detailed Description

IIO example header for the ADRV903X project.

Author
Analog Devices Inc.

Copyright 2026(c) Analog Devices, Inc.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

  • Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
  • Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
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  • The use of this software may or may not infringe the patent rights of one or more patent holders. This license does not release you from the requirement that you obtain separate licenses from these patent holders to use this software.
  • Use of the software either in source or binary form, must be run on or directly connected to an Analog Devices Inc. component.

THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Function Documentation

◆ example_main()

int example_main ( void )

Basic example main executiont.

Returns
ret - Result of the example execution. If working correctly, will execute continuously the while(1) loop and will not return.

Basic example main executiont.

  • 50 ADC readings with delay.
  • Threshold event (non-blocking).
    Returns
    ret - Result of the example execution. If working correctly, will execute continuously the while(1) loop and will not return.
    ret - Result of the example execution. If working correctly, will execute continuously the while(1) loop and will not return.
    Basic example main executiont.
  • 50 ADC readings with delay.
  • Threshold event (non-blocking).
    Returns
    ret - Result of the example execution. If working correctly, will execute continuously the while(1) loop and will not return.
    Basic example main executiont.
Returns
ret - Result of the example execution. If working correctly, will execute continuously the while(1) loop and will not return.

Basic example main executiont.

Returns
ret - Result of the example execution. If working correctly, will execute continuously function iio_app_run and will not return.
ret - Result of the example execution. If working correctly, will execute continuously the while(1) loop and will not return.

Basic example main executiont.

  • 50 ADC readings with delay.
  • Threshold event (non-blocking).
    Returns
    ret - Result of the example execution. If working correctly, will execute continuously the while(1) loop and will not return.
    Basic example main executiont.
Returns
ret - Result of the example execution. If working correctly, will execute continuously the while(1) loop and will not return.

Basic example main executiont.

Returns
ret - Result of the example execution. If working correctly, will execute continuously function iio_app_run and will not return.

Basic example main executiont.

Returns
ret - Result of the example execution.
ret - Result of the example execution. If working correctly, will execute continuously the while(1) loop and will not return.

Basic example main executiont.

  • 50 ADC readings with delay.
  • Threshold event (non-blocking).
    Returns
    ret - Result of the example execution. If working correctly, will execute continuously the while(1) loop and will not return.
    Basic example main executiont.
Returns
ret - Result of the example execution. If working correctly, will execute continuously the while(1) loop and will not return.

Basic example main executiont.

Returns
ret - Result of the example execution. If working correctly, will execute continuously function iio_app_run and will not return.

Basic example main executiont.

Returns
ret - Result of the example execution.

Basic example main executiont.

Brings up the full JESD204 link between the FPGA and the ADRV903X:

  1. AD9528 clock synthesizer setup (DEVCLK + SYSREF)
  2. SYSREF_REQ GPIO configuration
  3. ADXCVR initialization (TX and RX)
  4. AXI JESD204 TX and RX controller initialization
  5. ADRV903X initialization (firmware load up to PreMcsInit_NonBroadcast)
  6. AXI clkgen setup (lane_rate / 66 for JESD204C)
  7. JESD204 topology initialization and FSM start FSM drives: MCS (LINK_SETUP/OPT_SETUP_STAGE1/2) + link enable
  8. JESD204 link status readback
Returns
0 on success, negative error code on failure.

Basic example main executiont.

Brings up the full JESD204 link and demonstrates DMA data transfer:

  1. AD9528 clock synthesizer setup (DEVCLK + SYSREF)
  2. SYSREF_REQ GPIO configuration
  3. ADXCVR initialization (TX and RX)
  4. AXI JESD204 TX and RX controller initialization
  5. ADRV903X initialization (firmware load up to PreMcsInit_NonBroadcast)
  6. AXI clkgen setup (lane_rate / 66 for JESD204C)
  7. AXI DAC core init — load sine wave LUT into TX DMA buffer
  8. AXI ADC core init — reset TPL ADC core + IQ correction
  9. TX and RX DMAC initialization
  10. JESD204 topology initialization and FSM start FSM drives: MCS (LINK_SETUP/OPT_SETUP_STAGE1/2) + link enable
  11. Start TX DMA (continuous sine wave to DAC)
  12. Wait 1 s then capture RX DMA samples
  13. Print buffer addresses for inspection
Returns
0 on success, negative error code on failure.

Basic example main executiont.

Brings up the full JESD204 link and starts the IIO application loop:

  1. AD9528 clock synthesizer setup (DEVCLK + SYSREF)
  2. SYSREF_REQ GPIO configuration
  3. ADXCVR initialization (TX and RX)
  4. AXI JESD204 TX and RX controller initialization
  5. ADRV903X initialization (firmware load up to PreMcsInit_NonBroadcast)
  6. AXI clkgen setup (lane_rate / 66 for JESD204C)
  7. AXI DAC core init — DDS mode (IIO Oscilloscope controls tones)
  8. AXI ADC core init — reset TPL + IQ correction
  9. RX data offload — normal mode + per-capture XFER_LENGTH + RESETN
  10. TX and RX DMAC initialization
  11. JESD204 topology initialization and FSM start
  12. IIO application init and run (blocking)
Returns
0 on success, negative error code on failure.

Basic example main executiont.

Returns
ret - Result of the example execution. If working correctly, will execute continuously function iio_app_run_with_trigs and will not return.
ret - Result of the example execution. If working correctly, will execute continuously the while(1) loop and will not return.

Basic example main executiont.

  • 50 ADC readings with delay.
  • Threshold event (non-blocking).
    Returns
    ret - Result of the example execution. If working correctly, will execute continuously the while(1) loop and will not return.
    Basic example main executiont.
Returns
ret - Result of the example execution. If working correctly, will execute continuously the while(1) loop and will not return.

Basic example main executiont.

Returns
ret - Result of the example execution. If working correctly, will execute continuously function iio_app_run and will not return.

Basic example main executiont.

Returns
ret - Result of the example execution.

Basic example main executiont.

Brings up the full JESD204 link between the FPGA and the ADRV903X:

  1. AD9528 clock synthesizer setup (DEVCLK + SYSREF)
  2. SYSREF_REQ GPIO configuration
  3. ADXCVR initialization (TX and RX)
  4. AXI JESD204 TX and RX controller initialization
  5. ADRV903X initialization (firmware load up to PreMcsInit_NonBroadcast)
  6. AXI clkgen setup (lane_rate / 66 for JESD204C)
  7. JESD204 topology initialization and FSM start FSM drives: MCS (LINK_SETUP/OPT_SETUP_STAGE1/2) + link enable
  8. JESD204 link status readback
Returns
0 on success, negative error code on failure.

Basic example main executiont.

Brings up the full JESD204 link and demonstrates DMA data transfer:

  1. AD9528 clock synthesizer setup (DEVCLK + SYSREF)
  2. SYSREF_REQ GPIO configuration
  3. ADXCVR initialization (TX and RX)
  4. AXI JESD204 TX and RX controller initialization
  5. ADRV903X initialization (firmware load up to PreMcsInit_NonBroadcast)
  6. AXI clkgen setup (lane_rate / 66 for JESD204C)
  7. AXI DAC core init — load sine wave LUT into TX DMA buffer
  8. AXI ADC core init — reset TPL ADC core + IQ correction
  9. TX and RX DMAC initialization
  10. JESD204 topology initialization and FSM start FSM drives: MCS (LINK_SETUP/OPT_SETUP_STAGE1/2) + link enable
  11. Start TX DMA (continuous sine wave to DAC)
  12. Wait 1 s then capture RX DMA samples
  13. Print buffer addresses for inspection
Returns
0 on success, negative error code on failure.

Basic example main executiont.

Brings up the full JESD204 link and starts the IIO application loop:

  1. AD9528 clock synthesizer setup (DEVCLK + SYSREF)
  2. SYSREF_REQ GPIO configuration
  3. ADXCVR initialization (TX and RX)
  4. AXI JESD204 TX and RX controller initialization
  5. ADRV903X initialization (firmware load up to PreMcsInit_NonBroadcast)
  6. AXI clkgen setup (lane_rate / 66 for JESD204C)
  7. AXI DAC core init — DDS mode (IIO Oscilloscope controls tones)
  8. AXI ADC core init — reset TPL + IQ correction
  9. RX data offload — normal mode + per-capture XFER_LENGTH + RESETN
  10. TX and RX DMAC initialization
  11. JESD204 topology initialization and FSM start
  12. IIO application init and run (blocking)
Returns
0 on success, negative error code on failure.

Basic example main executiont.

Returns
ret - Result of the example execution. If working correctly, will execute continuously function iio_app_run_with_trigs and will not return.

Basic example main executiont.

Returns
0 in case of success, negative error code otherwise.
ret - Result of the example execution. If working correctly, will execute continuously the while(1) loop and will not return.

Basic example main executiont.

  • 50 ADC readings with delay.
  • Threshold event (non-blocking).
    Returns
    ret - Result of the example execution. If working correctly, will execute continuously the while(1) loop and will not return.
    Basic example main executiont.
Returns
ret - Result of the example execution. If working correctly, will execute continuously the while(1) loop and will not return.

Basic example main executiont.

Returns
ret - Result of the example execution. If working correctly, will execute continuously function iio_app_run and will not return.

Basic example main executiont.

Returns
ret - Result of the example execution.

Basic example main executiont.

Brings up the full JESD204 link between the FPGA and the ADRV903X:

  1. AD9528 clock synthesizer setup (DEVCLK + SYSREF)
  2. SYSREF_REQ GPIO configuration
  3. ADXCVR initialization (TX and RX)
  4. AXI JESD204 TX and RX controller initialization
  5. ADRV903X initialization (firmware load up to PreMcsInit_NonBroadcast)
  6. AXI clkgen setup (lane_rate / 66 for JESD204C)
  7. JESD204 topology initialization and FSM start FSM drives: MCS (LINK_SETUP/OPT_SETUP_STAGE1/2) + link enable
  8. JESD204 link status readback
Returns
0 on success, negative error code on failure.

Basic example main executiont.

Brings up the full JESD204 link and demonstrates DMA data transfer:

  1. AD9528 clock synthesizer setup (DEVCLK + SYSREF)
  2. SYSREF_REQ GPIO configuration
  3. ADXCVR initialization (TX and RX)
  4. AXI JESD204 TX and RX controller initialization
  5. ADRV903X initialization (firmware load up to PreMcsInit_NonBroadcast)
  6. AXI clkgen setup (lane_rate / 66 for JESD204C)
  7. AXI DAC core init — load sine wave LUT into TX DMA buffer
  8. AXI ADC core init — reset TPL ADC core + IQ correction
  9. TX and RX DMAC initialization
  10. JESD204 topology initialization and FSM start FSM drives: MCS (LINK_SETUP/OPT_SETUP_STAGE1/2) + link enable
  11. Start TX DMA (continuous sine wave to DAC)
  12. Wait 1 s then capture RX DMA samples
  13. Print buffer addresses for inspection
Returns
0 on success, negative error code on failure.

Basic example main executiont.

Brings up the full JESD204 link and starts the IIO application loop:

  1. AD9528 clock synthesizer setup (DEVCLK + SYSREF)
  2. SYSREF_REQ GPIO configuration
  3. ADXCVR initialization (TX and RX)
  4. AXI JESD204 TX and RX controller initialization
  5. ADRV903X initialization (firmware load up to PreMcsInit_NonBroadcast)
  6. AXI clkgen setup (lane_rate / 66 for JESD204C)
  7. AXI DAC core init — DDS mode (IIO Oscilloscope controls tones)
  8. AXI ADC core init — reset TPL + IQ correction
  9. RX data offload — normal mode + per-capture XFER_LENGTH + RESETN
  10. TX and RX DMAC initialization
  11. JESD204 topology initialization and FSM start
  12. IIO application init and run (blocking)
Returns
0 on success, negative error code on failure.

Basic example main executiont.

Returns
ret - Result of the example execution. If working correctly, will execute continuously function iio_app_run_with_trigs and will not return.

Basic example main executiont.

Returns
0 in case of success, negative error code otherwise.

Basic example main executiont.

Returns
0 in case of success, negative error code otherwise

Basic example main executiont.

Returns
ret - Result of the example execution. If working correctly, will turn the status led's on and off in the while loop, set some values in the config 2 register, and then return 0.
ret - Result of the example execution. If working correctly, will execute continuously the while(1) loop and will not return.

Basic example main executiont.

  • 50 ADC readings with delay.
  • Threshold event (non-blocking).
    Returns
    ret - Result of the example execution. If working correctly, will execute continuously the while(1) loop and will not return.
    Basic example main executiont.
Returns
ret - Result of the example execution. If working correctly, will execute continuously the while(1) loop and will not return.

Basic example main executiont.

Returns
ret - Result of the example execution. If working correctly, will execute continuously function iio_app_run and will not return.

Basic example main executiont.

Returns
ret - Result of the example execution.

Basic example main executiont.

Brings up the full JESD204 link between the FPGA and the ADRV903X:

  1. AD9528 clock synthesizer setup (DEVCLK + SYSREF)
  2. SYSREF_REQ GPIO configuration
  3. ADXCVR initialization (TX and RX)
  4. AXI JESD204 TX and RX controller initialization
  5. ADRV903X initialization (firmware load up to PreMcsInit_NonBroadcast)
  6. AXI clkgen setup (lane_rate / 66 for JESD204C)
  7. JESD204 topology initialization and FSM start FSM drives: MCS (LINK_SETUP/OPT_SETUP_STAGE1/2) + link enable
  8. JESD204 link status readback
Returns
0 on success, negative error code on failure.

Basic example main executiont.

Brings up the full JESD204 link and demonstrates DMA data transfer:

  1. AD9528 clock synthesizer setup (DEVCLK + SYSREF)
  2. SYSREF_REQ GPIO configuration
  3. ADXCVR initialization (TX and RX)
  4. AXI JESD204 TX and RX controller initialization
  5. ADRV903X initialization (firmware load up to PreMcsInit_NonBroadcast)
  6. AXI clkgen setup (lane_rate / 66 for JESD204C)
  7. AXI DAC core init — load sine wave LUT into TX DMA buffer
  8. AXI ADC core init — reset TPL ADC core + IQ correction
  9. TX and RX DMAC initialization
  10. JESD204 topology initialization and FSM start FSM drives: MCS (LINK_SETUP/OPT_SETUP_STAGE1/2) + link enable
  11. Start TX DMA (continuous sine wave to DAC)
  12. Wait 1 s then capture RX DMA samples
  13. Print buffer addresses for inspection
Returns
0 on success, negative error code on failure.

Basic example main executiont.

Brings up the full JESD204 link and starts the IIO application loop:

  1. AD9528 clock synthesizer setup (DEVCLK + SYSREF)
  2. SYSREF_REQ GPIO configuration
  3. ADXCVR initialization (TX and RX)
  4. AXI JESD204 TX and RX controller initialization
  5. ADRV903X initialization (firmware load up to PreMcsInit_NonBroadcast)
  6. AXI clkgen setup (lane_rate / 66 for JESD204C)
  7. AXI DAC core init — DDS mode (IIO Oscilloscope controls tones)
  8. AXI ADC core init — reset TPL + IQ correction
  9. RX data offload — normal mode + per-capture XFER_LENGTH + RESETN
  10. TX and RX DMAC initialization
  11. JESD204 topology initialization and FSM start
  12. IIO application init and run (blocking)
Returns
0 on success, negative error code on failure.

Basic example main executiont.

Returns
ret - Result of the example execution. If working correctly, will execute continuously function iio_app_run_with_trigs and will not return.

Basic example main executiont.

Returns
0 in case of success, negative error code otherwise.

Basic example main executiont.

Returns
0 in case of success, negative error code otherwise

Basic example main executiont.

Returns
ret - Result of the example execution. If working correctly, will turn the status led's on and off in the while loop, set some values in the config 2 register, and then return 0.

Basic example main executiont.

Returns
int

IIO descriptor and initialization parameter.

IIO app.

Declaring iio_devices structure

Initializing IIO app init param.

Initializing IIO app.

Running the IIO app (use iio_info or osc in terminal).

Set the threshold voltage to 5V

The comparator output will be available on the GPO_A pin

Set the DAC output on channel C to 5V

Measure input current on channel D

IIO descriptor and initialization parameter.

IIO app.

Declaring iio_devices structure

Initializing IIO app init param.

Initializing IIO app.

Running the IIO app (use iio_info or osc in terminal).

Set the threshold voltage to 5V

The comparator output will be available on the GPO_A pin

Set the DAC output on channel C to 5V

Measure input current on channel D

Initialize the ADC_RDY GPIO and associated IRQ event

Returns
0 if success, negative error code otherwise

IIO descriptor and initialization parameter.

IIO app.

Declaring iio_devices structure

Initializing IIO app init param.

Initializing IIO app.

Running the IIO app (use iio_info or osc in terminal).

Set the threshold voltage to 5V

The comparator output will be available on the GPO_A pin

Set the DAC output on channel C to 5V

Measure input current on channel D

Initialize the ADC_RDY GPIO and associated IRQ event

Returns
0 if success, negative error code otherwise

Negative temperature

Positive temperature

Negative temperature

Positive temperature

IIO descriptor and initialization parameter.

IIO app.

Declaring iio_devices structure

Initializing IIO app init param.

Initializing IIO app.

Running the IIO app (use iio_info or osc in terminal).

Set the threshold voltage to 5V

The comparator output will be available on the GPO_A pin

Set the DAC output on channel C to 5V

Measure input current on channel D

Initialize the ADC_RDY GPIO and associated IRQ event

Returns
0 if success, negative error code otherwise

Negative temperature

Positive temperature

Negative temperature

Positive temperature