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Platform dependent parameters for ADRV903X project (Xilinx). More...
Macros | |
| #define | GPIO_OFFSET 0 |
| #define | GPIO_DEVICE_ID XPAR_GPIO_0_DEVICE_ID |
| #define | SPI_DEVICE_ID XPAR_SPI_0_DEVICE_ID |
| #define | UART_IRQ_ID XPAR_AXI_INTC_AXI_UART_INTERRUPT_INTR |
| #define | DDR_MEM_BASEADDR XPAR_AXI_DDR_CNTRL_BASEADDR |
| #define | RX_JESD_BASEADDR XPAR_AXI_JESD204_RX_0_BASEADDR |
| #define | TX_JESD_BASEADDR XPAR_AXI_JESD204_TX_0_BASEADDR |
| #define | RX_XCVR_BASEADDR XPAR_AXI_ADRV903X_RX_XCVR_BASEADDR |
| #define | TX_XCVR_BASEADDR XPAR_AXI_ADRV903X_TX_XCVR_BASEADDR |
| #define | RX_CORE_BASEADDR XPAR_AD_IP_JESD204_TPL_ADC_0_BASEADDR |
| #define | TX_CORE_BASEADDR XPAR_AD_IP_JESD204_TPL_DAC_0_BASEADDR |
| #define | RX_DMA_BASEADDR XPAR_AXI_ADRV903X_RX_DMA_BASEADDR |
| #define | TX_DMA_BASEADDR XPAR_AXI_ADRV903X_TX_DMA_BASEADDR |
| #define | TX_DATA_OFFLOAD_BASEADDR 0x9C440000UL |
| #define | RX_DATA_OFFLOAD_BASEADDR 0x9C450000UL |
| #define | RX_CLKGEN_BASEADDR XPAR_AXI_ADRV903X_RX_CLKGEN_BASEADDR |
| #define | TX_CLKGEN_BASEADDR XPAR_AXI_ADRV903X_TX_CLKGEN_BASEADDR |
| #define | DAC_BUFFER_SAMPLES 65536 |
| #define | ADC_BUFFER_SAMPLES 32768 |
| #define | ADC_CHANNELS 8 |
| #define | AD9528_CS 1 |
| #define | ADRV903X_CS 0 |
| #define | DAC_GPIO_PLDDR_BYPASS (GPIO_OFFSET + 70) |
| #define | AD9528_RESET_B (GPIO_OFFSET + 69) |
| #define | AD9528_SYSREF_REQ (GPIO_OFFSET + 68) |
| #define | ADRV903X_RESET_B (GPIO_OFFSET + 56) |
Variables | |
| struct xil_spi_init_param | spi_extra |
| struct xil_gpio_init_param | xil_gpio_param |
Platform dependent parameters for ADRV903X project (Xilinx).
Copyright 2026(c) Analog Devices, Inc.
SPDX-License-Identifier: BSD-3-Clause
| #define AD9528_CS 1 |
| #define AD9528_RESET_B (GPIO_OFFSET + 69) |
| #define AD9528_SYSREF_REQ (GPIO_OFFSET + 68) |
| #define ADC_BUFFER_SAMPLES 32768 |
| #define ADC_CHANNELS 8 |
| #define ADRV903X_CS 0 |
| #define ADRV903X_RESET_B (GPIO_OFFSET + 56) |
| #define DAC_BUFFER_SAMPLES 65536 |
| #define DAC_GPIO_PLDDR_BYPASS (GPIO_OFFSET + 70) |
| #define DDR_MEM_BASEADDR XPAR_AXI_DDR_CNTRL_BASEADDR |
| #define GPIO_DEVICE_ID XPAR_GPIO_0_DEVICE_ID |
| #define GPIO_OFFSET 0 |
| #define RX_CLKGEN_BASEADDR XPAR_AXI_ADRV903X_RX_CLKGEN_BASEADDR |
| #define RX_CORE_BASEADDR XPAR_AD_IP_JESD204_TPL_ADC_0_BASEADDR |
| #define RX_DATA_OFFLOAD_BASEADDR 0x9C450000UL |
| #define RX_DMA_BASEADDR XPAR_AXI_ADRV903X_RX_DMA_BASEADDR |
| #define RX_JESD_BASEADDR XPAR_AXI_JESD204_RX_0_BASEADDR |
| #define RX_XCVR_BASEADDR XPAR_AXI_ADRV903X_RX_XCVR_BASEADDR |
| #define SPI_DEVICE_ID XPAR_SPI_0_DEVICE_ID |
| #define TX_CLKGEN_BASEADDR XPAR_AXI_ADRV903X_TX_CLKGEN_BASEADDR |
| #define TX_CORE_BASEADDR XPAR_AD_IP_JESD204_TPL_DAC_0_BASEADDR |
| #define TX_DATA_OFFLOAD_BASEADDR 0x9C440000UL |
| #define TX_DMA_BASEADDR XPAR_AXI_ADRV903X_TX_DMA_BASEADDR |
| #define TX_JESD_BASEADDR XPAR_AXI_JESD204_TX_0_BASEADDR |
| #define TX_XCVR_BASEADDR XPAR_AXI_ADRV903X_TX_XCVR_BASEADDR |
| #define UART_IRQ_ID XPAR_AXI_INTC_AXI_UART_INTERRUPT_INTR |
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