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#define | ADXL367_WRITE_REG 0x0A |
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#define | ADXL367_READ_REG 0x0B |
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#define | ADXL367_READ_FIFO 0x0D |
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#define | ADXL367_I2C_READ 0x01 |
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#define | ADXL367_I2C_WRITE 0x00 |
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#define | ADXL367_REG_DEVID_AD 0x00 |
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#define | ADXL367_REG_DEVID_MST 0x01 |
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#define | ADXL367_REG_PARTID 0x02 |
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#define | ADXL367_REG_REVID 0x03 |
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#define | ADXL367_REG_SERIAL_NUMBER_3 0x04 |
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#define | ADXL367_REG_SERIAL_NUMBER_2 0x05 |
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#define | ADXL367_REG_SERIAL_NUMBER_1 0x06 |
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#define | ADXL367_REG_SERIAL_NUMBER_0 0x07 |
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#define | ADXL367_REG_XDATA 0x08 |
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#define | ADXL367_REG_YDATA 0x09 |
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#define | ADXL367_REG_ZDATA 0x0A |
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#define | ADXL367_REG_STATUS 0x0B |
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#define | ADXL367_REG_FIFO_ENTRIES_L 0x0C |
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#define | ADXL367_REG_FIFO_ENTRIES_H 0x0D |
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#define | ADXL367_REG_XDATA_H 0x0E |
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#define | ADXL367_REG_XDATA_L 0x0F |
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#define | ADXL367_REG_YDATA_H 0x10 |
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#define | ADXL367_REG_YDATA_L 0x11 |
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#define | ADXL367_REG_ZDATA_H 0x12 |
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#define | ADXL367_REG_ZDATA_L 0x13 |
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#define | ADXL367_REG_TEMP_H 0x14 |
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#define | ADXL367_REG_TEMP_L 0x15 |
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#define | ADXL367_REG_EX_ADC_H 0x16 |
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#define | ADXL367_REG_EX_ADC_L 0x17 |
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#define | ADXL367_REG_I2C_FIFO_DATA 0x18 |
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#define | ADXL367_REG_SOFT_RESET 0x1F |
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#define | ADXL367_REG_THRESH_ACT_H 0x20 |
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#define | ADXL367_REG_THRESH_ACT_L 0x21 |
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#define | ADXL367_REG_TIME_ACT 0x22 |
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#define | ADXL367_REG_THRESH_INACT_H 0x23 |
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#define | ADXL367_REG_THRESH_INACT_L 0x24 |
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#define | ADXL367_REG_TIME_INACT_H 0x25 |
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#define | ADXL367_REG_TIME_INACT_L 0x26 |
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#define | ADXL367_REG_ACT_INACT_CTL 0x27 |
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#define | ADXL367_REG_FIFO_CONTROL 0x28 |
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#define | ADXL367_REG_FIFO_SAMPLES 0x29 |
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#define | ADXL367_REG_INTMAP1_LWR 0x2A |
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#define | ADXL367_REG_INTMAP2_LWR 0x2B |
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#define | ADXL367_REG_FILTER_CTL 0x2C |
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#define | ADXL367_REG_POWER_CTL 0x2D |
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#define | ADXL367_REG_SELF_TEST 0x2E |
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#define | ADXL367_REG_TAP_THRESH 0x2F |
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#define | ADXL367_REG_TAP_DUR 0x30 |
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#define | ADXL367_REG_TAP_LATENT 0x31 |
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#define | ADXL367_REG_TAP_WINDOW 0x32 |
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#define | ADXL367_REG_X_OFFSET 0x33 |
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#define | ADXL367_REG_Y_OFFSET 0x34 |
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#define | ADXL367_REG_Z_OFFSET 0x35 |
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#define | ADXL367_REG_X_SENS 0x36 |
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#define | ADXL367_REG_Y_SENS 0x37 |
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#define | ADXL367_REG_Z_SENS 0x38 |
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#define | ADXL367_REG_TIMER_CTL 0x39 |
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#define | ADXL367_REG_INTMAP1_UPPER 0x3A |
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#define | ADXL367_REG_INTMAP2_UPPER 0x3B |
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#define | ADXL367_REG_ADC_CTL 0x3C |
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#define | ADXL367_REG_TEMP_CTL 0x3D |
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#define | ADXL367_REG_TEMP_ADC_OV_TH_H 0x3E |
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#define | ADXL367_REG_TEMP_ADC_OV_TH_L 0x3F |
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#define | ADXL367_REG_TEMP_ADC_UN_TH_H 0x40 |
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#define | ADXL367_REG_TEMP_ADC_UN_TH_L 0x41 |
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#define | ADXL367_REG_TEMP_ADC_TIMER 0x42 |
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#define | ADXL367_REG_AXIS_MASK 0x43 |
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#define | ADXL367_REG_STATUS_COPY 0x44 |
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#define | ADXL367_REG_STATUS_2 0x45 |
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#define | ADXL367_STATUS_ERR_USER_REGS NO_OS_BIT(7) |
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#define | ADXL367_STATUS_AWAKE NO_OS_BIT(6) |
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#define | ADXL367_STATUS_INACT NO_OS_BIT(5) |
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#define | ADXL367_STATUS_ACT NO_OS_BIT(4) |
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#define | ADXL367_STATUS_FIFO_OVERRUN NO_OS_BIT(3) |
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#define | ADXL367_STATUS_FIFO_WATERMARK NO_OS_BIT(2) |
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#define | ADXL367_STATUS_FIFO_RDY NO_OS_BIT(1) |
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#define | ADXL367_STATUS_DATA_RDY NO_OS_BIT(0) |
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#define | ADXL367_THRESH_H 0x7F |
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#define | ADXL367_THRESH_L 0xFC |
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#define | ADXL367_ACT_INACT_CTL_LINKLOOP_MSK NO_OS_GENMASK(5, 4) |
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#define | ADXL367_ACT_INACT_CTL_INACT_EN_MSK NO_OS_GENMASK(3, 2) |
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#define | ADXL367_ACT_INACT_CTL_ACT_EN_MSK NO_OS_GENMASK(1, 0) |
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#define | ADXL367_NO_INACTIVITY_DETECTION_ENABLED 0x0 |
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#define | ADXL367_INACTIVITY_ENABLE 0x1 |
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#define | ADXL367_NO_INACTIVITY_DETECTION_ENABLED_2 0x2 |
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#define | ADXL367_REFERENCED_INACTIVITY_ENABLE 0x3 |
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#define | ADXL367_NO_ACTIVITY_DETECTION 0x0 |
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#define | ADXL367_ACTIVITY_ENABLE 0x1 |
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#define | ADXL367_NO_ACTIVITY_DETECTION_2 0x2 |
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#define | ADXL367_REFERENCED_ACTIVITY_ENABLE 0x3 |
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#define | ADXL367_FIFO_CONTROL_FIFO_CHANNEL_MSK NO_OS_GENMASK(6, 3) |
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#define | ADXL367_FIFO_CONTROL_FIFO_SAMPLES NO_OS_BIT(2) |
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#define | ADXL367_FIFO_CONTROL_FIFO_MODE_MSK NO_OS_GENMASK(1, 0) |
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#define | ADXL367_ALL_AXIS 0x0 |
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#define | ADXL367_X_AXIS 0x1 |
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#define | ADXL367_Y_AXIS 0x2 |
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#define | ADXL367_X_AXIS_2 0x3 |
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#define | ADXL367_ALL_AXIS_TEMP 0x4 |
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#define | ADXL367_X_AXIS_TEMP 0x5 |
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#define | ADXL367_Y_AXIS_TEMP 0x6 |
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#define | ADXL367_Z_AXIS_TEMP 0x7 |
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#define | ADXL367_ALL_AXIS_EXT_ADC 0x8 |
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#define | ADXL367_X_AXIS_EXT_ADC 0x9 |
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#define | ADXL367_Y_AXIS_EXT_ADC 0xA |
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#define | ADXL367_Z_AXIS_EXT_ADC 0xB |
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#define | ADXL367_FIFO_DISABLE 0 |
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#define | ADXL367_FIFO_OLDEST_SAVED 1 |
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#define | ADXL367_FIFO_STREAM 2 |
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#define | ADXL367_FIFO_TRIGGERED 3 |
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#define | ADXL367_INTMAP1_INT_LOW_INT1 NO_OS_BIT(7) |
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#define | ADXL367_INTMAP1_AWAKE_INT1 NO_OS_BIT(6) |
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#define | ADXL367_INTMAP1_INACT_INT1 NO_OS_BIT(5) |
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#define | ADXL367_INTMAP1_ACT_INT1 NO_OS_BIT(4) |
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#define | ADXL367_INTMAP1_FIFO_OVERRUN_INT1 NO_OS_BIT(3) |
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#define | ADXL367_INTMAP1_FIFO_WATERMARK_INT1 NO_OS_BIT(2) |
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#define | ADXL367_INTMAP1_FIFO_RDY_INT1 NO_OS_BIT(1) |
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#define | ADXL367_INTMAP1_DATA_RDY_INT1 NO_OS_BIT(0) |
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#define | ADXL367_INTMAP2_INT_LOW_INT2 NO_OS_BIT(7) |
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#define | ADXL367_INTMAP2_AWAKE_INT2 NO_OS_BIT(6) |
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#define | ADXL367_INTMAP2_INACT_INT2 NO_OS_BIT(5) |
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#define | ADXL367_INTMAP2_ACT_INT2 NO_OS_BIT(4) |
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#define | ADXL367_INTMAP2_FIFO_OVERRUN_INT2 NO_OS_BIT(3) |
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#define | ADXL367_INTMAP2_FIFO_WATERMARK_INT2 NO_OS_BIT(2) |
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#define | ADXL367_INTMAP2_FIFO_RDY_INT2 NO_OS_BIT(1) |
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#define | ADXL367_INTMAP2_DATA_RDY_INT2 NO_OS_BIT(0) |
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#define | ADXL367_FILTER_CTL_RANGE_MSK NO_OS_GENMASK(7, 6) |
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#define | ADXL367_FILTER_I2C_HS NO_OS_BIT(5) |
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#define | ADXL367_FILTER_CTL_RES NO_OS_BIT(4) |
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#define | ADXL367_FILTER_CTL_EXT_SAMPLE NO_OS_BIT(3) |
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#define | ADXL367_FILTER_CTL_ODR_MSK NO_OS_GENMASK(2, 0) |
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#define | ADXL367_RANGE_2G 0 /* +/-2 g */ |
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#define | ADXL367_RANGE_4G 1 /* +/-4 g */ |
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#define | ADXL367_RANGE_8G 2 /* +/-8 g */ |
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#define | ADXL367_POWER_CTL_RES NO_OS_BIT(7) |
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#define | ADXL367_POWER_CTL_EXT_CLK NO_OS_BIT(6) |
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#define | ADXL367_POWER_CTL_LOW_NOISE_MSK NO_OS_GENMASK(5, 4) |
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#define | ADXL367_POWER_CTL_WAKEUP NO_OS_BIT(3) |
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#define | ADXL367_POWER_CTL_AUTOSLEEP NO_OS_BIT(2) |
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#define | ADXL367_POWER_CTL_MEASURE_MSK NO_OS_GENMASK(1, 0) |
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#define | ADXL367_NOISE_MODE_NORMAL 0 |
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#define | ADXL367_NOISE_MODE_LOW 1 |
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#define | ADXL367_NOISE_MODE_ULTRALOW 2 |
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#define | ADXL367_SELF_TEST_ST_FORCE NO_OS_BIT(1) |
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#define | ADXL367_SELF_TEST_ST NO_OS_BIT(0) |
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#define | ADXL367_XYZ_AXIS_OFFSET_MASK 0x1F |
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#define | ADXL367_INTMAPX_UPPER_MASK 0xDF |
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#define | ADXL367_FIFO_8_12BIT_MSK NO_OS_GENMASK(7,6) |
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#define | ADXL367_ADC_INACT_EN NO_OS_BIT(3) |
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#define | ADXL367_ADC_ACT_EN NO_OS_BIT(1) |
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#define | ADXL367_ADC_EN NO_OS_BIT(0) |
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#define | ADXL367_TEMP_INACT_EN NO_OS_BIT(3) |
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#define | ADXL367_TEMP_ACT_EN NO_OS_BIT(1) |
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#define | ADXL367_TEMP_EN NO_OS_BIT(0) |
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#define | ADXL367_DEVICE_AD 0xAD |
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#define | ADXL367_DEVICE_MST 0x1D |
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#define | ADXL367_PART_ID 0xF7 |
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#define | ADXL367_RESET_KEY 0x52 |
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#define | ADXL367_FIFO_X_ID 0x00 |
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#define | ADXL367_FIFO_Y_ID 0x01 |
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#define | ADXL367_FIFO_Z_ID 0x02 |
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#define | ADXL367_FIFO_TEMP_ADC_ID 0x03 |
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#define | ADXL367_ABSOLUTE 0x00 |
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#define | ADXL367_REFERENCED 0x01 |
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#define | ADXL367_ACC_SCALE_FACTOR_MUL 245166ULL |
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#define | ADXL367_ACC_SCALE_FACTOR_DIV 1000000000 |
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#define | ADXL367_TEMP_OFFSET 1185 |
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#define | ADXL367_TEMP_25C 165 |
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#define | ADXL367_TEMP_SCALE 18518518 |
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#define | ADXL367_TEMP_SCALE_DIV 1000000000 |
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#define | ADXL367_SELF_TEST_MIN 90 * 100 / 25 |
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#define | ADXL367_SELF_TEST_MAX 270 * 100 / 25 |
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int | adxl367_init (struct adxl367_dev **device, struct adxl367_init_param init_param) |
| Initializes communication with the device and checks if the part is present by reading the device id. More...
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int | adxl367_remove (struct adxl367_dev *dev) |
| Frees the resources allocated by adxl367_init(). More...
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int | adxl367_self_test (struct adxl367_dev *dev) |
| Performs self test. More...
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int | adxl367_set_register_value (struct adxl367_dev *dev, uint8_t register_value, uint8_t register_address) |
| Writes data into a register. More...
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int | adxl367_get_register_value (struct adxl367_dev *dev, uint8_t *read_data, uint8_t register_address, uint8_t bytes_number) |
| Performs a burst read of a specified number of registers. More...
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int | adxl367_reg_write_msk (struct adxl367_dev *dev, uint8_t reg_addr, uint8_t data, uint8_t mask) |
| Performs a masked write to a register. More...
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int | adxl367_software_reset (struct adxl367_dev *dev) |
| Performs soft-reset. More...
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int | adxl367_set_power_mode (struct adxl367_dev *dev, enum adxl367_op_mode mode) |
| Places the device into standby/measure mode. More...
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int | adxl367_set_range (struct adxl367_dev *dev, enum adxl367_range range) |
| Selects the measurement range. More...
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int | adxl367_set_output_rate (struct adxl367_dev *dev, enum adxl367_odr odr) |
| Selects the Output Data Rate of the device. More...
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int | adxl367_set_offset (struct adxl367_dev *dev, uint16_t x_offset, uint16_t y_offset, uint16_t z_offset) |
| Sets offset for each axis. More...
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int | adxl367_get_raw_xyz (struct adxl367_dev *dev, int16_t *x, int16_t *y, int16_t *z) |
| Reads the 3-axis raw data from the accelerometer. More...
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int | adxl367_get_g_xyz (struct adxl367_dev *dev, struct adxl367_fractional_val *x, struct adxl367_fractional_val *y, struct adxl367_fractional_val *z) |
| Reads the 3-axis raw data from the accelerometer and converts it to g. More...
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int | adxl367_temp_read_en (struct adxl367_dev *dev, bool enable) |
| Enables temperature reading. More...
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int | adxl367_adc_read_en (struct adxl367_dev *dev, bool enable) |
| Enables ADC reading. Disables temperature reading. More...
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int | adxl367_read_raw_temp (struct adxl367_dev *dev, int16_t *raw_temp) |
| Reads the raw temperature of the device. If ADXL367_TEMP_EN is not set, use adxl367_temp_read_en() first to enable temperature reading. More...
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int | adxl367_read_temperature (struct adxl367_dev *dev, struct adxl367_fractional_val *temp) |
| Reads the temperature of the device. More...
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int | adxl367_read_adc (struct adxl367_dev *dev, int16_t *data) |
| Reads ADC data. If ADXL367_ADC_EN is not set, use adxl367_adc_read_en() first to enable ADC reading. More...
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int | adxl367_get_nb_of_fifo_entries (struct adxl367_dev *dev, uint16_t *entr_nb) |
| Reads the number of FIFO entries. More...
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int | adxl367_set_fifo_sample_sets_nb (struct adxl367_dev *dev, uint16_t sets_nb) |
| Sets the number of FIFO sample sets. More...
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int | adxl367_set_fifo_mode (struct adxl367_dev *dev, enum adxl367_fifo_mode mode) |
| Sets FIFO mode. More...
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int | adxl367_set_fifo_read_mode (struct adxl367_dev *dev, enum adxl367_fifo_read_mode read_mode) |
| Sets FIFO read mode. More...
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int | adxl367_set_fifo_format (struct adxl367_dev *dev, enum adxl367_fifo_format format) |
| Sets FIFO format. More...
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int | adxl367_fifo_setup (struct adxl367_dev *dev, enum adxl367_fifo_mode mode, enum adxl367_fifo_format format, uint8_t sets_nb) |
| Configures the FIFO feature. Uses ADXL367_14B_CHID read mode as default. More...
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int | adxl367_read_raw_fifo (struct adxl367_dev *dev, int16_t *x, int16_t *y, int16_t *z, int16_t *temp_adc, uint16_t *entries) |
| Reads all available raw values from FIFO. If, after setting FIFO mode, any of x, y, z, temp or adc aren't selected, assign NULL pointer. Uses ADXL367_14B_CHID read mode as default. More...
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int | adxl367_read_converted_fifo (struct adxl367_dev *dev, struct adxl367_fractional_val *x, struct adxl367_fractional_val *y, struct adxl367_fractional_val *z, struct adxl367_fractional_val *temp_adc, uint16_t *entries) |
| Reads converted values from FIFO. If, after setting FIFO mode, any of x, y, z, temp or adc aren't selected, assign NULL pointer. Uses ADXL367_14B_CHID read mode as default. More...
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int | adxl367_int_map (struct adxl367_dev *dev, struct adxl367_int_map *map, uint8_t pin) |
| Enables specified events to interrupt pin. More...
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int | adxl367_setup_activity_detection (struct adxl367_dev *dev, uint8_t ref_or_abs, uint16_t threshold, uint8_t time) |
| Configures activity detection. More...
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int | adxl367_setup_inactivity_detection (struct adxl367_dev *dev, uint8_t ref_or_abs, uint16_t threshold, uint16_t time) |
| Configures inactivity detection. More...
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Header file of ADXL367 Driver.
- Author
- Andrei Porumb (andre.nosp@m.i.po.nosp@m.rumb@.nosp@m.anal.nosp@m.og.co.nosp@m.m)
Copyright 2022(c) Analog Devices, Inc.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
- Neither the name of Analog Devices, Inc. nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.