|
| #define | ADXL367_WRITE_REG 0x0A |
| |
| #define | ADXL367_READ_REG 0x0B |
| |
| #define | ADXL367_READ_FIFO 0x0D |
| |
| #define | ADXL367_I2C_READ 0x01 |
| |
| #define | ADXL367_I2C_WRITE 0x00 |
| |
| #define | ADXL367_REG_DEVID_AD 0x00 |
| |
| #define | ADXL367_REG_DEVID_MST 0x01 |
| |
| #define | ADXL367_REG_PARTID 0x02 |
| |
| #define | ADXL367_REG_REVID 0x03 |
| |
| #define | ADXL367_REG_SERIAL_NUMBER_3 0x04 |
| |
| #define | ADXL367_REG_SERIAL_NUMBER_2 0x05 |
| |
| #define | ADXL367_REG_SERIAL_NUMBER_1 0x06 |
| |
| #define | ADXL367_REG_SERIAL_NUMBER_0 0x07 |
| |
| #define | ADXL367_REG_XDATA 0x08 |
| |
| #define | ADXL367_REG_YDATA 0x09 |
| |
| #define | ADXL367_REG_ZDATA 0x0A |
| |
| #define | ADXL367_REG_STATUS 0x0B |
| |
| #define | ADXL367_REG_FIFO_ENTRIES_L 0x0C |
| |
| #define | ADXL367_REG_FIFO_ENTRIES_H 0x0D |
| |
| #define | ADXL367_REG_XDATA_H 0x0E |
| |
| #define | ADXL367_REG_XDATA_L 0x0F |
| |
| #define | ADXL367_REG_YDATA_H 0x10 |
| |
| #define | ADXL367_REG_YDATA_L 0x11 |
| |
| #define | ADXL367_REG_ZDATA_H 0x12 |
| |
| #define | ADXL367_REG_ZDATA_L 0x13 |
| |
| #define | ADXL367_REG_TEMP_H 0x14 |
| |
| #define | ADXL367_REG_TEMP_L 0x15 |
| |
| #define | ADXL367_REG_EX_ADC_H 0x16 |
| |
| #define | ADXL367_REG_EX_ADC_L 0x17 |
| |
| #define | ADXL367_REG_I2C_FIFO_DATA 0x18 |
| |
| #define | ADXL367_REG_SOFT_RESET 0x1F |
| |
| #define | ADXL367_REG_THRESH_ACT_H 0x20 |
| |
| #define | ADXL367_REG_THRESH_ACT_L 0x21 |
| |
| #define | ADXL367_REG_TIME_ACT 0x22 |
| |
| #define | ADXL367_REG_THRESH_INACT_H 0x23 |
| |
| #define | ADXL367_REG_THRESH_INACT_L 0x24 |
| |
| #define | ADXL367_REG_TIME_INACT_H 0x25 |
| |
| #define | ADXL367_REG_TIME_INACT_L 0x26 |
| |
| #define | ADXL367_REG_ACT_INACT_CTL 0x27 |
| |
| #define | ADXL367_REG_FIFO_CONTROL 0x28 |
| |
| #define | ADXL367_REG_FIFO_SAMPLES 0x29 |
| |
| #define | ADXL367_REG_INTMAP1_LWR 0x2A |
| |
| #define | ADXL367_REG_INTMAP2_LWR 0x2B |
| |
| #define | ADXL367_REG_FILTER_CTL 0x2C |
| |
| #define | ADXL367_REG_POWER_CTL 0x2D |
| |
| #define | ADXL367_REG_SELF_TEST 0x2E |
| |
| #define | ADXL367_REG_TAP_THRESH 0x2F |
| |
| #define | ADXL367_REG_TAP_DUR 0x30 |
| |
| #define | ADXL367_REG_TAP_LATENT 0x31 |
| |
| #define | ADXL367_REG_TAP_WINDOW 0x32 |
| |
| #define | ADXL367_REG_X_OFFSET 0x33 |
| |
| #define | ADXL367_REG_Y_OFFSET 0x34 |
| |
| #define | ADXL367_REG_Z_OFFSET 0x35 |
| |
| #define | ADXL367_REG_X_SENS 0x36 |
| |
| #define | ADXL367_REG_Y_SENS 0x37 |
| |
| #define | ADXL367_REG_Z_SENS 0x38 |
| |
| #define | ADXL367_REG_TIMER_CTL 0x39 |
| |
| #define | ADXL367_REG_INTMAP1_UPPER 0x3A |
| |
| #define | ADXL367_REG_INTMAP2_UPPER 0x3B |
| |
| #define | ADXL367_REG_ADC_CTL 0x3C |
| |
| #define | ADXL367_REG_TEMP_CTL 0x3D |
| |
| #define | ADXL367_REG_TEMP_ADC_OV_TH_H 0x3E |
| |
| #define | ADXL367_REG_TEMP_ADC_OV_TH_L 0x3F |
| |
| #define | ADXL367_REG_TEMP_ADC_UN_TH_H 0x40 |
| |
| #define | ADXL367_REG_TEMP_ADC_UN_TH_L 0x41 |
| |
| #define | ADXL367_REG_TEMP_ADC_TIMER 0x42 |
| |
| #define | ADXL367_REG_AXIS_MASK 0x43 |
| |
| #define | ADXL367_REG_STATUS_COPY 0x44 |
| |
| #define | ADXL367_REG_STATUS_2 0x45 |
| |
| #define | ADXL367_REG_STATUS_3 0x46 |
| |
| #define | ADXL367_REG_PEDOMETER_STEP_CNT_H 0x47 |
| |
| #define | ADXL367_REG_PEDOMETER_STEP_CNT_L 0x48 |
| |
| #define | ADXL367_REG_PEDOMETER_CTL 0x49 |
| |
| #define | ADXL367_REG_PEDOMETER_THRESH_H 0x4a |
| |
| #define | ADXL367_REG_PEDOMETER_THRESH_L 0x4b |
| |
| #define | ADXL367_REG_PEDOMETER_SENS_H 0x4c |
| |
| #define | ADXL367_REG_PEDOMETER_SENS_L 0x4d |
| |
| #define | ADXL367_STATUS_ERR_USER_REGS NO_OS_BIT(7) |
| |
| #define | ADXL367_STATUS_AWAKE NO_OS_BIT(6) |
| |
| #define | ADXL367_STATUS_INACT NO_OS_BIT(5) |
| |
| #define | ADXL367_STATUS_ACT NO_OS_BIT(4) |
| |
| #define | ADXL367_STATUS_FIFO_OVERRUN NO_OS_BIT(3) |
| |
| #define | ADXL367_STATUS_FIFO_WATERMARK NO_OS_BIT(2) |
| |
| #define | ADXL367_STATUS_FIFO_RDY NO_OS_BIT(1) |
| |
| #define | ADXL367_STATUS_DATA_RDY NO_OS_BIT(0) |
| |
| #define | ADXL367_THRESH_H 0x7F |
| |
| #define | ADXL367_THRESH_L 0xFC |
| |
| #define | ADXL367_ACT_INACT_CTL_REF_READBACK_MSK NO_OS_GENMASK(7, 6) |
| |
| #define | ADXL367_ACT_INACT_CTL_LINKLOOP_MSK NO_OS_GENMASK(5, 4) |
| |
| #define | ADXL367_ACT_INACT_CTL_INACT_EN_MSK NO_OS_GENMASK(3, 2) |
| |
| #define | ADXL367_ACT_INACT_CTL_ACT_EN_MSK NO_OS_GENMASK(1, 0) |
| |
| #define | ADXL367_NO_INACTIVITY_DETECTION_ENABLED 0x0 |
| |
| #define | ADXL367_INACTIVITY_ENABLE 0x1 |
| |
| #define | ADXL367_NO_INACTIVITY_DETECTION_ENABLED_2 0x2 |
| |
| #define | ADXL367_REFERENCED_INACTIVITY_ENABLE 0x3 |
| |
| #define | ADXL367_NO_ACTIVITY_DETECTION 0x0 |
| |
| #define | ADXL367_ACTIVITY_ENABLE 0x1 |
| |
| #define | ADXL367_NO_ACTIVITY_DETECTION_2 0x2 |
| |
| #define | ADXL367_REFERENCED_ACTIVITY_ENABLE 0x3 |
| |
| #define | ADXL367_FIFO_CONTROL_FIFO_CHANNEL_MSK NO_OS_GENMASK(6, 3) |
| |
| #define | ADXL367_FIFO_CONTROL_FIFO_SAMPLES NO_OS_BIT(2) |
| |
| #define | ADXL367_FIFO_CONTROL_FIFO_MODE_MSK NO_OS_GENMASK(1, 0) |
| |
| #define | ADXL367_ALL_AXIS 0x0 |
| |
| #define | ADXL367_X_AXIS 0x1 |
| |
| #define | ADXL367_Y_AXIS 0x2 |
| |
| #define | ADXL367_X_AXIS_2 0x3 |
| |
| #define | ADXL367_ALL_AXIS_TEMP 0x4 |
| |
| #define | ADXL367_X_AXIS_TEMP 0x5 |
| |
| #define | ADXL367_Y_AXIS_TEMP 0x6 |
| |
| #define | ADXL367_Z_AXIS_TEMP 0x7 |
| |
| #define | ADXL367_ALL_AXIS_EXT_ADC 0x8 |
| |
| #define | ADXL367_X_AXIS_EXT_ADC 0x9 |
| |
| #define | ADXL367_Y_AXIS_EXT_ADC 0xA |
| |
| #define | ADXL367_Z_AXIS_EXT_ADC 0xB |
| |
| #define | ADXL367_FIFO_DISABLE 0 |
| |
| #define | ADXL367_FIFO_OLDEST_SAVED 1 |
| |
| #define | ADXL367_FIFO_STREAM 2 |
| |
| #define | ADXL367_FIFO_TRIGGERED 3 |
| |
| #define | ADXL367_INTMAP1_INT_LOW_INT1 NO_OS_BIT(7) |
| |
| #define | ADXL367_INTMAP1_AWAKE_INT1 NO_OS_BIT(6) |
| |
| #define | ADXL367_INTMAP1_INACT_INT1 NO_OS_BIT(5) |
| |
| #define | ADXL367_INTMAP1_ACT_INT1 NO_OS_BIT(4) |
| |
| #define | ADXL367_INTMAP1_FIFO_OVERRUN_INT1 NO_OS_BIT(3) |
| |
| #define | ADXL367_INTMAP1_FIFO_WATERMARK_INT1 NO_OS_BIT(2) |
| |
| #define | ADXL367_INTMAP1_FIFO_RDY_INT1 NO_OS_BIT(1) |
| |
| #define | ADXL367_INTMAP1_DATA_RDY_INT1 NO_OS_BIT(0) |
| |
| #define | ADXL367_INTMAP2_INT_LOW_INT2 NO_OS_BIT(7) |
| |
| #define | ADXL367_INTMAP2_AWAKE_INT2 NO_OS_BIT(6) |
| |
| #define | ADXL367_INTMAP2_INACT_INT2 NO_OS_BIT(5) |
| |
| #define | ADXL367_INTMAP2_ACT_INT2 NO_OS_BIT(4) |
| |
| #define | ADXL367_INTMAP2_FIFO_OVERRUN_INT2 NO_OS_BIT(3) |
| |
| #define | ADXL367_INTMAP2_FIFO_WATERMARK_INT2 NO_OS_BIT(2) |
| |
| #define | ADXL367_INTMAP2_FIFO_RDY_INT2 NO_OS_BIT(1) |
| |
| #define | ADXL367_INTMAP2_DATA_RDY_INT2 NO_OS_BIT(0) |
| |
| #define | ADXL367_FILTER_CTL_RANGE_MSK NO_OS_GENMASK(7, 6) |
| |
| #define | ADXL367_FILTER_I2C_HS NO_OS_BIT(5) |
| |
| #define | ADXL367_FILTER_CTL_RES NO_OS_BIT(4) |
| |
| #define | ADXL367_FILTER_CTL_EXT_SAMPLE NO_OS_BIT(3) |
| |
| #define | ADXL367_FILTER_CTL_ODR_MSK NO_OS_GENMASK(2, 0) |
| |
| #define | ADXL367_RANGE_2G 0 /* +/-2 g */ |
| |
| #define | ADXL367_RANGE_4G 1 /* +/-4 g */ |
| |
| #define | ADXL367_RANGE_8G 2 /* +/-8 g */ |
| |
| #define | ADXL367_POWER_CTL_RES NO_OS_BIT(7) |
| |
| #define | ADXL367_POWER_CTL_EXT_CLK NO_OS_BIT(6) |
| |
| #define | ADXL367_POWER_CTL_LOW_NOISE_MSK NO_OS_GENMASK(5, 4) |
| |
| #define | ADXL367_POWER_CTL_WAKEUP NO_OS_BIT(3) |
| |
| #define | ADXL367_POWER_CTL_AUTOSLEEP NO_OS_BIT(2) |
| |
| #define | ADXL367_POWER_CTL_MEASURE_MSK NO_OS_GENMASK(1, 0) |
| |
| #define | ADXL367_NOISE_MODE_NORMAL 0 |
| |
| #define | ADXL367_NOISE_MODE_LOW 1 |
| |
| #define | ADXL367_NOISE_MODE_ULTRALOW 2 |
| |
| #define | ADXL367_SELF_TEST_ST_FORCE NO_OS_BIT(1) |
| |
| #define | ADXL367_SELF_TEST_ST NO_OS_BIT(0) |
| |
| #define | ADXL367_XYZ_AXIS_OFFSET_MASK 0x1F |
| |
| #define | ADXL367_INTMAPX_UPPER_MASK 0xDF |
| |
| #define | ADXL367_FIFO_8_12BIT_MSK NO_OS_GENMASK(7,6) |
| |
| #define | ADXL367_ADC_INACT_EN NO_OS_BIT(3) |
| |
| #define | ADXL367_ADC_ACT_EN NO_OS_BIT(1) |
| |
| #define | ADXL367_ADC_EN NO_OS_BIT(0) |
| |
| #define | ADXL367_NL_COMP_EN NO_OS_BIT(7) |
| |
| #define | ADXL367_TEMP_INACT_EN NO_OS_BIT(3) |
| |
| #define | ADXL367_TEMP_ACT_EN NO_OS_BIT(1) |
| |
| #define | ADXL367_TEMP_EN NO_OS_BIT(0) |
| |
| #define | ADXL367_PEDOMETER_OVERFLOW_MSK NO_OS_BIT(0) |
| |
| #define | ADXL367_PEDOMETER_RESET_STEPMSK NO_OS_BIT(2) |
| |
| #define | ADXL367_PEDOMETER_RESET_OF_MSK NO_OS_BIT(1) |
| |
| #define | ADXL367_PEDOMETER_EN_MSK NO_OS_BIT(0) |
| |
| #define | ADXL367_DEVICE_AD 0xAD |
| |
| #define | ADXL367_DEVICE_MST 0x1D |
| |
| #define | ADXL367_PART_ID 0xF7 |
| |
| #define | ADXL367_RESET_KEY 0x52 |
| |
| #define | ADXL367_FIFO_X_ID 0x00 |
| |
| #define | ADXL367_FIFO_Y_ID 0x01 |
| |
| #define | ADXL367_FIFO_Z_ID 0x02 |
| |
| #define | ADXL367_FIFO_TEMP_ADC_ID 0x03 |
| |
| #define | ADXL367_ABSOLUTE 0x00 |
| |
| #define | ADXL367_REFERENCED 0x01 |
| |
| #define | ADXL367_ACC_SCALE_FACTOR_MUL 245166ULL |
| |
| #define | ADXL367_ACC_SCALE_FACTOR_DIV 1000000000 |
| |
| #define | ADXL367_TEMP_OFFSET 1185 |
| |
| #define | ADXL367_TEMP_25C 165 |
| |
| #define | ADXL367_TEMP_SCALE 18518518 |
| |
| #define | ADXL367_TEMP_SCALE_DIV 1000000000 |
| |
| #define | ADXL367_SELF_TEST_MIN 90 * 100 / 25 |
| |
| #define | ADXL367_SELF_TEST_MAX 270 * 100 / 25 |
| |
|
| int | adxl367_init (struct adxl367_dev **device, struct adxl367_init_param init_param) |
| | Initializes communication with the device and checks if the part is present by reading the device id.
|
| |
| int | adxl367_remove (struct adxl367_dev *dev) |
| | Frees the resources allocated by adxl367_init().
|
| |
| int | adxl367_self_test (struct adxl367_dev *dev) |
| | Performs self test.
|
| |
| int | adxl367_set_register_value (struct adxl367_dev *dev, uint8_t register_value, uint8_t register_address) |
| | Writes data into a register.
|
| |
| int | adxl367_get_register_value (struct adxl367_dev *dev, uint8_t *read_data, uint8_t register_address, uint8_t bytes_number) |
| | Performs a burst read of a specified number of registers.
|
| |
| int | adxl367_reg_write_msk (struct adxl367_dev *dev, uint8_t reg_addr, uint8_t data, uint8_t mask) |
| | Performs a masked write to a register.
|
| |
| int | adxl367_software_reset (struct adxl367_dev *dev) |
| | Performs soft-reset.
|
| |
| int | adxl367_set_power_mode (struct adxl367_dev *dev, enum adxl367_op_mode mode) |
| | Places the device into standby/measure mode.
|
| |
| int | adxl367_set_range (struct adxl367_dev *dev, enum adxl367_range range) |
| | Selects the measurement range.
|
| |
| int | adxl367_set_output_rate (struct adxl367_dev *dev, enum adxl367_odr odr) |
| | Selects the Output Data Rate of the device.
|
| |
| int | adxl367_set_offset (struct adxl367_dev *dev, uint16_t x_offset, uint16_t y_offset, uint16_t z_offset) |
| | Sets offset for each axis.
|
| |
| int | adxl367_get_raw_xyz (struct adxl367_dev *dev, int16_t *x, int16_t *y, int16_t *z) |
| | Reads the 3-axis raw data from the accelerometer.
|
| |
| int | adxl367_get_g_xyz (struct adxl367_dev *dev, struct adxl367_fractional_val *x, struct adxl367_fractional_val *y, struct adxl367_fractional_val *z) |
| | Reads the 3-axis raw data from the accelerometer and converts it to g.
|
| |
| int | adxl367_temp_read_en (struct adxl367_dev *dev, bool enable) |
| | Enables temperature reading.
|
| |
| int | adxl367_adc_read_en (struct adxl367_dev *dev, bool enable) |
| | Enables ADC reading. Disables temperature reading.
|
| |
| int | adxl367_read_raw_temp (struct adxl367_dev *dev, int16_t *raw_temp) |
| | Reads the raw temperature of the device. If ADXL367_TEMP_EN is not set, use adxl367_temp_read_en() first to enable temperature reading.
|
| |
| int | adxl367_read_temperature (struct adxl367_dev *dev, struct adxl367_fractional_val *temp) |
| | Reads the temperature of the device.
|
| |
| int | adxl367_read_adc (struct adxl367_dev *dev, int16_t *data) |
| | Reads ADC data. If ADXL367_ADC_EN is not set, use adxl367_adc_read_en() first to enable ADC reading.
|
| |
| int | adxl367_get_nb_of_fifo_entries (struct adxl367_dev *dev, uint16_t *entr_nb) |
| | Reads the number of FIFO entries.
|
| |
| int | adxl367_set_fifo_sample_sets_nb (struct adxl367_dev *dev, uint16_t sets_nb) |
| | Sets the number of FIFO sample sets.
|
| |
| int | adxl367_set_fifo_mode (struct adxl367_dev *dev, enum adxl367_fifo_mode mode) |
| | Sets FIFO mode.
|
| |
| int | adxl367_set_fifo_read_mode (struct adxl367_dev *dev, enum adxl367_fifo_read_mode read_mode) |
| | Sets FIFO read mode.
|
| |
| int | adxl367_set_fifo_format (struct adxl367_dev *dev, enum adxl367_fifo_format format) |
| | Sets FIFO format.
|
| |
| int | adxl367_fifo_setup (struct adxl367_dev *dev, enum adxl367_fifo_mode mode, enum adxl367_fifo_format format, uint8_t sets_nb) |
| | Configures the FIFO feature. Uses ADXL367_14B_CHID read mode as default.
|
| |
| int | adxl367_read_raw_fifo (struct adxl367_dev *dev, int16_t *x, int16_t *y, int16_t *z, int16_t *temp_adc, uint16_t *entries) |
| | Reads all available raw values from FIFO. If, after setting FIFO mode, any of x, y, z, temp or adc aren't selected, assign NULL pointer. Uses ADXL367_14B_CHID read mode as default.
|
| |
| int | adxl367_read_converted_fifo (struct adxl367_dev *dev, struct adxl367_fractional_val *x, struct adxl367_fractional_val *y, struct adxl367_fractional_val *z, struct adxl367_fractional_val *temp_adc, uint16_t *entries) |
| | Reads converted values from FIFO. If, after setting FIFO mode, any of x, y, z, temp or adc aren't selected, assign NULL pointer. Uses ADXL367_14B_CHID read mode as default.
|
| |
| int | adxl367_int_map (struct adxl367_dev *dev, struct adxl367_int_map *map, uint8_t pin) |
| | Enables specified events to interrupt pin.
|
| |
| int | adxl367_setup_activity_detection (struct adxl367_dev *dev, uint8_t ref_or_abs, uint16_t threshold, uint8_t time) |
| | Configures activity detection.
|
| |
| int | adxl367_setup_inactivity_detection (struct adxl367_dev *dev, uint8_t ref_or_abs, uint16_t threshold, uint16_t time) |
| | Configures inactivity detection.
|
| |
| int | adxl367_z_nonlinearity_compensation (struct adxl367_dev *dev, bool enable) |
| |
| int | adxl367_reference_readback (struct adxl367_dev *dev, bool inactivity, int16_t *x, int16_t *y, int16_t *z) |
| |
| int | adxl367_pedometer_enable (struct adxl367_dev *dev, bool enable) |
| |
| int | adxl367_pedometer_get_steps (struct adxl367_dev *dev, uint16_t *steps) |
| |
| int | adxl367_pedometer_reset (struct adxl367_dev *dev) |
| |
Header file of ADXL367 Driver.
- Author
- Andrei Porumb (andre.nosp@m.i.po.nosp@m.rumb@.nosp@m.anal.nosp@m.og.co.nosp@m.m)
Copyright 2022(c) Analog Devices, Inc.
SPDX-License-Identifier: BSD-3-Clause