no-OS
Macros | Enumerations | Functions
clk_axi_clkgen.c File Reference

Driver for the Analog Devices AXI CLKGEN. More...

#include "clk_axi_clkgen.h"
#include <stdbool.h>
#include <stdio.h>
#include <stdlib.h>
#include <inttypes.h>
#include "no_os_util.h"
#include "no_os_alloc.h"
#include "no_os_error.h"
#include "no_os_delay.h"
#include "no_os_axi_io.h"
Include dependency graph for clk_axi_clkgen.c:

Macros

#define AXI_PCORE_VER(major, minor, letter)   ((major << 16) | (minor << 8) | letter)
 
#define AXI_PCORE_VER_MAJOR(version)   (version >> 16)
 
#define AXI_PCORE_VER_MINOR(version)   ((version >> 8) & 0xff)
 
#define AXI_PCORE_VER_LETTER(version)   (version & 0xff)
 
#define AXI_REG_VERSION   0x0000
 
#define AXI_VERSION(x)   (((x) & 0xffffffff) << 0)
 
#define AXI_VERSION_IS(x, y, z)   ((x) << 16 | (y) << 8 | (z))
 
#define AXI_VERSION_MAJOR(x)   ((x) >> 16)
 
#define AXI_REG_FPGA_INFO   0x001C
 
#define AXI_REG_FPGA_VOLTAGE   0x0140
 
#define AXI_INFO_FPGA_TECH(info)   ((info) >> 24)
 
#define AXI_INFO_FPGA_FAMILY(info)   (((info) >> 16) & 0xff)
 
#define AXI_INFO_FPGA_SPEED_GRADE(info)   (((info) >> 8) & 0xff)
 
#define AXI_INFO_FPGA_DEV_PACKAGE(info)   ((info) & 0xff)
 
#define AXI_INFO_FPGA_VOLTAGE(val)   ((val) & 0xffff)
 
#define AXI_CLKGEN_REG_RESETN   0x40
 
#define AXI_CLKGEN_MMCM_RESETN   NO_OS_BIT(1)
 
#define AXI_CLKGEN_RESETN   NO_OS_BIT(0)
 
#define AXI_CLKGEN_REG_STATUS   0x5c
 
#define AXI_CLKGEN_STATUS   NO_OS_BIT(0)
 
#define AXI_CLKGEN_REG_DRP_CNTRL   0x70
 
#define AXI_CLKGEN_DRP_CNTRL_SEL   NO_OS_BIT(29)
 
#define AXI_CLKGEN_DRP_CNTRL_READ   NO_OS_BIT(28)
 
#define AXI_CLKGEN_REG_DRP_STATUS   0x74
 
#define AXI_CLKGEN_DRP_STATUS_BUSY   NO_OS_BIT(16)
 
#define MMCM_REG_CLKOUT0_1   0x08
 
#define MMCM_REG_CLKOUT0_2   0x09
 
#define MMCM_REG_CLKOUT1_1   0x0A
 
#define MMCM_REG_CLKOUT1_2   0x0B
 
#define MMCM_REG_CLK_FB1   0x14
 
#define MMCM_REG_CLK_FB2   0x15
 
#define MMCM_REG_CLK_DIV   0x16
 
#define MMCM_REG_LOCK1   0x18
 
#define MMCM_REG_LOCK2   0x19
 
#define MMCM_REG_LOCK3   0x1a
 
#define MMCM_REG_FILTER1   0x4e
 
#define MMCM_REG_FILTER2   0x4f
 

Enumerations

enum  axi_fgpa_technology {
  AXI_FPGA_TECH_UNKNOWN = 0,
  AXI_FPGA_TECH_SERIES7,
  AXI_FPGA_TECH_ULTRASCALE,
  AXI_FPGA_TECH_ULTRASCALE_PLUS,
  AXI_FPGA_TECH_UNKNOWN = 0,
  AXI_FPGA_TECH_SERIES7,
  AXI_FPGA_TECH_ULTRASCALE,
  AXI_FPGA_TECH_ULTRASCALE_PLUS
}
 Enum for technology/generation of the FPGA device. More...
 
enum  axi_fpga_family {
  AXI_FPGA_FAMILY_UNKNOWN = 0,
  AXI_FPGA_FAMILY_ARTIX,
  AXI_FPGA_FAMILY_KINTEX,
  AXI_FPGA_FAMILY_VIRTEX,
  AXI_FPGA_FAMILY_ZYNQ,
  AXI_FPGA_FAMILY_UNKNOWN = 0,
  AXI_FPGA_FAMILY_ARTIX,
  AXI_FPGA_FAMILY_KINTEX,
  AXI_FPGA_FAMILY_VIRTEX,
  AXI_FPGA_FAMILY_ZYNQ
}
 Enum for family variant of the FPGA device. More...
 
enum  axi_fpga_speed_grade {
  AXI_FPGA_SPEED_UNKNOWN = 0,
  AXI_FPGA_SPEED_1 = 10,
  AXI_FPGA_SPEED_1L = 11,
  AXI_FPGA_SPEED_1H = 12,
  AXI_FPGA_SPEED_1HV = 13,
  AXI_FPGA_SPEED_1LV = 14,
  AXI_FPGA_SPEED_2 = 20,
  AXI_FPGA_SPEED_2L = 21,
  AXI_FPGA_SPEED_2LV = 22,
  AXI_FPGA_SPEED_3 = 30,
  AXI_FPGA_SPEED_UNKNOWN = 0,
  AXI_FPGA_SPEED_1 = 10,
  AXI_FPGA_SPEED_1L = 11,
  AXI_FPGA_SPEED_1H = 12,
  AXI_FPGA_SPEED_1HV = 13,
  AXI_FPGA_SPEED_1LV = 14,
  AXI_FPGA_SPEED_2 = 20,
  AXI_FPGA_SPEED_2L = 21,
  AXI_FPGA_SPEED_2LV = 22,
  AXI_FPGA_SPEED_3 = 30
}
 Enum for FPGA's speed-grade. More...
 

Functions

int32_t axi_clkgen_write (struct axi_clkgen *clkgen, uint32_t reg_addr, uint32_t reg_val)
 axi_clkgen_write More...
 
int32_t axi_clkgen_read (struct axi_clkgen *clkgen, uint32_t reg_addr, uint32_t *reg_val)
 axi_clkgen_read More...
 
void axi_clkgen_mmcm_write (struct axi_clkgen *clkgen, uint32_t reg, uint32_t val, uint32_t mask)
 axi_clkgen_mmcm_write More...
 
void axi_clkgen_calc_params (struct axi_clkgen *axi_clkgen, uint32_t fin, uint32_t fout, uint32_t *best_d, uint32_t *best_m, uint32_t *best_dout)
 axi_clkgen_calc_params More...
 
void axi_clkgen_calc_clk_params (uint32_t divider, uint32_t *low, uint32_t *high, uint32_t *edge, uint32_t *nocount)
 axi_clkgen_calc_clk_params More...
 
int32_t axi_clkgen_set_rate (struct axi_clkgen *clkgen, uint32_t rate)
 axi_clkgen_set_rate More...
 
int32_t axi_clkgen_get_rate (struct axi_clkgen *clkgen, uint32_t *rate)
 axi_clkgen_get_rate More...
 
int32_t axi_clkgen_init (struct axi_clkgen **clk, const struct axi_clkgen_init *init)
 axi_clkgen_init More...
 
int32_t axi_clkgen_remove (struct axi_clkgen *clkgen)
 axi_clkgen_remove More...
 

Detailed Description

Driver for the Analog Devices AXI CLKGEN.

Author
DBogdan (drago.nosp@m.s.bo.nosp@m.gdan@.nosp@m.anal.nosp@m.og.co.nosp@m.m)

Copyright 2018(c) Analog Devices, Inc.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

  1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
  2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
  3. Neither the name of Analog Devices, Inc. nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Macro Definition Documentation

◆ AXI_CLKGEN_DRP_CNTRL_READ

#define AXI_CLKGEN_DRP_CNTRL_READ   NO_OS_BIT(28)

◆ AXI_CLKGEN_DRP_CNTRL_SEL

#define AXI_CLKGEN_DRP_CNTRL_SEL   NO_OS_BIT(29)

◆ AXI_CLKGEN_DRP_STATUS_BUSY

#define AXI_CLKGEN_DRP_STATUS_BUSY   NO_OS_BIT(16)

◆ AXI_CLKGEN_MMCM_RESETN

#define AXI_CLKGEN_MMCM_RESETN   NO_OS_BIT(1)

◆ AXI_CLKGEN_REG_DRP_CNTRL

#define AXI_CLKGEN_REG_DRP_CNTRL   0x70

◆ AXI_CLKGEN_REG_DRP_STATUS

#define AXI_CLKGEN_REG_DRP_STATUS   0x74

◆ AXI_CLKGEN_REG_RESETN

#define AXI_CLKGEN_REG_RESETN   0x40

◆ AXI_CLKGEN_REG_STATUS

#define AXI_CLKGEN_REG_STATUS   0x5c

◆ AXI_CLKGEN_RESETN

#define AXI_CLKGEN_RESETN   NO_OS_BIT(0)

◆ AXI_CLKGEN_STATUS

#define AXI_CLKGEN_STATUS   NO_OS_BIT(0)

◆ AXI_INFO_FPGA_DEV_PACKAGE

#define AXI_INFO_FPGA_DEV_PACKAGE (   info)    ((info) & 0xff)

◆ AXI_INFO_FPGA_FAMILY

#define AXI_INFO_FPGA_FAMILY (   info)    (((info) >> 16) & 0xff)

◆ AXI_INFO_FPGA_SPEED_GRADE

#define AXI_INFO_FPGA_SPEED_GRADE (   info)    (((info) >> 8) & 0xff)

◆ AXI_INFO_FPGA_TECH

#define AXI_INFO_FPGA_TECH (   info)    ((info) >> 24)

◆ AXI_INFO_FPGA_VOLTAGE

#define AXI_INFO_FPGA_VOLTAGE (   val)    ((val) & 0xffff)

◆ AXI_PCORE_VER

#define AXI_PCORE_VER (   major,
  minor,
  letter 
)    ((major << 16) | (minor << 8) | letter)

◆ AXI_PCORE_VER_LETTER

#define AXI_PCORE_VER_LETTER (   version)    (version & 0xff)

◆ AXI_PCORE_VER_MAJOR

#define AXI_PCORE_VER_MAJOR (   version)    (version >> 16)

◆ AXI_PCORE_VER_MINOR

#define AXI_PCORE_VER_MINOR (   version)    ((version >> 8) & 0xff)

◆ AXI_REG_FPGA_INFO

#define AXI_REG_FPGA_INFO   0x001C

◆ AXI_REG_FPGA_VOLTAGE

#define AXI_REG_FPGA_VOLTAGE   0x0140

◆ AXI_REG_VERSION

#define AXI_REG_VERSION   0x0000

◆ AXI_VERSION

#define AXI_VERSION (   x)    (((x) & 0xffffffff) << 0)

◆ AXI_VERSION_IS

#define AXI_VERSION_IS (   x,
  y,
  z 
)    ((x) << 16 | (y) << 8 | (z))

◆ AXI_VERSION_MAJOR

#define AXI_VERSION_MAJOR (   x)    ((x) >> 16)

◆ MMCM_REG_CLK_DIV

#define MMCM_REG_CLK_DIV   0x16

◆ MMCM_REG_CLK_FB1

#define MMCM_REG_CLK_FB1   0x14

◆ MMCM_REG_CLK_FB2

#define MMCM_REG_CLK_FB2   0x15

◆ MMCM_REG_CLKOUT0_1

#define MMCM_REG_CLKOUT0_1   0x08

◆ MMCM_REG_CLKOUT0_2

#define MMCM_REG_CLKOUT0_2   0x09

◆ MMCM_REG_CLKOUT1_1

#define MMCM_REG_CLKOUT1_1   0x0A

◆ MMCM_REG_CLKOUT1_2

#define MMCM_REG_CLKOUT1_2   0x0B

◆ MMCM_REG_FILTER1

#define MMCM_REG_FILTER1   0x4e

◆ MMCM_REG_FILTER2

#define MMCM_REG_FILTER2   0x4f

◆ MMCM_REG_LOCK1

#define MMCM_REG_LOCK1   0x18

◆ MMCM_REG_LOCK2

#define MMCM_REG_LOCK2   0x19

◆ MMCM_REG_LOCK3

#define MMCM_REG_LOCK3   0x1a

Enumeration Type Documentation

◆ axi_fgpa_technology

enum axi_fgpa_technology

Enum for technology/generation of the FPGA device.

Enumerator
AXI_FPGA_TECH_UNKNOWN 
AXI_FPGA_TECH_SERIES7 
AXI_FPGA_TECH_ULTRASCALE 
AXI_FPGA_TECH_ULTRASCALE_PLUS 
AXI_FPGA_TECH_UNKNOWN 
AXI_FPGA_TECH_SERIES7 
AXI_FPGA_TECH_ULTRASCALE 
AXI_FPGA_TECH_ULTRASCALE_PLUS 

◆ axi_fpga_family

enum axi_fpga_family

Enum for family variant of the FPGA device.

Enumerator
AXI_FPGA_FAMILY_UNKNOWN 
AXI_FPGA_FAMILY_ARTIX 
AXI_FPGA_FAMILY_KINTEX 
AXI_FPGA_FAMILY_VIRTEX 
AXI_FPGA_FAMILY_ZYNQ 
AXI_FPGA_FAMILY_UNKNOWN 
AXI_FPGA_FAMILY_ARTIX 
AXI_FPGA_FAMILY_KINTEX 
AXI_FPGA_FAMILY_VIRTEX 
AXI_FPGA_FAMILY_ZYNQ 

◆ axi_fpga_speed_grade

enum axi_fpga_speed_grade

Enum for FPGA's speed-grade.

Enumerator
AXI_FPGA_SPEED_UNKNOWN 
AXI_FPGA_SPEED_1 
AXI_FPGA_SPEED_1L 
AXI_FPGA_SPEED_1H 
AXI_FPGA_SPEED_1HV 
AXI_FPGA_SPEED_1LV 
AXI_FPGA_SPEED_2 
AXI_FPGA_SPEED_2L 
AXI_FPGA_SPEED_2LV 
AXI_FPGA_SPEED_3 
AXI_FPGA_SPEED_UNKNOWN 
AXI_FPGA_SPEED_1 
AXI_FPGA_SPEED_1L 
AXI_FPGA_SPEED_1H 
AXI_FPGA_SPEED_1HV 
AXI_FPGA_SPEED_1LV 
AXI_FPGA_SPEED_2 
AXI_FPGA_SPEED_2L 
AXI_FPGA_SPEED_2LV 
AXI_FPGA_SPEED_3 

Function Documentation

◆ axi_clkgen_calc_clk_params()

void axi_clkgen_calc_clk_params ( uint32_t  divider,
uint32_t *  low,
uint32_t *  high,
uint32_t *  edge,
uint32_t *  nocount 
)

axi_clkgen_calc_clk_params

◆ axi_clkgen_calc_params()

void axi_clkgen_calc_params ( struct axi_clkgen *  axi_clkgen,
uint32_t  fin,
uint32_t  fout,
uint32_t *  best_d,
uint32_t *  best_m,
uint32_t *  best_dout 
)

axi_clkgen_calc_params

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◆ axi_clkgen_get_rate()

int32_t axi_clkgen_get_rate ( struct axi_clkgen *  clkgen,
uint32_t *  rate 
)

axi_clkgen_get_rate

◆ axi_clkgen_init()

int32_t axi_clkgen_init ( struct axi_clkgen **  clk,
const struct axi_clkgen_init *  init 
)

axi_clkgen_init

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◆ axi_clkgen_mmcm_write()

void axi_clkgen_mmcm_write ( struct axi_clkgen *  clkgen,
uint32_t  reg,
uint32_t  val,
uint32_t  mask 
)

axi_clkgen_mmcm_write

◆ axi_clkgen_read()

int32_t axi_clkgen_read ( struct axi_clkgen *  clkgen,
uint32_t  reg_addr,
uint32_t *  reg_val 
)

axi_clkgen_read

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◆ axi_clkgen_remove()

int32_t axi_clkgen_remove ( struct axi_clkgen *  clkgen)

axi_clkgen_remove

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◆ axi_clkgen_set_rate()

int32_t axi_clkgen_set_rate ( struct axi_clkgen *  clkgen,
uint32_t  rate 
)

axi_clkgen_set_rate

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◆ axi_clkgen_write()

int32_t axi_clkgen_write ( struct axi_clkgen *  clkgen,
uint32_t  reg_addr,
uint32_t  reg_val 
)

axi_clkgen_write

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