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Macros | Enumerations | Functions
clk_axi_clkgen.c File Reference

Driver for the Analog Devices AXI CLKGEN. More...

#include "clk_axi_clkgen.h"
#include <stdbool.h>
#include <stdio.h>
#include <stdlib.h>
#include <inttypes.h>
#include "no_os_util.h"
#include "no_os_alloc.h"
#include "no_os_error.h"
#include "no_os_delay.h"
#include "no_os_axi_io.h"
Include dependency graph for clk_axi_clkgen.c:

Macros

#define AXI_PCORE_VER(major, minor, letter)
 
#define AXI_PCORE_VER_MAJOR(version)
 
#define AXI_PCORE_VER_MINOR(version)
 
#define AXI_PCORE_VER_LETTER(version)
 
#define AXI_REG_VERSION   0x0000
 
#define AXI_VERSION(x)
 
#define AXI_VERSION_IS(x, y, z)
 
#define AXI_VERSION_MAJOR(x)
 
#define AXI_REG_FPGA_INFO   0x001C
 
#define AXI_REG_FPGA_VOLTAGE   0x0140
 
#define AXI_INFO_FPGA_TECH(info)
 
#define AXI_INFO_FPGA_FAMILY(info)
 
#define AXI_INFO_FPGA_SPEED_GRADE(info)
 
#define AXI_INFO_FPGA_DEV_PACKAGE(info)
 
#define AXI_INFO_FPGA_VOLTAGE(val)
 
#define AXI_CLKGEN_REG_RESETN   0x40
 
#define AXI_CLKGEN_MMCM_RESETN   NO_OS_BIT(1)
 
#define AXI_CLKGEN_RESETN   NO_OS_BIT(0)
 
#define AXI_CLKGEN_REG_STATUS   0x5c
 
#define AXI_CLKGEN_STATUS   NO_OS_BIT(0)
 
#define AXI_CLKGEN_REG_DRP_CNTRL   0x70
 
#define AXI_CLKGEN_DRP_CNTRL_SEL   NO_OS_BIT(29)
 
#define AXI_CLKGEN_DRP_CNTRL_READ   NO_OS_BIT(28)
 
#define AXI_CLKGEN_REG_DRP_STATUS   0x74
 
#define AXI_CLKGEN_DRP_STATUS_BUSY   NO_OS_BIT(16)
 
#define MMCM_REG_CLKOUT0_1   0x08
 
#define MMCM_REG_CLKOUT0_2   0x09
 
#define MMCM_REG_CLKOUT1_1   0x0A
 
#define MMCM_REG_CLKOUT1_2   0x0B
 
#define MMCM_REG_CLK_FB1   0x14
 
#define MMCM_REG_CLK_FB2   0x15
 
#define MMCM_REG_CLK_DIV   0x16
 
#define MMCM_REG_LOCK1   0x18
 
#define MMCM_REG_LOCK2   0x19
 
#define MMCM_REG_LOCK3   0x1a
 
#define MMCM_REG_FILTER1   0x4e
 
#define MMCM_REG_FILTER2   0x4f
 

Enumerations

enum  axi_fgpa_technology {
  AXI_FPGA_TECH_UNKNOWN = 0 ,
  AXI_FPGA_TECH_SERIES7 ,
  AXI_FPGA_TECH_ULTRASCALE ,
  AXI_FPGA_TECH_ULTRASCALE_PLUS
}
 
enum  axi_fpga_family {
  AXI_FPGA_FAMILY_UNKNOWN = 0 ,
  AXI_FPGA_FAMILY_ARTIX ,
  AXI_FPGA_FAMILY_KINTEX ,
  AXI_FPGA_FAMILY_VIRTEX ,
  AXI_FPGA_FAMILY_ZYNQ
}
 
enum  axi_fpga_speed_grade {
  AXI_FPGA_SPEED_UNKNOWN = 0 ,
  AXI_FPGA_SPEED_1 = 10 ,
  AXI_FPGA_SPEED_1L = 11 ,
  AXI_FPGA_SPEED_1H = 12 ,
  AXI_FPGA_SPEED_1HV = 13 ,
  AXI_FPGA_SPEED_1LV = 14 ,
  AXI_FPGA_SPEED_2 = 20 ,
  AXI_FPGA_SPEED_2L = 21 ,
  AXI_FPGA_SPEED_2LV = 22 ,
  AXI_FPGA_SPEED_3 = 30
}
 

Functions

int32_t axi_clkgen_write (struct axi_clkgen *clkgen, uint32_t reg_addr, uint32_t reg_val)
 axi_clkgen_write
 
int32_t axi_clkgen_read (struct axi_clkgen *clkgen, uint32_t reg_addr, uint32_t *reg_val)
 axi_clkgen_read
 
void axi_clkgen_mmcm_write (struct axi_clkgen *clkgen, uint32_t reg, uint32_t val, uint32_t mask)
 axi_clkgen_mmcm_write
 
void axi_clkgen_calc_params (struct axi_clkgen *axi_clkgen, uint32_t fin, uint32_t fout, uint32_t *best_d, uint32_t *best_m, uint32_t *best_dout)
 axi_clkgen_calc_params
 
void axi_clkgen_calc_clk_params (uint32_t divider, uint32_t *low, uint32_t *high, uint32_t *edge, uint32_t *nocount)
 axi_clkgen_calc_clk_params
 
int32_t axi_clkgen_set_rate (struct axi_clkgen *clkgen, uint32_t rate)
 axi_clkgen_set_rate
 
int32_t axi_clkgen_get_rate (struct axi_clkgen *clkgen, uint32_t *rate)
 axi_clkgen_get_rate
 
int32_t axi_clkgen_init (struct axi_clkgen **clk, const struct axi_clkgen_init *init)
 axi_clkgen_init
 
int32_t axi_clkgen_remove (struct axi_clkgen *clkgen)
 axi_clkgen_remove
 

Detailed Description

Driver for the Analog Devices AXI CLKGEN.

Author
DBogdan (drago.nosp@m.s.bo.nosp@m.gdan@.nosp@m.anal.nosp@m.og.co.nosp@m.m)

Copyright 2018(c) Analog Devices, Inc.

SPDX-License-Identifier: BSD-3-Clause

Macro Definition Documentation

◆ AXI_CLKGEN_DRP_CNTRL_READ

#define AXI_CLKGEN_DRP_CNTRL_READ   NO_OS_BIT(28)

◆ AXI_CLKGEN_DRP_CNTRL_SEL

#define AXI_CLKGEN_DRP_CNTRL_SEL   NO_OS_BIT(29)

◆ AXI_CLKGEN_DRP_STATUS_BUSY

#define AXI_CLKGEN_DRP_STATUS_BUSY   NO_OS_BIT(16)

◆ AXI_CLKGEN_MMCM_RESETN

#define AXI_CLKGEN_MMCM_RESETN   NO_OS_BIT(1)

◆ AXI_CLKGEN_REG_DRP_CNTRL

#define AXI_CLKGEN_REG_DRP_CNTRL   0x70

◆ AXI_CLKGEN_REG_DRP_STATUS

#define AXI_CLKGEN_REG_DRP_STATUS   0x74

◆ AXI_CLKGEN_REG_RESETN

#define AXI_CLKGEN_REG_RESETN   0x40

◆ AXI_CLKGEN_REG_STATUS

#define AXI_CLKGEN_REG_STATUS   0x5c

◆ AXI_CLKGEN_RESETN

#define AXI_CLKGEN_RESETN   NO_OS_BIT(0)

◆ AXI_CLKGEN_STATUS

#define AXI_CLKGEN_STATUS   NO_OS_BIT(0)

◆ AXI_INFO_FPGA_DEV_PACKAGE

#define AXI_INFO_FPGA_DEV_PACKAGE ( info)
Value:
((info) & 0xff)

◆ AXI_INFO_FPGA_FAMILY

#define AXI_INFO_FPGA_FAMILY ( info)
Value:
(((info) >> 16) & 0xff)

◆ AXI_INFO_FPGA_SPEED_GRADE

#define AXI_INFO_FPGA_SPEED_GRADE ( info)
Value:
(((info) >> 8) & 0xff)

◆ AXI_INFO_FPGA_TECH

#define AXI_INFO_FPGA_TECH ( info)
Value:
((info) >> 24)

◆ AXI_INFO_FPGA_VOLTAGE

#define AXI_INFO_FPGA_VOLTAGE ( val)
Value:
((val) & 0xffff)

◆ AXI_PCORE_VER

#define AXI_PCORE_VER ( major,
minor,
letter )
Value:
((major << 16) | (minor << 8) | letter)

◆ AXI_PCORE_VER_LETTER

#define AXI_PCORE_VER_LETTER ( version)
Value:
(version & 0xff)

◆ AXI_PCORE_VER_MAJOR

#define AXI_PCORE_VER_MAJOR ( version)
Value:
(version >> 16)

◆ AXI_PCORE_VER_MINOR

#define AXI_PCORE_VER_MINOR ( version)
Value:
((version >> 8) & 0xff)

◆ AXI_REG_FPGA_INFO

#define AXI_REG_FPGA_INFO   0x001C

◆ AXI_REG_FPGA_VOLTAGE

#define AXI_REG_FPGA_VOLTAGE   0x0140

◆ AXI_REG_VERSION

#define AXI_REG_VERSION   0x0000

◆ AXI_VERSION

#define AXI_VERSION ( x)
Value:
(((x) & 0xffffffff) << 0)

◆ AXI_VERSION_IS

#define AXI_VERSION_IS ( x,
y,
z )
Value:
((x) << 16 | (y) << 8 | (z))

◆ AXI_VERSION_MAJOR

#define AXI_VERSION_MAJOR ( x)
Value:
((x) >> 16)

◆ MMCM_REG_CLK_DIV

#define MMCM_REG_CLK_DIV   0x16

◆ MMCM_REG_CLK_FB1

#define MMCM_REG_CLK_FB1   0x14

◆ MMCM_REG_CLK_FB2

#define MMCM_REG_CLK_FB2   0x15

◆ MMCM_REG_CLKOUT0_1

#define MMCM_REG_CLKOUT0_1   0x08

◆ MMCM_REG_CLKOUT0_2

#define MMCM_REG_CLKOUT0_2   0x09

◆ MMCM_REG_CLKOUT1_1

#define MMCM_REG_CLKOUT1_1   0x0A

◆ MMCM_REG_CLKOUT1_2

#define MMCM_REG_CLKOUT1_2   0x0B

◆ MMCM_REG_FILTER1

#define MMCM_REG_FILTER1   0x4e

◆ MMCM_REG_FILTER2

#define MMCM_REG_FILTER2   0x4f

◆ MMCM_REG_LOCK1

#define MMCM_REG_LOCK1   0x18

◆ MMCM_REG_LOCK2

#define MMCM_REG_LOCK2   0x19

◆ MMCM_REG_LOCK3

#define MMCM_REG_LOCK3   0x1a

Enumeration Type Documentation

◆ axi_fgpa_technology

enum axi_fgpa_technology
Enumerator
AXI_FPGA_TECH_UNKNOWN 
AXI_FPGA_TECH_SERIES7 
AXI_FPGA_TECH_ULTRASCALE 
AXI_FPGA_TECH_ULTRASCALE_PLUS 

◆ axi_fpga_family

enum axi_fpga_family
Enumerator
AXI_FPGA_FAMILY_UNKNOWN 
AXI_FPGA_FAMILY_ARTIX 
AXI_FPGA_FAMILY_KINTEX 
AXI_FPGA_FAMILY_VIRTEX 
AXI_FPGA_FAMILY_ZYNQ 

◆ axi_fpga_speed_grade

enum axi_fpga_speed_grade
Enumerator
AXI_FPGA_SPEED_UNKNOWN 
AXI_FPGA_SPEED_1 
AXI_FPGA_SPEED_1L 
AXI_FPGA_SPEED_1H 
AXI_FPGA_SPEED_1HV 
AXI_FPGA_SPEED_1LV 
AXI_FPGA_SPEED_2 
AXI_FPGA_SPEED_2L 
AXI_FPGA_SPEED_2LV 
AXI_FPGA_SPEED_3 

Function Documentation

◆ axi_clkgen_calc_clk_params()

void axi_clkgen_calc_clk_params ( uint32_t divider,
uint32_t * low,
uint32_t * high,
uint32_t * edge,
uint32_t * nocount )

axi_clkgen_calc_clk_params

◆ axi_clkgen_calc_params()

void axi_clkgen_calc_params ( struct axi_clkgen * axi_clkgen,
uint32_t fin,
uint32_t fout,
uint32_t * best_d,
uint32_t * best_m,
uint32_t * best_dout )

axi_clkgen_calc_params

◆ axi_clkgen_get_rate()

int32_t axi_clkgen_get_rate ( struct axi_clkgen * clkgen,
uint32_t * rate )

axi_clkgen_get_rate

◆ axi_clkgen_init()

int32_t axi_clkgen_init ( struct axi_clkgen ** clk,
const struct axi_clkgen_init * init )

axi_clkgen_init

◆ axi_clkgen_mmcm_write()

void axi_clkgen_mmcm_write ( struct axi_clkgen * clkgen,
uint32_t reg,
uint32_t val,
uint32_t mask )

axi_clkgen_mmcm_write

◆ axi_clkgen_read()

int32_t axi_clkgen_read ( struct axi_clkgen * clkgen,
uint32_t reg_addr,
uint32_t * reg_val )

axi_clkgen_read

◆ axi_clkgen_remove()

int32_t axi_clkgen_remove ( struct axi_clkgen * clkgen)

axi_clkgen_remove

◆ axi_clkgen_set_rate()

int32_t axi_clkgen_set_rate ( struct axi_clkgen * clkgen,
uint32_t rate )

axi_clkgen_set_rate

◆ axi_clkgen_write()

int32_t axi_clkgen_write ( struct axi_clkgen * clkgen,
uint32_t reg_addr,
uint32_t reg_val )

axi_clkgen_write