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40 #ifndef _PARAMETERS_H_
41 #define _PARAMETERS_H_
43 #include "app_config.h"
44 #ifdef ALTERA_PLATFORM
47 #include "xparameters.h"
50 #define UART_BAUDRATE 115200
51 #ifndef ALTERA_PLATFORM
53 #define SPI_DEVICE_ID XPAR_SPI_0_DEVICE_ID
54 #define GPIO_DEVICE_ID XPAR_GPIO_0_DEVICE_ID
55 #define UART_DEVICE_ID XPAR_AXI_UART_DEVICE_ID
59 #define ADC_DDR_BASEADDR (XPAR_AXI_DDR_CNTRL_BASEADDR + 0x800000)
60 #define DAC_DDR_BASEADDR (XPAR_AXI_DDR_CNTRL_BASEADDR + 0x900000)
62 #define SPI_DEVICE_ID XPAR_XSPIPS_0_DEVICE_ID
63 #define GPIO_DEVICE_ID XPAR_XGPIOPS_0_DEVICE_ID
64 #define UART_DEVICE_ID XPAR_XUARTPS_0_DEVICE_ID
65 #ifdef XPS_BOARD_ZCU102
66 #define UART_IRQ_ID XPAR_XUARTPS_0_INTR
68 #define UART_IRQ_ID XPAR_XUARTPS_1_INTR
71 #define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
73 #ifdef PLATFORM_ZYNQMP
74 #define GPIO_OFFSET 78
76 #define GPIO_OFFSET 54
79 #define ADC_DDR_BASEADDR (XPAR_DDR_MEM_BASEADDR + 0x800000)
80 #define DAC_DDR_BASEADDR (XPAR_DDR_MEM_BASEADDR + 0x900000)
83 #define RX_CORE_BASEADDR XPAR_AXI_AD9680_TPL_CORE_ADC_TPL_CORE_BASEADDR
84 #define TX_CORE_BASEADDR XPAR_AXI_AD9152_TPL_CORE_DAC_TPL_CORE_BASEADDR
86 #define RX_DMA_BASEADDR XPAR_AXI_AD9680_DMA_BASEADDR
87 #define TX_DMA_BASEADDR XPAR_AXI_AD9152_DMA_BASEADDR
89 #define RX_JESD_BASEADDR XPAR_AXI_AD9680_JESD_RX_AXI_BASEADDR
90 #define TX_JESD_BASEADDR XPAR_AXI_AD9152_JESD_TX_AXI_BASEADDR
92 #define RX_XCVR_BASEADDR XPAR_AXI_AD9680_XCVR_BASEADDR
93 #define TX_XCVR_BASEADDR XPAR_AXI_AD9152_XCVR_BASEADDR
95 #define SPI_DEVICE_ID 0
96 #define GPIO_DEVICE_ID 0
100 #define SPI_BASEADDR SYS_SPI_BASE
101 #define GPIO_BASEADDR SYS_GPIO_OUT_BASE
103 #define ADC_DDR_BASEADDR (SYS_DDR3_CNTRL_ARCH_BASE + 0x800000)
104 #define DAC_DDR_BASEADDR (SYS_DDR3_CNTRL_ARCH_BASE + 0x900000)
106 #define RX_CORE_BASEADDR AXI_AD9680_CORE_BASE
107 #define TX_CORE_BASEADDR AXI_AD9152_CORE_BASE
109 #define RX_DMA_BASEADDR AXI_AD9680_DMA_BASE
110 #define TX_DMA_BASEADDR AXI_AD9152_DMA_BASE
112 #define RX_JESD_BASEADDR AD9680_JESD204_LINK_RECONFIG_BASE
113 #define TX_JESD_BASEADDR AD9152_JESD204_LINK_RECONFIG_BASE
115 #define RX_XCVR_BASEADDR AD9680_JESD204_LINK_MANAGEMENT_BASE
116 #define TX_XCVR_BASEADDR AD9152_JESD204_LINK_MANAGEMENT_BASE
118 #define RX_A10_FPLL_BASEADDR AD9680_JESD204_LINK_PLL_RECONFIG_BASE
119 #define TX_A10_FPLL_BASEADDR AD9152_JESD204_LINK_PLL_RECONFIG_BASE
121 #define TX_PLL_BASEADDR AD9152_JESD204_LANE_PLL_RECONFIG_BASE
122 #define RX_PLL_BASEADDR AD9680_JESD204_LINK_PLL_RECONFIG_BASE
124 #define RX_ADXCFG_0_BASEADDR AVL_ADXCFG_0_RCFG_S1_BASE
125 #define RX_ADXCFG_1_BASEADDR AVL_ADXCFG_1_RCFG_S1_BASE
126 #define RX_ADXCFG_2_BASEADDR AVL_ADXCFG_2_RCFG_S1_BASE
127 #define RX_ADXCFG_3_BASEADDR AVL_ADXCFG_3_RCFG_S1_BASE
128 #define TX_ADXCFG_0_BASEADDR AVL_ADXCFG_0_RCFG_S0_BASE
129 #define TX_ADXCFG_1_BASEADDR AVL_ADXCFG_1_RCFG_S0_BASE
130 #define TX_ADXCFG_2_BASEADDR AVL_ADXCFG_2_RCFG_S0_BASE
131 #define TX_ADXCFG_3_BASEADDR AVL_ADXCFG_3_RCFG_S0_BASE
134 #define GPIO_CLKD_STATUS_0 (GPIO_OFFSET + 32)
135 #define GPIO_CLKD_STATUS_1 (GPIO_OFFSET + 33)
136 #define GPIO_DAC_IRQ (GPIO_OFFSET + 34)
137 #define GPIO_ADC_FDA (GPIO_OFFSET + 35)
138 #define GPIO_ADC_FDB (GPIO_OFFSET + 36)
139 #define GPIO_DAC_TXEN (GPIO_OFFSET + 37)
140 #define GPIO_ADC_PD (GPIO_OFFSET + 38)
141 #define GPIO_TRIG (GPIO_OFFSET + 39)
ad9523_channels
Definition: parameters.h:151
@ ADC_DEVICE_CLK
Definition: parameters.h:156
@ DAC_DEVICE_SYSREF
Definition: parameters.h:153
@ ADC_FPGA_CLK
Definition: parameters.h:158
@ DAC_FPGA_SYSREF
Definition: parameters.h:155
@ DAC_DEVICE_CLK
Definition: parameters.h:152
@ ADC_FPGA_SYSREF
Definition: parameters.h:159
@ DAC_FPGA_CLK
Definition: parameters.h:154
@ ADC_DEVICE_SYSREF
Definition: parameters.h:157