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Definitions specific to xilinx platform used by pulsar-adc project. More...
#include <stdio.h>#include <xparameters.h>#include <xil_cache.h>#include <xilinx_uart.h>#include "axi_pwm_extra.h"#include "spi_engine.h"Macros | |
| #define | UART_DEVICE_ID XPAR_AXI_UART_DEVICE_ID |
| #define | UART_IRQ_ID XPAR_AXI_INTC_AXI_UART_INTERRUPT_INTR |
| #define | UART_EXTRA &uart_extra_ip |
| #define | UART_OPS &xil_uart_ops |
| #define | DCACHE_INVALIDATE Xil_DCacheInvalidateRange |
| #define | UART_BAUDRATE 115200 |
| #define | DMA_BASEADDR XPAR_AXI_PULSAR_ADC_DMA_BASEADDR |
| #define | SPI_ENGINE_BASEADDR XPAR_SPI_PULSAR_ADC_SPI_PULSAR_ADC_AXI_REGMAP_BASEADDR |
| #define | RX_CLKGEN_BASEADDR XPAR_SPI_CLKGEN_BASEADDR |
| #define | AXI_PWMGEN_BASEADDR XPAR_PULSAR_ADC_TRIGGER_GEN_BASEADDR |
| #define | ADC_DDR_BASEADDR (XPAR_DDR_MEM_BASEADDR + 0x800000) |
| #define | SAMPLES_PER_CHANNEL_PLATFORM 2000 |
| #define | MAX_SIZE_BASE_ADDR (SAMPLES_PER_CHANNEL_PLATFORM * sizeof(uint32_t)) |
| #define | SPI_ENG_REF_CLK_FREQ_HZ XPAR_PS7_SPI_0_SPI_CLK_FREQ_HZ |
| #define | REFCLK_RATE 160000000 |
| #define | SPI_DEVICE_ID 0 |
| #define | SPI_OPS &spi_eng_platform_ops |
| #define | SPI_EXTRA &spi_eng_init_param |
| #define | SPI_CS 0 |
| #define | SPI_BAUDRATE 80000000 |
| #define | PWM_OPS &axi_pwm_ops |
| #define | PWM_EXTRA &pulsar_adc_axi_pwm_init |
| #define | PWM_PERIOD 555 |
| #define | PWM_DUTY 10 |
| #define | PULSAR_ADC_ADC_REF_VOLTAGE 5000 |
Variables | |
| struct xil_uart_init_param | uart_extra_ip |
| struct spi_engine_init_param | spi_eng_init_param |
| struct axi_pwm_init_param | pulsar_adc_axi_pwm_init |
Definitions specific to xilinx platform used by pulsar-adc project.
Copyright 2024(c) Analog Devices, Inc.
SPDX-License-Identifier: BSD-3-Clause
| #define ADC_DDR_BASEADDR (XPAR_DDR_MEM_BASEADDR + 0x800000) |
| #define AXI_PWMGEN_BASEADDR XPAR_PULSAR_ADC_TRIGGER_GEN_BASEADDR |
| #define DCACHE_INVALIDATE Xil_DCacheInvalidateRange |
| #define DMA_BASEADDR XPAR_AXI_PULSAR_ADC_DMA_BASEADDR |
| #define MAX_SIZE_BASE_ADDR (SAMPLES_PER_CHANNEL_PLATFORM * sizeof(uint32_t)) |
| #define PULSAR_ADC_ADC_REF_VOLTAGE 5000 |
| #define PWM_DUTY 10 |
| #define PWM_EXTRA &pulsar_adc_axi_pwm_init |
| #define PWM_OPS &axi_pwm_ops |
| #define PWM_PERIOD 555 |
| #define REFCLK_RATE 160000000 |
| #define RX_CLKGEN_BASEADDR XPAR_SPI_CLKGEN_BASEADDR |
| #define SAMPLES_PER_CHANNEL_PLATFORM 2000 |
| #define SPI_BAUDRATE 80000000 |
| #define SPI_CS 0 |
| #define SPI_DEVICE_ID 0 |
| #define SPI_ENG_REF_CLK_FREQ_HZ XPAR_PS7_SPI_0_SPI_CLK_FREQ_HZ |
| #define SPI_ENGINE_BASEADDR XPAR_SPI_PULSAR_ADC_SPI_PULSAR_ADC_AXI_REGMAP_BASEADDR |
| #define SPI_EXTRA &spi_eng_init_param |
| #define SPI_OPS &spi_eng_platform_ops |
| #define UART_BAUDRATE 115200 |
| #define UART_DEVICE_ID XPAR_AXI_UART_DEVICE_ID |
| #define UART_EXTRA &uart_extra_ip |
| #define UART_IRQ_ID XPAR_AXI_INTC_AXI_UART_INTERRUPT_INTR |
| #define UART_OPS &xil_uart_ops |
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