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40 #ifndef __PARAMETERS_H__
41 #define __PARAMETERS_H__
47 #include <xparameters.h>
48 #include <xil_cache.h>
57 #ifdef _XPARAMETERS_PS_H_
58 #define UART_DEVICE_ID XPAR_XUARTPS_0_DEVICE_ID
59 #define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
61 #ifdef XPS_BOARD_ZCU102
62 #define UART_IRQ_ID XPAR_XUARTPS_0_INTR
64 #define UART_IRQ_ID XPAR_XUARTPS_1_INTR
67 #else // _XPARAMETERS_PS_H_
68 #define UART_DEVICE_ID XPAR_AXI_UART_DEVICE_ID
69 #define INTC_DEVICE_ID XPAR_INTC_SINGLE_DEVICE_ID
70 #define UART_IRQ_ID XPAR_AXI_INTC_AXI_UART_INTERRUPT_INTR
71 #endif // _XPARAMETERS_PS_H_
73 #define UART_EXTRA &uart_extra_ip
74 #define UART_OPS &xil_uart_ops
76 #define DCACHE_INVALIDATE Xil_DCacheInvalidateRange
78 #define UART_BAUDRATE 115200
80 #define DMA_BASEADDR XPAR_AXI_PULSAR_ADC_DMA_BASEADDR
81 #define SPI_ENGINE_BASEADDR XPAR_SPI_PULSAR_ADC_SPI_PULSAR_ADC_AXI_REGMAP_BASEADDR
82 #define RX_CLKGEN_BASEADDR XPAR_SPI_CLKGEN_BASEADDR
83 #define AXI_PWMGEN_BASEADDR XPAR_PULSAR_ADC_TRIGGER_GEN_BASEADDR
84 #define ADC_DDR_BASEADDR (XPAR_DDR_MEM_BASEADDR + 0x800000)
86 #define SAMPLES_PER_CHANNEL_PLATFORM 2000
87 #define MAX_SIZE_BASE_ADDR (SAMPLES_PER_CHANNEL_PLATFORM * sizeof(uint32_t))
89 #define SPI_ENG_REF_CLK_FREQ_HZ XPAR_PS7_SPI_0_SPI_CLK_FREQ_HZ
91 #define REFCLK_RATE 160000000
93 #define SPI_DEVICE_ID 0
94 #define SPI_OPS &spi_eng_platform_ops
95 #define SPI_EXTRA &spi_eng_init_param
97 #define SPI_BAUDRATE 80000000
99 #define PWM_OPS &axi_pwm_ops
100 #define PWM_EXTRA &pulsar_adc_axi_pwm_init
101 #define PWM_PERIOD 555
104 #define PULSAR_ADC_ADC_REF_VOLTAGE 5000
Structure holding the initialization parameters for Xilinx platform specific UART parameters.
Definition: xilinx_uart.h:73
Structure holding the initialization parameters for axi PWM.
Definition: axi_pwm_extra.h:56
Structure containing the init parameters needed by the SPI engine.
Definition: spi_engine.h:89