34#ifndef __PARAMETERS_H__
35#define __PARAMETERS_H__
38#include <xparameters.h>
45#ifdef _XPARAMETERS_PS_H_
46#define UART_DEVICE_ID XPAR_XUARTPS_0_DEVICE_ID
47#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
49#ifdef XPS_BOARD_ZCU102
50#define UART_IRQ_ID XPAR_XUARTPS_0_INTR
52#define UART_IRQ_ID XPAR_XUARTPS_1_INTR
56#define UART_DEVICE_ID XPAR_AXI_UART_DEVICE_ID
57#define INTC_DEVICE_ID XPAR_INTC_SINGLE_DEVICE_ID
58#define UART_IRQ_ID XPAR_AXI_INTC_AXI_UART_INTERRUPT_INTR
61#define UART_EXTRA &uart_extra_ip
62#define UART_OPS &xil_uart_ops
64#define DCACHE_INVALIDATE Xil_DCacheInvalidateRange
66#define UART_BAUDRATE 115200
68#define DMA_BASEADDR XPAR_AXI_PULSAR_ADC_DMA_BASEADDR
69#define SPI_ENGINE_BASEADDR XPAR_SPI_PULSAR_ADC_SPI_PULSAR_ADC_AXI_REGMAP_BASEADDR
70#define RX_CLKGEN_BASEADDR XPAR_SPI_CLKGEN_BASEADDR
71#define AXI_PWMGEN_BASEADDR XPAR_PULSAR_ADC_TRIGGER_GEN_BASEADDR
72#define ADC_DDR_BASEADDR (XPAR_DDR_MEM_BASEADDR + 0x800000)
74#define SAMPLES_PER_CHANNEL_PLATFORM 2000
75#define MAX_SIZE_BASE_ADDR (SAMPLES_PER_CHANNEL_PLATFORM * sizeof(uint32_t))
77#define SPI_ENG_REF_CLK_FREQ_HZ XPAR_PS7_SPI_0_SPI_CLK_FREQ_HZ
79#define REFCLK_RATE 160000000
81#define SPI_DEVICE_ID 0
82#define SPI_OPS &spi_eng_platform_ops
83#define SPI_EXTRA &spi_eng_init_param
85#define SPI_BAUDRATE 80000000
87#define PWM_OPS &axi_pwm_ops
88#define PWM_EXTRA &pulsar_adc_axi_pwm_init
92#define PULSAR_ADC_ADC_REF_VOLTAGE 5000
Structure holding the initialization parameters for axi PWM.
Definition axi_pwm_extra.h:44
Structure containing the init parameters needed by the SPI engine.
Definition spi_engine.h:71
Structure holding the initialization parameters for Xilinx platform specific UART parameters.
Definition xilinx_uart.h:56