34#ifndef __PARAMETERS_H__
35#define __PARAMETERS_H__
38#include <xparameters.h>
45#ifdef _XPARAMETERS_PS_H_
46#define UART_DEVICE_ID XPAR_XUARTPS_0_DEVICE_ID
48#ifdef XPS_BOARD_ZCU102
49#define UART_IRQ_ID XPAR_XUARTPS_0_INTR
51#define UART_IRQ_ID XPAR_XUARTPS_1_INTR
55#define UART_DEVICE_ID XPAR_AXI_UART_DEVICE_ID
56#define UART_IRQ_ID XPAR_AXI_INTC_AXI_UART_INTERRUPT_INTR
59#define UART_EXTRA &uart_extra_ip
60#define UART_OPS &xil_uart_ops
62#define DCACHE_INVALIDATE Xil_DCacheInvalidateRange
64#define UART_BAUDRATE 115200
66#define DMA_BASEADDR XPAR_AXI_PULSAR_ADC_DMA_BASEADDR
67#define SPI_ENGINE_BASEADDR XPAR_SPI_PULSAR_ADC_SPI_PULSAR_ADC_AXI_REGMAP_BASEADDR
68#define RX_CLKGEN_BASEADDR XPAR_SPI_CLKGEN_BASEADDR
69#define AXI_PWMGEN_BASEADDR XPAR_PULSAR_ADC_TRIGGER_GEN_BASEADDR
70#define ADC_DDR_BASEADDR (XPAR_DDR_MEM_BASEADDR + 0x800000)
72#define SAMPLES_PER_CHANNEL_PLATFORM 2000
73#define MAX_SIZE_BASE_ADDR (SAMPLES_PER_CHANNEL_PLATFORM * sizeof(uint32_t))
75#define SPI_ENG_REF_CLK_FREQ_HZ XPAR_PS7_SPI_0_SPI_CLK_FREQ_HZ
77#define REFCLK_RATE 160000000
79#define SPI_DEVICE_ID 0
80#define SPI_OPS &spi_eng_platform_ops
81#define SPI_EXTRA &spi_eng_init_param
83#define SPI_BAUDRATE 80000000
85#define PWM_OPS &axi_pwm_ops
86#define PWM_EXTRA &pulsar_adc_axi_pwm_init
90#define PULSAR_ADC_ADC_REF_VOLTAGE 5000
Structure holding the initialization parameters for axi PWM.
Definition axi_pwm_extra.h:44
Structure containing the init parameters needed by the SPI engine.
Definition spi_engine.h:71
Structure holding the initialization parameters for Xilinx platform specific UART parameters.
Definition xilinx_uart.h:56