#include <ad9361_api.h>
Collaboration diagram for AD9361_InitParam:
Member Data Documentation
◆ ad9361_rfpll_ext_recalc_rate
| uint32_t(* AD9361_InitParam::ad9361_rfpll_ext_recalc_rate) (struct refclk_scale *clk_priv) |
◆ ad9361_rfpll_ext_round_rate
| int32_t(* AD9361_InitParam::ad9361_rfpll_ext_round_rate) (struct refclk_scale *clk_priv, uint32_t rate) |
◆ ad9361_rfpll_ext_set_rate
| int32_t(* AD9361_InitParam::ad9361_rfpll_ext_set_rate) (struct refclk_scale *clk_priv, uint32_t rate) |
◆ agc_adc_large_overload_exceed_counter
| uint8_t AD9361_InitParam::agc_adc_large_overload_exceed_counter |
◆ agc_adc_large_overload_inc_steps
| uint8_t AD9361_InitParam::agc_adc_large_overload_inc_steps |
◆ agc_adc_lmt_small_overload_prevent_gain_inc_enable
| uint8_t AD9361_InitParam::agc_adc_lmt_small_overload_prevent_gain_inc_enable |
◆ agc_adc_small_overload_exceed_counter
| uint8_t AD9361_InitParam::agc_adc_small_overload_exceed_counter |
◆ agc_attack_delay_extra_margin_us
| uint32_t AD9361_InitParam::agc_attack_delay_extra_margin_us |
◆ agc_dig_gain_step_size
| uint8_t AD9361_InitParam::agc_dig_gain_step_size |
◆ agc_dig_saturation_exceed_counter
| uint8_t AD9361_InitParam::agc_dig_saturation_exceed_counter |
◆ agc_gain_update_interval_us
| uint32_t AD9361_InitParam::agc_gain_update_interval_us |
◆ agc_immed_gain_change_if_large_adc_overload_enable
| uint8_t AD9361_InitParam::agc_immed_gain_change_if_large_adc_overload_enable |
◆ agc_immed_gain_change_if_large_lmt_overload_enable
| uint8_t AD9361_InitParam::agc_immed_gain_change_if_large_lmt_overload_enable |
◆ agc_inner_thresh_high
| uint8_t AD9361_InitParam::agc_inner_thresh_high |
◆ agc_inner_thresh_high_dec_steps
| uint8_t AD9361_InitParam::agc_inner_thresh_high_dec_steps |
◆ agc_inner_thresh_low
| uint8_t AD9361_InitParam::agc_inner_thresh_low |
◆ agc_inner_thresh_low_inc_steps
| uint8_t AD9361_InitParam::agc_inner_thresh_low_inc_steps |
◆ agc_lmt_overload_large_exceed_counter
| uint8_t AD9361_InitParam::agc_lmt_overload_large_exceed_counter |
◆ agc_lmt_overload_large_inc_steps
| uint8_t AD9361_InitParam::agc_lmt_overload_large_inc_steps |
◆ agc_lmt_overload_small_exceed_counter
| uint8_t AD9361_InitParam::agc_lmt_overload_small_exceed_counter |
◆ agc_outer_thresh_high
| uint8_t AD9361_InitParam::agc_outer_thresh_high |
◆ agc_outer_thresh_high_dec_steps
| uint8_t AD9361_InitParam::agc_outer_thresh_high_dec_steps |
◆ agc_outer_thresh_low
| uint8_t AD9361_InitParam::agc_outer_thresh_low |
◆ agc_outer_thresh_low_inc_steps
| uint8_t AD9361_InitParam::agc_outer_thresh_low_inc_steps |
◆ agc_sync_for_gain_counter_enable
| uint8_t AD9361_InitParam::agc_sync_for_gain_counter_enable |
◆ aux_adc_decimation
| uint32_t AD9361_InitParam::aux_adc_decimation |
◆ aux_adc_rate
| uint32_t AD9361_InitParam::aux_adc_rate |
◆ aux_dac1_active_in_alert_enable
| uint8_t AD9361_InitParam::aux_dac1_active_in_alert_enable |
◆ aux_dac1_active_in_rx_enable
| uint8_t AD9361_InitParam::aux_dac1_active_in_rx_enable |
◆ aux_dac1_active_in_tx_enable
| uint8_t AD9361_InitParam::aux_dac1_active_in_tx_enable |
◆ aux_dac1_default_value_mV
| uint32_t AD9361_InitParam::aux_dac1_default_value_mV |
◆ aux_dac1_rx_delay_us
| uint32_t AD9361_InitParam::aux_dac1_rx_delay_us |
◆ aux_dac1_tx_delay_us
| uint32_t AD9361_InitParam::aux_dac1_tx_delay_us |
◆ aux_dac2_active_in_alert_enable
| uint8_t AD9361_InitParam::aux_dac2_active_in_alert_enable |
◆ aux_dac2_active_in_rx_enable
| uint8_t AD9361_InitParam::aux_dac2_active_in_rx_enable |
◆ aux_dac2_active_in_tx_enable
| uint8_t AD9361_InitParam::aux_dac2_active_in_tx_enable |
◆ aux_dac2_default_value_mV
| uint32_t AD9361_InitParam::aux_dac2_default_value_mV |
◆ aux_dac2_rx_delay_us
| uint32_t AD9361_InitParam::aux_dac2_rx_delay_us |
◆ aux_dac2_tx_delay_us
| uint32_t AD9361_InitParam::aux_dac2_tx_delay_us |
◆ aux_dac_manual_mode_enable
| uint8_t AD9361_InitParam::aux_dac_manual_mode_enable |
◆ clk_output_mode_select
| uint32_t AD9361_InitParam::clk_output_mode_select |
◆ ctrl_outs_enable_mask
| uint8_t AD9361_InitParam::ctrl_outs_enable_mask |
◆ ctrl_outs_index
| uint8_t AD9361_InitParam::ctrl_outs_index |
◆ dc_offset_attenuation_high_range
| uint8_t AD9361_InitParam::dc_offset_attenuation_high_range |
◆ dc_offset_attenuation_low_range
| uint8_t AD9361_InitParam::dc_offset_attenuation_low_range |
◆ dc_offset_count_high_range
| uint8_t AD9361_InitParam::dc_offset_count_high_range |
◆ dc_offset_count_low_range
| uint8_t AD9361_InitParam::dc_offset_count_low_range |
◆ dc_offset_tracking_update_event_mask
| uint8_t AD9361_InitParam::dc_offset_tracking_update_event_mask |
◆ dcxo_coarse_and_fine_tune
| uint32_t AD9361_InitParam::dcxo_coarse_and_fine_tune[2] |
◆ delay_rx_data
| uint32_t AD9361_InitParam::delay_rx_data |
◆ dev_sel
| enum dev_id AD9361_InitParam::dev_sel |
◆ digital_interface_tune_fir_disable
| uint8_t AD9361_InitParam::digital_interface_tune_fir_disable |
◆ digital_interface_tune_skip_mode
| uint8_t AD9361_InitParam::digital_interface_tune_skip_mode |
◆ elna_bypass_loss_mdB
| uint32_t AD9361_InitParam::elna_bypass_loss_mdB |
◆ elna_gain_mdB
| uint32_t AD9361_InitParam::elna_gain_mdB |
◆ elna_gaintable_all_index_enable
| uint8_t AD9361_InitParam::elna_gaintable_all_index_enable |
◆ elna_rx1_gpo0_control_enable
| uint8_t AD9361_InitParam::elna_rx1_gpo0_control_enable |
◆ elna_rx2_gpo1_control_enable
| uint8_t AD9361_InitParam::elna_rx2_gpo1_control_enable |
◆ elna_settling_delay_ns
| uint32_t AD9361_InitParam::elna_settling_delay_ns |
◆ ensm_enable_pin_pulse_mode_enable
| uint8_t AD9361_InitParam::ensm_enable_pin_pulse_mode_enable |
◆ ensm_enable_txnrx_control_enable
| uint8_t AD9361_InitParam::ensm_enable_txnrx_control_enable |
◆ external_rx_lo_enable
| uint8_t AD9361_InitParam::external_rx_lo_enable |
◆ external_tx_lo_enable
| uint8_t AD9361_InitParam::external_tx_lo_enable |
◆ fagc_allow_agc_gain_increase
| uint8_t AD9361_InitParam::fagc_allow_agc_gain_increase |
◆ fagc_dec_pow_measuremnt_duration
| uint32_t AD9361_InitParam::fagc_dec_pow_measuremnt_duration |
◆ fagc_energy_lost_stronger_sig_gain_lock_exit_cnt
| uint32_t AD9361_InitParam::fagc_energy_lost_stronger_sig_gain_lock_exit_cnt |
◆ fagc_final_overrange_count
| uint32_t AD9361_InitParam::fagc_final_overrange_count |
◆ fagc_gain_increase_after_gain_lock_en
| uint8_t AD9361_InitParam::fagc_gain_increase_after_gain_lock_en |
◆ fagc_gain_index_type_after_exit_rx_mode
| uint32_t AD9361_InitParam::fagc_gain_index_type_after_exit_rx_mode |
◆ fagc_large_overload_inc_steps
| uint32_t AD9361_InitParam::fagc_large_overload_inc_steps |
◆ fagc_lmt_final_settling_steps
| uint32_t AD9361_InitParam::fagc_lmt_final_settling_steps |
◆ fagc_lock_level_gain_increase_upper_limit
| uint32_t AD9361_InitParam::fagc_lock_level_gain_increase_upper_limit |
◆ fagc_lock_level_lmt_gain_increase_en
| uint8_t AD9361_InitParam::fagc_lock_level_lmt_gain_increase_en |
◆ fagc_lp_thresh_increment_steps
| uint32_t AD9361_InitParam::fagc_lp_thresh_increment_steps |
◆ fagc_lp_thresh_increment_time
| uint32_t AD9361_InitParam::fagc_lp_thresh_increment_time |
◆ fagc_lpf_final_settling_steps
| uint32_t AD9361_InitParam::fagc_lpf_final_settling_steps |
◆ fagc_optimized_gain_offset
| uint32_t AD9361_InitParam::fagc_optimized_gain_offset |
◆ fagc_power_measurement_duration_in_state5
| uint32_t AD9361_InitParam::fagc_power_measurement_duration_in_state5 |
◆ fagc_rst_gla_en_agc_pulled_high_en
| uint8_t AD9361_InitParam::fagc_rst_gla_en_agc_pulled_high_en |
◆ fagc_rst_gla_engergy_lost_goto_optim_gain_en
| uint8_t AD9361_InitParam::fagc_rst_gla_engergy_lost_goto_optim_gain_en |
◆ fagc_rst_gla_engergy_lost_sig_thresh_below_ll
| uint32_t AD9361_InitParam::fagc_rst_gla_engergy_lost_sig_thresh_below_ll |
◆ fagc_rst_gla_engergy_lost_sig_thresh_exceeded_en
| uint8_t AD9361_InitParam::fagc_rst_gla_engergy_lost_sig_thresh_exceeded_en |
◆ fagc_rst_gla_if_en_agc_pulled_high_mode
| uint32_t AD9361_InitParam::fagc_rst_gla_if_en_agc_pulled_high_mode |
◆ fagc_rst_gla_large_adc_overload_en
| uint8_t AD9361_InitParam::fagc_rst_gla_large_adc_overload_en |
◆ fagc_rst_gla_large_lmt_overload_en
| uint8_t AD9361_InitParam::fagc_rst_gla_large_lmt_overload_en |
◆ fagc_rst_gla_stronger_sig_thresh_above_ll
| uint32_t AD9361_InitParam::fagc_rst_gla_stronger_sig_thresh_above_ll |
◆ fagc_rst_gla_stronger_sig_thresh_exceeded_en
| uint8_t AD9361_InitParam::fagc_rst_gla_stronger_sig_thresh_exceeded_en |
◆ fagc_state_wait_time_ns
| uint32_t AD9361_InitParam::fagc_state_wait_time_ns |
◆ fagc_use_last_lock_level_for_set_gain_en
| uint8_t AD9361_InitParam::fagc_use_last_lock_level_for_set_gain_en |
◆ fdd_alt_word_order_enable
| uint8_t AD9361_InitParam::fdd_alt_word_order_enable |
◆ fdd_rx_rate_2tx_enable
| uint8_t AD9361_InitParam::fdd_rx_rate_2tx_enable |
◆ frequency_division_duplex_independent_mode_enable
| uint8_t AD9361_InitParam::frequency_division_duplex_independent_mode_enable |
◆ frequency_division_duplex_mode_enable
| uint8_t AD9361_InitParam::frequency_division_duplex_mode_enable |
◆ full_duplex_swap_bits_enable
| uint8_t AD9361_InitParam::full_duplex_swap_bits_enable |
◆ full_port_enable
| uint8_t AD9361_InitParam::full_port_enable |
◆ gc_adc_large_overload_thresh
| uint8_t AD9361_InitParam::gc_adc_large_overload_thresh |
◆ gc_adc_ovr_sample_size
| uint8_t AD9361_InitParam::gc_adc_ovr_sample_size |
◆ gc_adc_small_overload_thresh
| uint8_t AD9361_InitParam::gc_adc_small_overload_thresh |
◆ gc_dec_pow_measurement_duration
| uint16_t AD9361_InitParam::gc_dec_pow_measurement_duration |
◆ gc_dig_gain_enable
| uint8_t AD9361_InitParam::gc_dig_gain_enable |
◆ gc_lmt_overload_high_thresh
| uint16_t AD9361_InitParam::gc_lmt_overload_high_thresh |
◆ gc_lmt_overload_low_thresh
| uint16_t AD9361_InitParam::gc_lmt_overload_low_thresh |
◆ gc_low_power_thresh
| uint8_t AD9361_InitParam::gc_low_power_thresh |
◆ gc_max_dig_gain
| uint8_t AD9361_InitParam::gc_max_dig_gain |
◆ gc_rx1_mode
| uint8_t AD9361_InitParam::gc_rx1_mode |
◆ gc_rx2_mode
| uint8_t AD9361_InitParam::gc_rx2_mode |
◆ gc_use_rx_fir_out_for_dec_pwr_meas_enable
| uint8_t AD9361_InitParam::gc_use_rx_fir_out_for_dec_pwr_meas_enable |
◆ gpio_cal_sw1
| struct no_os_gpio_init_param AD9361_InitParam::gpio_cal_sw1 |
◆ gpio_cal_sw2
| struct no_os_gpio_init_param AD9361_InitParam::gpio_cal_sw2 |
◆ gpio_resetb
| struct no_os_gpio_init_param AD9361_InitParam::gpio_resetb |
◆ gpio_sync
| struct no_os_gpio_init_param AD9361_InitParam::gpio_sync |
◆ gpo0_inactive_state_high_enable
| uint8_t AD9361_InitParam::gpo0_inactive_state_high_enable |
◆ gpo0_rx_delay_us
| uint8_t AD9361_InitParam::gpo0_rx_delay_us |
◆ gpo0_slave_rx_enable
| uint8_t AD9361_InitParam::gpo0_slave_rx_enable |
◆ gpo0_slave_tx_enable
| uint8_t AD9361_InitParam::gpo0_slave_tx_enable |
◆ gpo0_tx_delay_us
| uint8_t AD9361_InitParam::gpo0_tx_delay_us |
◆ gpo1_inactive_state_high_enable
| uint8_t AD9361_InitParam::gpo1_inactive_state_high_enable |
◆ gpo1_rx_delay_us
| uint8_t AD9361_InitParam::gpo1_rx_delay_us |
◆ gpo1_slave_rx_enable
| uint8_t AD9361_InitParam::gpo1_slave_rx_enable |
◆ gpo1_slave_tx_enable
| uint8_t AD9361_InitParam::gpo1_slave_tx_enable |
◆ gpo1_tx_delay_us
| uint8_t AD9361_InitParam::gpo1_tx_delay_us |
◆ gpo2_inactive_state_high_enable
| uint8_t AD9361_InitParam::gpo2_inactive_state_high_enable |
◆ gpo2_rx_delay_us
| uint8_t AD9361_InitParam::gpo2_rx_delay_us |
◆ gpo2_slave_rx_enable
| uint8_t AD9361_InitParam::gpo2_slave_rx_enable |
◆ gpo2_slave_tx_enable
| uint8_t AD9361_InitParam::gpo2_slave_tx_enable |
◆ gpo2_tx_delay_us
| uint8_t AD9361_InitParam::gpo2_tx_delay_us |
◆ gpo3_inactive_state_high_enable
| uint8_t AD9361_InitParam::gpo3_inactive_state_high_enable |
◆ gpo3_rx_delay_us
| uint8_t AD9361_InitParam::gpo3_rx_delay_us |
◆ gpo3_slave_rx_enable
| uint8_t AD9361_InitParam::gpo3_slave_rx_enable |
◆ gpo3_slave_tx_enable
| uint8_t AD9361_InitParam::gpo3_slave_tx_enable |
◆ gpo3_tx_delay_us
| uint8_t AD9361_InitParam::gpo3_tx_delay_us |
◆ gpo_manual_mode_enable
| uint8_t AD9361_InitParam::gpo_manual_mode_enable |
◆ gpo_manual_mode_enable_mask
| uint32_t AD9361_InitParam::gpo_manual_mode_enable_mask |
◆ half_duplex_mode_enable
| uint8_t AD9361_InitParam::half_duplex_mode_enable |
◆ high_gain_dB
| uint32_t AD9361_InitParam::high_gain_dB |
◆ invert_data_bus_enable
| uint8_t AD9361_InitParam::invert_data_bus_enable |
◆ invert_data_clk_enable
| uint8_t AD9361_InitParam::invert_data_clk_enable |
◆ invert_rx_frame_enable
| uint8_t AD9361_InitParam::invert_rx_frame_enable |
◆ low_gain_dB
| uint32_t AD9361_InitParam::low_gain_dB |
◆ low_high_gain_threshold_mdB
| uint32_t AD9361_InitParam::low_high_gain_threshold_mdB |
◆ lvds_bias_mV
| uint32_t AD9361_InitParam::lvds_bias_mV |
◆ lvds_invert1_control
| uint8_t AD9361_InitParam::lvds_invert1_control |
◆ lvds_invert2_control
| uint8_t AD9361_InitParam::lvds_invert2_control |
◆ lvds_mode_enable
| uint8_t AD9361_InitParam::lvds_mode_enable |
◆ lvds_rx_onchip_termination_enable
| uint8_t AD9361_InitParam::lvds_rx_onchip_termination_enable |
◆ mgc_dec_gain_step
| uint8_t AD9361_InitParam::mgc_dec_gain_step |
◆ mgc_inc_gain_step
| uint8_t AD9361_InitParam::mgc_inc_gain_step |
◆ mgc_rx1_ctrl_inp_enable
| uint8_t AD9361_InitParam::mgc_rx1_ctrl_inp_enable |
◆ mgc_rx2_ctrl_inp_enable
| uint8_t AD9361_InitParam::mgc_rx2_ctrl_inp_enable |
◆ mgc_split_table_ctrl_inp_gain_mode
| uint8_t AD9361_InitParam::mgc_split_table_ctrl_inp_gain_mode |
◆ one_rx_one_tx_mode_use_rx_num
| uint8_t AD9361_InitParam::one_rx_one_tx_mode_use_rx_num |
◆ one_rx_one_tx_mode_use_tx_num
| uint8_t AD9361_InitParam::one_rx_one_tx_mode_use_tx_num |
◆ one_shot_mode_en
| uint8_t AD9361_InitParam::one_shot_mode_en |
◆ pp_rx_swap_enable
| uint8_t AD9361_InitParam::pp_rx_swap_enable |
◆ pp_tx_swap_enable
| uint8_t AD9361_InitParam::pp_tx_swap_enable |
◆ qec_tracking_slow_mode_enable
| uint8_t AD9361_InitParam::qec_tracking_slow_mode_enable |
◆ reference_clk_rate
| uint32_t AD9361_InitParam::reference_clk_rate |
◆ rf_rx_bandwidth_hz
| uint32_t AD9361_InitParam::rf_rx_bandwidth_hz |
◆ rf_tx_bandwidth_hz
| uint32_t AD9361_InitParam::rf_tx_bandwidth_hz |
◆ rssi_delay
| uint32_t AD9361_InitParam::rssi_delay |
◆ rssi_duration
| uint32_t AD9361_InitParam::rssi_duration |
◆ rssi_restart_mode
| uint8_t AD9361_InitParam::rssi_restart_mode |
◆ rssi_unit_is_rx_samples_enable
| uint8_t AD9361_InitParam::rssi_unit_is_rx_samples_enable |
◆ rssi_wait
| uint32_t AD9361_InitParam::rssi_wait |
◆ rx1rx2_phase_inversion_en
| uint8_t AD9361_InitParam::rx1rx2_phase_inversion_en |
◆ rx_adc_init
| struct axi_adc_init* AD9361_InitParam::rx_adc_init |
◆ rx_channel_swap_enable
| uint8_t AD9361_InitParam::rx_channel_swap_enable |
◆ rx_data_clock_delay
| uint32_t AD9361_InitParam::rx_data_clock_delay |
◆ rx_data_delay
| uint32_t AD9361_InitParam::rx_data_delay |
◆ rx_fastlock_delay_ns
| uint32_t AD9361_InitParam::rx_fastlock_delay_ns |
◆ rx_fastlock_pincontrol_enable
| uint8_t AD9361_InitParam::rx_fastlock_pincontrol_enable |
◆ rx_frame_pulse_mode_enable
| uint8_t AD9361_InitParam::rx_frame_pulse_mode_enable |
◆ rx_path_clock_frequencies
| uint32_t AD9361_InitParam::rx_path_clock_frequencies[6] |
◆ rx_rf_port_input_select
| uint32_t AD9361_InitParam::rx_rf_port_input_select |
◆ rx_synthesizer_frequency_hz
| uint64_t AD9361_InitParam::rx_synthesizer_frequency_hz |
◆ single_data_rate_enable
| uint8_t AD9361_InitParam::single_data_rate_enable |
◆ single_port_mode_enable
| uint8_t AD9361_InitParam::single_port_mode_enable |
◆ spi_param
| struct no_os_spi_init_param AD9361_InitParam::spi_param |
◆ split_gain_table_mode_enable
| uint8_t AD9361_InitParam::split_gain_table_mode_enable |
◆ swap_ports_enable
| uint8_t AD9361_InitParam::swap_ports_enable |
◆ tdd_skip_vco_cal_enable
| uint8_t AD9361_InitParam::tdd_skip_vco_cal_enable |
◆ tdd_use_dual_synth_mode_enable
| uint8_t AD9361_InitParam::tdd_use_dual_synth_mode_enable |
◆ temp_sense_decimation
| uint32_t AD9361_InitParam::temp_sense_decimation |
◆ temp_sense_measurement_interval_ms
| uint16_t AD9361_InitParam::temp_sense_measurement_interval_ms |
◆ temp_sense_offset_signed
| int8_t AD9361_InitParam::temp_sense_offset_signed |
◆ temp_sense_periodic_measurement_enable
| uint8_t AD9361_InitParam::temp_sense_periodic_measurement_enable |
◆ trx_synthesizer_target_fref_overwrite_hz
| uint32_t AD9361_InitParam::trx_synthesizer_target_fref_overwrite_hz |
◆ two_rx_two_tx_mode_enable
| uint8_t AD9361_InitParam::two_rx_two_tx_mode_enable |
◆ two_t_two_r_timing_enable
| uint8_t AD9361_InitParam::two_t_two_r_timing_enable |
◆ tx1_mon_front_end_gain
| uint32_t AD9361_InitParam::tx1_mon_front_end_gain |
◆ tx1_mon_lo_cm
| uint32_t AD9361_InitParam::tx1_mon_lo_cm |
◆ tx2_mon_front_end_gain
| uint32_t AD9361_InitParam::tx2_mon_front_end_gain |
◆ tx2_mon_lo_cm
| uint32_t AD9361_InitParam::tx2_mon_lo_cm |
◆ tx_attenuation_mdB
| int32_t AD9361_InitParam::tx_attenuation_mdB |
◆ tx_channel_swap_enable
| uint8_t AD9361_InitParam::tx_channel_swap_enable |
◆ tx_dac_init
| struct axi_dac_init* AD9361_InitParam::tx_dac_init |
◆ tx_data_delay
| uint32_t AD9361_InitParam::tx_data_delay |
◆ tx_fastlock_delay_ns
| uint32_t AD9361_InitParam::tx_fastlock_delay_ns |
◆ tx_fastlock_pincontrol_enable
| uint8_t AD9361_InitParam::tx_fastlock_pincontrol_enable |
◆ tx_fb_clock_delay
| uint32_t AD9361_InitParam::tx_fb_clock_delay |
◆ tx_lo_powerdown_managed_enable
| uint8_t AD9361_InitParam::tx_lo_powerdown_managed_enable |
◆ tx_mon_delay
| uint32_t AD9361_InitParam::tx_mon_delay |
◆ tx_mon_duration
| uint32_t AD9361_InitParam::tx_mon_duration |
◆ tx_mon_track_en
| uint8_t AD9361_InitParam::tx_mon_track_en |
◆ tx_path_clock_frequencies
| uint32_t AD9361_InitParam::tx_path_clock_frequencies[6] |
◆ tx_rf_port_input_select
| uint32_t AD9361_InitParam::tx_rf_port_input_select |
◆ tx_synthesizer_frequency_hz
| uint64_t AD9361_InitParam::tx_synthesizer_frequency_hz |
◆ update_tx_gain_in_alert_enable
| uint8_t AD9361_InitParam::update_tx_gain_in_alert_enable |
◆ xo_disable_use_ext_refclk_enable
| uint8_t AD9361_InitParam::xo_disable_use_ext_refclk_enable |
The documentation for this struct was generated from the following file:
- drivers/rf-transceiver/ad9361/ad9361_api.h
