ad9250_platform_data Struct Reference

Platform specific information. More...

#include <ad9250.h>

Public Attributes
int8_t	extrn_pdwnmode
int8_t	en_clk_dcs
int8_t	clk_selection
int8_t	clk_div_ratio
int8_t	clk_div_phase
int8_t	adc_vref
int8_t	pll_low_encode
int8_t	name [16]

Detailed Description

Platform specific information.

Member Data Documentation

adc_vref

int8_t ad9250_platform_data::adc_vref

Main reference full-scale VREF adjustment. 0x0f = internal 2.087 V p-p ... 0x01 = internal 1.772 V p-p 0x00 = internal 1.75 V p-p [default] 0x1F = internal 1.727 V p-p ... 0x10 = internal 1.383 V p-p

clk_div_phase

int8_t ad9250_platform_data::clk_div_phase

Clock divide phase relative to the encode clock. 0x0 = 0 input clock cycles delayed 0x1 = 1 input clock cycles delayed ... 0x7 = 7 input clock cycles delayed

clk_div_ratio

int8_t ad9250_platform_data::clk_div_ratio

Clock divider ratio relative to the encode clock. 0x00 = divide by 1 0x01 = divide by 2 ... 0x07 = divide by 8

clk_selection

int8_t ad9250_platform_data::clk_selection

Clock selection. 0 = Nyquist clock 2 = RF clock divide by 4 3 = clock off

en_clk_dcs

int8_t ad9250_platform_data::en_clk_dcs

Clock duty cycle stabilizer enable. 0 = disable 1 = enable

extrn_pdwnmode

int8_t ad9250_platform_data::extrn_pdwnmode

External PDWN mode. 0 = PDWN is full power down 1 = PDWN puts device in standby

name

int8_t ad9250_platform_data::name[16]

Device name

pll_low_encode

int8_t ad9250_platform_data::pll_low_encode

PLL low encode. 0 = for lane speeds > 2 Gbps 1 = for lane speeds < 2 Gbps

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The documentation for this struct was generated from the following file:

• drivers/adc/ad9250/ad9250.h