#include <adf4153.h>

Public Attributes
uint32_t	ref_in

uint32_t	channel_spacing

uint16_t	frac_value: 12

uint16_t	int_value: 9

uint8_t	fastlock: 1

uint16_t	mod_value: 12

uint8_t	r_counter: 4

uint8_t	prescaler: 1

uint8_t	muxout: 3

uint8_t	load_control: 1

uint8_t	counter_reset: 1

uint8_t	cp_three_state: 1

uint8_t	power_down: 1

uint8_t	ldp: 1

uint8_t	pd_polarity: 1

uint8_t	cp_current: 4

uint8_t	ref_doubler: 1

uint8_t	resync: 4

uint8_t	noise_spur: 5

Member Data Documentation

◆ channel_spacing

uint32_t adf4153_settings_t::channel_spacing

◆ counter_reset

uint8_t adf4153_settings_t::counter_reset

resets the R and N counters

◆ cp_current

uint8_t adf4153_settings_t::cp_current

Charge Pump Current settings, this should be set to the charge pump current that the loop filter is designed with

◆ cp_three_state

uint8_t adf4153_settings_t::cp_three_state

puts the charge pump into three-state mode when programmed to 1

◆ fastlock

uint8_t adf4153_settings_t::fastlock

when set to logic high fast-lock is enabled

◆ frac_value

uint16_t adf4153_settings_t::frac_value

these 12 bits control what is loaded as the FRAC value into the fractional interpolator.

◆ int_value

uint16_t adf4153_settings_t::int_value

these nine bits control what is loaded as the INT value, this is used to determine the overall division factor.

◆ ldp

uint8_t adf4153_settings_t::ldp

lock detect precision

◆ load_control

uint8_t adf4153_settings_t::load_control

when set to logic high the value being programmed in the modulus is not loaded into the modulus. Instead, it sets the resync delay of the Sigma-Delta.

◆ mod_value

uint16_t adf4153_settings_t::mod_value

set the fractional modulus, this is the ratio of the PFD frequency to the channel step resolution on the RF output

◆ muxout

uint8_t adf4153_settings_t::muxout

the on chip multiplexer selection bits

◆ noise_spur

uint8_t adf4153_settings_t::noise_spur

allows the user to optimize a design either for improved spurious performance or for improved phase noise performance

◆ pd_polarity

uint8_t adf4153_settings_t::pd_polarity

phase detector polarity

◆ power_down

uint8_t adf4153_settings_t::power_down

activate power down mode

◆ prescaler

uint8_t adf4153_settings_t::prescaler

the dual-modulus prescaler, along with the INT, FRAC and MOD counters, determines the overall division ratio from the RFin to PFD input

◆ r_counter

uint8_t adf4153_settings_t::r_counter

the r counter allows the input reference frequency to be divided down to produce the reference clock to phase frequency detector

◆ ref_doubler

uint8_t adf4153_settings_t::ref_doubler

REFin Doubler, when the doubler is enabled, both the rising and falling edges of REFin become active edges at the PFD input

◆ ref_in

uint32_t adf4153_settings_t::ref_in

◆ resync

uint8_t adf4153_settings_t::resync

define the time between two resync, if it is zero, than the phase resync feature is disabled

The documentation for this struct was generated from the following file:

drivers/frequency/adf4153/adf4153.h

Public Attributes