no-OS
Loading...
Searching...
No Matches
Public Attributes | List of all members
adxcvr Struct Reference

ADI JESD204B/C AXI_ADXCVR Highspeed Transceiver Device structure. More...

#include <altera_adxcvr.h>

Collaboration diagram for adxcvr:
[legend]

Public Attributes

const char * name
 
uint32_t base
 
bool is_transmit
 
uint32_t lanes_per_link
 
uint32_t adxcfg_base [4]
 
uint32_t atx_pll_base
 
uint32_t reset_counter
 
uint32_t lane_rate_khz
 
uint32_t parent_rate_khz
 
bool initial_recalc
 
bool cpll_enable
 
bool qpll_enable
 
bool tx_enable
 
bool lpm_enable
 
uint32_t num_lanes
 
uint32_t ref_rate_khz
 
uint32_t sys_clk_sel
 
uint32_t out_clk_sel
 
struct xilinx_xcvr xlx_xcvr
 
struct no_os_clk_desc * clk_out
 

Detailed Description

ADI JESD204B/C AXI_ADXCVR Highspeed Transceiver Device structure.

ADI JESD204B/C AXI_ADXCVR Highspeed Transceiver Initialization structure.

Member Data Documentation

◆ adxcfg_base

uint32_t adxcvr::adxcfg_base[4]

◆ atx_pll_base

uint32_t adxcvr::atx_pll_base

◆ base

uint32_t adxcvr::base

Base address

◆ clk_out

struct no_os_clk_desc* adxcvr::clk_out

Exported no-OS output clock

◆ cpll_enable

bool adxcvr::cpll_enable

Enable CPLL for the transceiver

◆ initial_recalc

bool adxcvr::initial_recalc

◆ is_transmit

bool adxcvr::is_transmit

◆ lane_rate_khz

uint32_t adxcvr::lane_rate_khz

Lane rate in KHz

◆ lanes_per_link

uint32_t adxcvr::lanes_per_link

◆ lpm_enable

bool adxcvr::lpm_enable

Enable LPM mode for the transceiver. Otherwise use DFE.

◆ name

const char * adxcvr::name

Device Name

◆ num_lanes

uint32_t adxcvr::num_lanes

Number of lanes

◆ out_clk_sel

uint32_t adxcvr::out_clk_sel

Controls the OUTCLKSEL multiplexer, controlling what will be forwarded to OUTCLK pin.

◆ parent_rate_khz

uint32_t adxcvr::parent_rate_khz

◆ qpll_enable

bool adxcvr::qpll_enable

Enable QPLL for the transceiver

◆ ref_rate_khz

uint32_t adxcvr::ref_rate_khz

Reference Clock rate

◆ reset_counter

uint32_t adxcvr::reset_counter

◆ sys_clk_sel

uint32_t adxcvr::sys_clk_sel

Select the PLL reference clock source to be forwarded to the OUTCLK MUX: 0-CPLL, 3-QPLL0.

◆ tx_enable

bool adxcvr::tx_enable

TX Enable

◆ xlx_xcvr

struct xilinx_xcvr adxcvr::xlx_xcvr

Structure holding the configuration of the Xilinx Transceiver.

The documentation for this struct was generated from the following files: