41#define ADXCVR_SYS_CLK_CPLL 0x00
42#define ADXCVR_SYS_CLK_QPLL1 0x02
43#define ADXCVR_SYS_CLK_QPLL0 0x03
46#define ADXCVR_OUTCLK_PCS 1
47#define ADXCVR_OUTCLK_PMA 2
48#define ADXCVR_REFCLK 3
49#define ADXCVR_REFCLK_DIV2 4
50#define ADXCVR_PROGDIV_CLK 5
124 unsigned int drp_port,
129 unsigned int drp_port,
146 unsigned long parent_rate);
const struct no_os_clk_platform_ops adxcvr_clk_ops
adxcvr clock ops
Definition axi_adxcvr.c:749
int adxcvr_clk_disable(struct adxcvr *xcvr)
AXI ADXCVR Clock Disable.
Definition axi_adxcvr.c:523
int adxcvr_clk_enable(struct adxcvr *xcvr)
AXI ADXCVR Clock Enable.
Definition axi_adxcvr.c:473
int32_t adxcvr_read(struct adxcvr *xcvr, uint32_t reg_addr, uint32_t *reg_val)
adxcvr_read
Definition altera_adxcvr.c:83
int32_t adxcvr_init(struct adxcvr **ad_xcvr, const struct adxcvr_init *init)
adxcvr_init
Definition altera_adxcvr.c:427
int32_t adxcvr_remove(struct adxcvr *xcvr)
adxcvr_remove
Definition altera_adxcvr.c:478
int adxcvr_drp_read(struct adxcvr *xcvr, unsigned int drp_port, unsigned int reg, unsigned int *val)
AXI ADXCVR DPR Port Read.
Definition axi_adxcvr.c:158
int adxcvr_drp_write(struct adxcvr *xcvr, unsigned int drp_port, unsigned int reg, unsigned int val)
AXI ADXCVR DPR Port Write.
Definition axi_adxcvr.c:193
int adxcvr_clk_set_rate(struct adxcvr *xcvr, unsigned long rate, unsigned long parent_rate)
AXI ADXCVR Clock Set Rate.
Definition axi_adxcvr.c:303
int32_t adxcvr_write(struct adxcvr *xcvr, uint32_t reg_addr, uint32_t reg_val)
adxcvr_write
Definition altera_adxcvr.c:71
int32_t adxcvr_status_error(struct adxcvr *xcvr)
AXI ADXCVR Status Read.
Definition axi_adxcvr.c:427
Definition altera_adxcvr.h:92
uint32_t lane_rate_khz
Definition altera_adxcvr.h:97
const char * name
Definition altera_adxcvr.h:93
uint32_t sys_clk_sel
Definition axi_adxcvr.h:102
uint32_t out_clk_sel
Definition axi_adxcvr.h:106
uint32_t ref_rate_khz
Definition axi_adxcvr.h:112
bool export_no_os_clk
Definition axi_adxcvr.h:114
uint32_t base
Definition altera_adxcvr.h:94
bool lpm_enable
Definition axi_adxcvr.h:108
ADI JESD204B/C AXI_ADXCVR Highspeed Transceiver Device structure.
Definition altera_adxcvr.h:79
const char * name
Definition altera_adxcvr.h:80
bool cpll_enable
Definition axi_adxcvr.h:62
uint32_t lane_rate_khz
Definition altera_adxcvr.h:87
uint32_t base
Definition altera_adxcvr.h:81
uint32_t ref_rate_khz
Definition axi_adxcvr.h:74
uint32_t out_clk_sel
Definition axi_adxcvr.h:82
bool qpll_enable
Definition axi_adxcvr.h:64
uint32_t num_lanes
Definition axi_adxcvr.h:70
bool tx_enable
Definition axi_adxcvr.h:66
struct xilinx_xcvr xlx_xcvr
Definition axi_adxcvr.h:84
uint32_t sys_clk_sel
Definition axi_adxcvr.h:78
struct no_os_clk_desc * clk_out
Definition axi_adxcvr.h:86
bool lpm_enable
Definition axi_adxcvr.h:68
Structure holding CLK descriptor.
Definition no_os_clk.h:69
xilinx_xcvr parameters structure.
Definition xilinx_transceiver.h:160
Driver for the Xilinx High-speed transceiver dynamic reconfiguration.