no-OS/doxygen/axi__adxcvr_8h_source.html

/***************************************************************************/

#ifndef AXI_ADXCVR_H_

#define AXI_ADXCVR_H_


/******************************************************************************/

/***************************** Include Files **********************************/

/******************************************************************************/

#include <stdint.h>

#include <stdbool.h>

#include "xilinx_transceiver.h"


/******************************************************************************/

/********************** Macros and Types Declarations *************************/

/******************************************************************************/


// Selection of PLL reference clock source to drive the RXOUTCLK

#define ADXCVR_SYS_CLK_CPLL         0x00

#define ADXCVR_SYS_CLK_QPLL1        0x02

#define ADXCVR_SYS_CLK_QPLL0        0x03


// adi,out-clk-select

#define ADXCVR_OUTCLK_PCS       1

#define ADXCVR_OUTCLK_PMA       2

#define ADXCVR_REFCLK       3

#define ADXCVR_REFCLK_DIV2  4

#define ADXCVR_PROGDIV_CLK  5 /* GTHE3, GTHE4, GTYE4 only */


struct adxcvr {

    const char *name;

    uint32_t base;

    bool cpll_enable;

    bool qpll_enable;

    bool tx_enable;

    bool lpm_enable;

    uint32_t num_lanes;

    uint32_t lane_rate_khz;

    uint32_t ref_rate_khz;

    uint32_t sys_clk_sel;

    uint32_t out_clk_sel;

    struct xilinx_xcvr xlx_xcvr;

    struct no_os_clk_desc *clk_out;

};


struct adxcvr_init {

    const char *name;

    uint32_t base;

    uint32_t sys_clk_sel;

    uint32_t out_clk_sel;

    bool lpm_enable;

    uint32_t lane_rate_khz;

    uint32_t ref_rate_khz;

    bool export_no_os_clk;

};


extern const struct no_os_clk_platform_ops adxcvr_clk_ops;


/******************************************************************************/

/************************ Functions Declarations ******************************/

/******************************************************************************/

int adxcvr_drp_read(struct adxcvr *xcvr,

            unsigned int drp_port,

            unsigned int reg,

            unsigned int *val);

int adxcvr_drp_write(struct adxcvr *xcvr,

             unsigned int drp_port,

             unsigned int reg,

             unsigned int val);

int32_t adxcvr_status_error(struct adxcvr *xcvr);

int adxcvr_clk_enable(struct adxcvr *xcvr);

int adxcvr_clk_disable(struct adxcvr *xcvr);

int32_t adxcvr_init(struct adxcvr **ad_xcvr,

            const struct adxcvr_init *init);

int32_t adxcvr_remove(struct adxcvr *xcvr);

int adxcvr_clk_set_rate(struct adxcvr *xcvr,

            unsigned long rate,

            unsigned long parent_rate);

int32_t adxcvr_write(struct adxcvr *xcvr, uint32_t reg_addr, uint32_t reg_val);

int32_t adxcvr_read(struct adxcvr *xcvr, uint32_t reg_addr, uint32_t *reg_val);

#endif