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Classes | Macros | Enumerations
t_ad9528.h File Reference

Contains enum and structure data types for all AD9528 function calls. More...

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Classes

struct  ad9528pll1Settings_t
 Structure to hold AD9528 PLL1 settings. More...
 
struct  ad9528pll2Settings_t
 Structure to hold AD9528 PLL2 settings. More...
 
struct  ad9528outputSettings_t
 Structure to hold AD9528 Output Clock settings. More...
 
struct  ad9528sysrefSettings_t
 Structure to hold AD9528 SYSREF output settings. More...
 
struct  ad9528Device_t
 Structure to hold AD9528 settings. More...
 

Macros

#define AD9528_ADDR_ADI_SPI_CONFIG_A   0x000
 
#define AD9528_ADDR_ADI_SPI_CONFIG_B   0x001
 
#define AD9528_ADDR_IO_UPDATE   0x00F
 
#define AD9528_ADDR_REF_A_DIVIDER_LSB   0x100
 
#define AD9528_ADDR_REF_A_DIVIDER_MSB   0x101
 
#define AD9528_ADDR_REF_B_DIVIDER_LSB   0x102
 
#define AD9528_ADDR_REF_B_DIVIDER_MSB   0x103
 
#define AD9528_ADDR_PLL1_N_DIV_LSB   0x104
 
#define AD9528_ADDR_PLL1_N_DIV_MSB   0x105
 
#define AD9528_ADDR_PLL1_CHARGEPUMP   0x106
 
#define AD9528_ADDR_PLL1_CP_CTRL2   0x107
 
#define AD9528_ADDR_INPUT_RECEIVERS1   0x108
 
#define AD9528_ADDR_INPUT_RECEIVERS2   0x109
 
#define AD9528_ADDR_INPUT_RECEIVERS3   0x10A
 
#define AD9528_ADDR_PLL1_FASTLOCK   0x10B
 
#define AD9528_ADDR_PLL2_CHARGEPUMP   0x200
 
#define AD9528_ADDR_PLL2_N_DIV   0x201
 
#define AD9528_ADDR_PLL2_CTRL   0x202
 
#define AD9528_ADDR_PLL2_VCO_CTRL   0x203
 
#define AD9528_ADDR_PLL2_VCO_DIV   0x204
 
#define AD9528_ADDR_PLL2_LF_CTRL1   0x205
 
#define AD9528_ADDR_PLL2_LF_CTRL2   0x206
 
#define AD9528_ADDR_PLL2_RDIV   0x207
 
#define AD9528_ADDR_PLL2_REPLICA_CHDIV   0x208
 
#define AD9528_ADDR_PLL2_REPLICA_DIV_PHASE   0x209
 
#define AD9528_ADDR_CH_OUT0_CTRL1   0x300
 
#define AD9528_ADDR_CH_OUT0_CTRL2   0x301
 
#define AD9528_ADDR_CH_OUT0_CHDIV   0x302
 
#define AD9528_ADDR_OUTPUT_SYNC   0x32A
 
#define AD9528_ADDR_MASK_SYNC1   0x32B
 
#define AD9528_ADDR_MASK_SYNC2   0x32C
 
#define AD9528_ADDR_EN_OUTPUT_PATH_SEL1   0x32D
 
#define AD9528_ADDR_EN_OUTPUT_PATH_SEL2   0x32E
 
#define AD9528_ADDR_SYSERF_DIV_LSB   0x400
 
#define AD9528_ADDR_SYSERF_DIV_MSB   0x401
 
#define AD9528_ADDR_SYSREF_CTRL3   0x402
 
#define AD9528_ADDR_SYSREF_CTRL4   0x403
 
#define AD9528_ADDR_SYSREF_CTRL5   0x404
 
#define AD9528_ADDR_POWERDOWN_CTRL   0x500
 
#define AD9528_ADDR_CH_POWERDOWN1   0x501
 
#define AD9528_ADDR_CH_POWERDOWN2   0x502
 
#define AD9528_ADDR_LDO_ENABLES1   0x503
 
#define AD9528_ADDR_LDO_ENABLES2   0x504
 
#define AD9528_ADDR_STATUS0_CTRL   0x505
 
#define AD9528_ADDR_STATUS1_CTRL   0x506
 
#define AD9528_ADDR_STATUS_OE   0x507
 
#define AD9528_ADDR_STATUS_READBACK0   0x508
 
#define AD9528_ADDR_STATUS_READBACK1   0x509
 

Enumerations

enum  ad9528outSourceSel_t {
  CHANNEL_DIV = 0,
  PLL1_OUTPUT = 1,
  SYSREF = 2,
  INV_PLL1_OUTPUT = 5
}
 Enum to select what source outputs from each AD9528 output channel. More...
 
enum  ad9528outBufferControl_t {
  LVDS = 0,
  LVDS_BOOST = 1,
  HSTL = 2
}
 Enum to select what output buffer standard is used for the clock outputs. More...
 
enum  ad9528RefBuffer_t {
  DISABLED = 0,
  SINGLE_ENDED,
  NEG_SINGLE_ENDED,
  DIFFERENTIAL
}
 Enum to select the clock input buffer mode. More...
 
enum  sysrefSourceSelection_t {
  EXTERNAL = 0,
  EXT_RESAMPLED = 1,
  INTERNAL = 2
}
 Enum to select the SYSREF output source. More...
 
enum  sysrefPatternMode_t {
  NSHOT = 0,
  CONTINUOUS = 1,
  PRBS = 2,
  STOP = 3
}
 Enum to choose the SYSREF pattern mode. More...
 
enum  sysrefPinEdgeMode_t {
  LEVEL_ACTIVE_HIGH = 0,
  LEVEL_ACTIVE_LOW = 1,
  RISING_EDGE = 2,
  FALLING_EDGE = 3
}
 Enum to select the SYSREF input pin mode. More...
 
enum  sysrefNshotMode_t {
  ONE_PULSE = 0,
  TWO_PULSES = 2,
  FOUR_PULSES = 3,
  SIX_PULSES = 4,
  EIGHT_PULSES = 5
}
 Enum to select the SYSREF output # of pulses for NSHOT mode. More...
 
enum  sysrefRequestMethod_t {
  SPI = 0,
  PIN = 1
}
 

Detailed Description

Contains enum and structure data types for all AD9528 function calls.

Macro Definition Documentation

◆ AD9528_ADDR_ADI_SPI_CONFIG_A

#define AD9528_ADDR_ADI_SPI_CONFIG_A   0x000

Legal Disclaimer Copyright 2015-2017 Analog Devices Inc. Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.

◆ AD9528_ADDR_ADI_SPI_CONFIG_B

#define AD9528_ADDR_ADI_SPI_CONFIG_B   0x001

◆ AD9528_ADDR_CH_OUT0_CHDIV

#define AD9528_ADDR_CH_OUT0_CHDIV   0x302

◆ AD9528_ADDR_CH_OUT0_CTRL1

#define AD9528_ADDR_CH_OUT0_CTRL1   0x300

◆ AD9528_ADDR_CH_OUT0_CTRL2

#define AD9528_ADDR_CH_OUT0_CTRL2   0x301

◆ AD9528_ADDR_CH_POWERDOWN1

#define AD9528_ADDR_CH_POWERDOWN1   0x501

◆ AD9528_ADDR_CH_POWERDOWN2

#define AD9528_ADDR_CH_POWERDOWN2   0x502

◆ AD9528_ADDR_EN_OUTPUT_PATH_SEL1

#define AD9528_ADDR_EN_OUTPUT_PATH_SEL1   0x32D

◆ AD9528_ADDR_EN_OUTPUT_PATH_SEL2

#define AD9528_ADDR_EN_OUTPUT_PATH_SEL2   0x32E

◆ AD9528_ADDR_INPUT_RECEIVERS1

#define AD9528_ADDR_INPUT_RECEIVERS1   0x108

◆ AD9528_ADDR_INPUT_RECEIVERS2

#define AD9528_ADDR_INPUT_RECEIVERS2   0x109

◆ AD9528_ADDR_INPUT_RECEIVERS3

#define AD9528_ADDR_INPUT_RECEIVERS3   0x10A

◆ AD9528_ADDR_IO_UPDATE

#define AD9528_ADDR_IO_UPDATE   0x00F

◆ AD9528_ADDR_LDO_ENABLES1

#define AD9528_ADDR_LDO_ENABLES1   0x503

◆ AD9528_ADDR_LDO_ENABLES2

#define AD9528_ADDR_LDO_ENABLES2   0x504

◆ AD9528_ADDR_MASK_SYNC1

#define AD9528_ADDR_MASK_SYNC1   0x32B

◆ AD9528_ADDR_MASK_SYNC2

#define AD9528_ADDR_MASK_SYNC2   0x32C

◆ AD9528_ADDR_OUTPUT_SYNC

#define AD9528_ADDR_OUTPUT_SYNC   0x32A

◆ AD9528_ADDR_PLL1_CHARGEPUMP

#define AD9528_ADDR_PLL1_CHARGEPUMP   0x106

◆ AD9528_ADDR_PLL1_CP_CTRL2

#define AD9528_ADDR_PLL1_CP_CTRL2   0x107

◆ AD9528_ADDR_PLL1_FASTLOCK

#define AD9528_ADDR_PLL1_FASTLOCK   0x10B

◆ AD9528_ADDR_PLL1_N_DIV_LSB

#define AD9528_ADDR_PLL1_N_DIV_LSB   0x104

◆ AD9528_ADDR_PLL1_N_DIV_MSB

#define AD9528_ADDR_PLL1_N_DIV_MSB   0x105

◆ AD9528_ADDR_PLL2_CHARGEPUMP

#define AD9528_ADDR_PLL2_CHARGEPUMP   0x200

◆ AD9528_ADDR_PLL2_CTRL

#define AD9528_ADDR_PLL2_CTRL   0x202

◆ AD9528_ADDR_PLL2_LF_CTRL1

#define AD9528_ADDR_PLL2_LF_CTRL1   0x205

◆ AD9528_ADDR_PLL2_LF_CTRL2

#define AD9528_ADDR_PLL2_LF_CTRL2   0x206

◆ AD9528_ADDR_PLL2_N_DIV

#define AD9528_ADDR_PLL2_N_DIV   0x201

◆ AD9528_ADDR_PLL2_RDIV

#define AD9528_ADDR_PLL2_RDIV   0x207

◆ AD9528_ADDR_PLL2_REPLICA_CHDIV

#define AD9528_ADDR_PLL2_REPLICA_CHDIV   0x208

◆ AD9528_ADDR_PLL2_REPLICA_DIV_PHASE

#define AD9528_ADDR_PLL2_REPLICA_DIV_PHASE   0x209

◆ AD9528_ADDR_PLL2_VCO_CTRL

#define AD9528_ADDR_PLL2_VCO_CTRL   0x203

◆ AD9528_ADDR_PLL2_VCO_DIV

#define AD9528_ADDR_PLL2_VCO_DIV   0x204

◆ AD9528_ADDR_POWERDOWN_CTRL

#define AD9528_ADDR_POWERDOWN_CTRL   0x500

◆ AD9528_ADDR_REF_A_DIVIDER_LSB

#define AD9528_ADDR_REF_A_DIVIDER_LSB   0x100

◆ AD9528_ADDR_REF_A_DIVIDER_MSB

#define AD9528_ADDR_REF_A_DIVIDER_MSB   0x101

◆ AD9528_ADDR_REF_B_DIVIDER_LSB

#define AD9528_ADDR_REF_B_DIVIDER_LSB   0x102

◆ AD9528_ADDR_REF_B_DIVIDER_MSB

#define AD9528_ADDR_REF_B_DIVIDER_MSB   0x103

◆ AD9528_ADDR_STATUS0_CTRL

#define AD9528_ADDR_STATUS0_CTRL   0x505

◆ AD9528_ADDR_STATUS1_CTRL

#define AD9528_ADDR_STATUS1_CTRL   0x506

◆ AD9528_ADDR_STATUS_OE

#define AD9528_ADDR_STATUS_OE   0x507

◆ AD9528_ADDR_STATUS_READBACK0

#define AD9528_ADDR_STATUS_READBACK0   0x508

◆ AD9528_ADDR_STATUS_READBACK1

#define AD9528_ADDR_STATUS_READBACK1   0x509

◆ AD9528_ADDR_SYSERF_DIV_LSB

#define AD9528_ADDR_SYSERF_DIV_LSB   0x400

◆ AD9528_ADDR_SYSERF_DIV_MSB

#define AD9528_ADDR_SYSERF_DIV_MSB   0x401

◆ AD9528_ADDR_SYSREF_CTRL3

#define AD9528_ADDR_SYSREF_CTRL3   0x402

◆ AD9528_ADDR_SYSREF_CTRL4

#define AD9528_ADDR_SYSREF_CTRL4   0x403

◆ AD9528_ADDR_SYSREF_CTRL5

#define AD9528_ADDR_SYSREF_CTRL5   0x404

Enumeration Type Documentation

◆ ad9528outBufferControl_t

Enum to select what output buffer standard is used for the clock outputs.

Enumerator
LVDS 
LVDS_BOOST 
HSTL 

◆ ad9528outSourceSel_t

Enum to select what source outputs from each AD9528 output channel.

Enumerator
CHANNEL_DIV 
PLL1_OUTPUT 
SYSREF 
INV_PLL1_OUTPUT 

◆ ad9528RefBuffer_t

Enum to select the clock input buffer mode.

Enumerator
DISABLED 
SINGLE_ENDED 
NEG_SINGLE_ENDED 
DIFFERENTIAL 

◆ sysrefNshotMode_t

Enum to select the SYSREF output # of pulses for NSHOT mode.

Enumerator
ONE_PULSE 
TWO_PULSES 
FOUR_PULSES 
SIX_PULSES 
EIGHT_PULSES 

◆ sysrefPatternMode_t

Enum to choose the SYSREF pattern mode.

Enumerator
NSHOT 
CONTINUOUS 
PRBS 
STOP 

◆ sysrefPinEdgeMode_t

Enum to select the SYSREF input pin mode.

Enumerator
LEVEL_ACTIVE_HIGH 
LEVEL_ACTIVE_LOW 
RISING_EDGE 
FALLING_EDGE 

◆ sysrefRequestMethod_t

Enumerator
SPI 
PIN 

◆ sysrefSourceSelection_t

Enum to select the SYSREF output source.

Enumerator
EXTERNAL 
EXT_RESAMPLED 
INTERNAL