xilinx_transceiver.c File Reference

Driver for the Xilinx High-speed transceiver dynamic reconfiguration. More...

#include <stdlib.h>
#include <stdio.h>
#include <inttypes.h>
#include "no_os_util.h"
#include "no_os_error.h"
#include "axi_adxcvr.h"
#include "xilinx_transceiver.h"
#include "no_os_print_log.h"

Include dependency graph for xilinx_transceiver.c:

Macros
#define	OUT_DIV_ADDR   0x88
#define	OUT_DIV_TX_OFFSET   0x4
#define	OUT_DIV_RX_OFFSET   0x0
#define	RXCDR_CFG0_ADDR   0xa8
#define	RXCDR_CFG0_MASK   0xffff
#define	RXCDR_CFG1_ADDR   0xa9
#define	RXCDR_CFG1_MASK   0xffff
#define	RXCDR_CFG2_ADDR   0xaa
#define	RXCDR_CFG2_MASK   0xffff
#define	RXCDR_CFG3_ADDR   0xab
#define	RXCDR_CFG3_MASK   0xffff
#define	RXCDR_CFG4_ADDR   0xac
#define	RXCDR_CFG4_MASK   0x00ff
#define	RX_DFE_LPM_CFG_ADDR   0x29
#define	RX_DFE_LPM_CFG_MASK   0xffff
#define	QPLL_CFG0_ADDR   0x32
#define	QPLL_CFG0_LOWBAND_MASK   0x0040
#define	QPLL_CFG1_ADDR   0x33
#define	QPLL_REFCLK_DIV_M_MASK   0xf800
#define	QPLL_REFCLK_DIV_M_OFFSET   11
#define	QPLL_REFCLK_DIV_M(x)
#define	QPLL_FBDIV_N_ADDR   0x36
#define	QPLL_FBDIV_N_MASK   0x03ff
#define	QPLL_FBDIV_RATIO_ADDR   0x37
#define	QPLL_FBDIV_RATIO_MASK   0x0040
#define	CPLL_CFG0_ADDR   0x5c
#define	CPLL_CFG0_MASK   0xff00
#define	CPLL_CFG1_ADDR   0x5d
#define	CPLL_CFG1_MASK   0xffff
#define	CPLL_REFCLK_DIV_M_ADDR   0x5e
#define	CPLL_REFCLK_DIV_M_MASK   0x1f00
#define	CPLL_FB_DIV_45_N1_MASK   0x0080
#define	CPLL_FBDIV_N2_MASK   0x007f
#define	RX_CLK25_DIV   0x11
#define	RX_CLK25_DIV_OFFSET   6
#define	RX_CLK25_DIV_MASK   0x07c0
#define	TX_CLK25_DIV   0x6a
#define	TX_CLK25_DIV_MASK   0x1f
#define	GTH34_SYSCLK_QPLL1   2
#define	GTX_RX_PRBS_ERR_CNT   0x15c /* 16-bit */
#define	GTH3_RX_PRBS_ERR_CNT   0x15E /* 32-bit */
#define	GTH4_RX_PRBS_ERR_CNT   0x25E /* 32-bit also applied for GTY */
#define	GTH34_QPLL_FBDIV(xcvr, x)
#define	GTH34_QPLL_REFCLK_DIV(xcvr, x)
#define	GTY4_QPLL_CLKOUT_RATE(xcvr, x)

Functions
int	xilinx_xcvr_drp_update (struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t reg, uint32_t mask, uint32_t val)
int	xilinx_xcvr_configure_cdr (struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t lane_rate, uint32_t out_div, bool lpm_enable)
int	xilinx_xcvr_configure_lpm_dfe_mode (struct xilinx_xcvr *xcvr, uint32_t drp_port, bool lpm)
int	xilinx_xcvr_calc_cpll_config (struct xilinx_xcvr *xcvr, uint32_t refclk_khz, uint32_t lane_rate_khz, struct xilinx_xcvr_cpll_config *conf, uint32_t *out_div)
int	xilinx_xcvr_calc_qpll_config (struct xilinx_xcvr *xcvr, uint32_t sys_clk_sel, uint32_t refclk_khz, uint32_t lane_rate_khz, struct xilinx_xcvr_qpll_config *conf, uint32_t *out_div)
int	xilinx_xcvr_gtx2_cpll_read_config (struct xilinx_xcvr *xcvr, uint32_t drp_port, struct xilinx_xcvr_cpll_config *conf)
int	xilinx_xcvr_cpll_read_config (struct xilinx_xcvr *xcvr, uint32_t drp_port, struct xilinx_xcvr_cpll_config *conf)
int	xilinx_xcvr_cpll_write_config (struct xilinx_xcvr *xcvr, uint32_t drp_port, const struct xilinx_xcvr_cpll_config *conf)
int	xilinx_xcvr_cpll_calc_lane_rate (struct xilinx_xcvr *xcvr, uint32_t refclk_hz, const struct xilinx_xcvr_cpll_config *conf, uint32_t out_div)
int	xilinx_xcvr_qpll_read_config (struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t sys_clk_sel, struct xilinx_xcvr_qpll_config *conf)
int	xilinx_xcvr_qpll_write_config (struct xilinx_xcvr *xcvr, uint32_t sys_clk_sel, uint32_t drp_port, const struct xilinx_xcvr_qpll_config *conf)
int	xilinx_xcvr_qpll_calc_lane_rate (struct xilinx_xcvr *xcvr, uint32_t refclk_hz, const struct xilinx_xcvr_qpll_config *conf, uint32_t out_div)
int	xilinx_xcvr_read_out_div (struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t *rx_out_div, uint32_t *tx_out_div)
int	xilinx_xcvr_write_out_div (struct xilinx_xcvr *xcvr, uint32_t drp_port, int32_t rx_out_div, int32_t tx_out_div)
int	xilinx_xcvr_write_prog_div (struct xilinx_xcvr *xcvr, uint32_t drp_port, int32_t rx_prog_div, int32_t tx_prog_div)
int	xilinx_xcvr_write_prog_div_rate (struct xilinx_xcvr *xcvr, uint32_t drp_port, int32_t rx_rate, int32_t tx_rate)
int	xilinx_xcvr_write_async_gearbox_en (struct xilinx_xcvr *xcvr, uint32_t drp_port, bool en)
int	xilinx_xcvr_write_rx_clk25_div (struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t div)
int	xilinx_xcvr_write_tx_clk25_div (struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t div)
int	xilinx_xcvr_prbsel_enc_get (struct xilinx_xcvr *xcvr, uint32_t prbs, bool reverse_lu)
int	xilinx_xcvr_prbs_err_cnt_get (struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t *cnt)

Detailed Description

Driver for the Xilinx High-speed transceiver dynamic reconfiguration.

Author

DBogdan (drago.nosp@m.s.bo.nosp@m.gdan@.nosp@m.anal.nosp@m.og.co.nosp@m.m)

Copyright 2018(c) Analog Devices, Inc.

SPDX-License-Identifier: BSD-3-Clause

Macro Definition Documentation

CPLL_CFG0_ADDR

#define CPLL_CFG0_ADDR   0x5c

CPLL_CFG0_MASK

#define CPLL_CFG0_MASK   0xff00

CPLL_CFG1_ADDR

#define CPLL_CFG1_ADDR   0x5d

CPLL_CFG1_MASK

#define CPLL_CFG1_MASK   0xffff

CPLL_FB_DIV_45_N1_MASK

#define CPLL_FB_DIV_45_N1_MASK   0x0080

CPLL_FBDIV_N2_MASK

#define CPLL_FBDIV_N2_MASK   0x007f

CPLL_REFCLK_DIV_M_ADDR

#define CPLL_REFCLK_DIV_M_ADDR   0x5e

CPLL_REFCLK_DIV_M_MASK

#define CPLL_REFCLK_DIV_M_MASK   0x1f00

GTH34_QPLL_FBDIV

#define GTH34_QPLL_FBDIV	(		xcvr,
			x )

Value:

    (0x14 + xilinx_xcvr_qpll_sel((xcvr), (x)) * 0x80)

GTH34_QPLL_REFCLK_DIV

#define GTH34_QPLL_REFCLK_DIV	(		xcvr,
			x )

Value:

    (0x18 + xilinx_xcvr_qpll_sel((xcvr), (x)) * 0x80)

GTH34_SYSCLK_QPLL1

#define GTH34_SYSCLK_QPLL1   2

GTH3_RX_PRBS_ERR_CNT

#define GTH3_RX_PRBS_ERR_CNT   0x15E /* 32-bit */

GTH4_RX_PRBS_ERR_CNT

#define GTH4_RX_PRBS_ERR_CNT   0x25E /* 32-bit also applied for GTY */

GTX_RX_PRBS_ERR_CNT

#define GTX_RX_PRBS_ERR_CNT   0x15c /* 16-bit */

GTY4_QPLL_CLKOUT_RATE

#define GTY4_QPLL_CLKOUT_RATE	(		xcvr,
			x )

Value:

    (0x0E + xilinx_xcvr_qpll_sel((xcvr), (x)) * 0x80)

OUT_DIV_ADDR

#define OUT_DIV_ADDR   0x88

OUT_DIV_RX_OFFSET

#define OUT_DIV_RX_OFFSET   0x0

OUT_DIV_TX_OFFSET

#define OUT_DIV_TX_OFFSET   0x4

QPLL_CFG0_ADDR

#define QPLL_CFG0_ADDR   0x32

QPLL_CFG0_LOWBAND_MASK

#define QPLL_CFG0_LOWBAND_MASK   0x0040

QPLL_CFG1_ADDR

#define QPLL_CFG1_ADDR   0x33

QPLL_FBDIV_N_ADDR

#define QPLL_FBDIV_N_ADDR   0x36

QPLL_FBDIV_N_MASK

#define QPLL_FBDIV_N_MASK   0x03ff

QPLL_FBDIV_RATIO_ADDR

#define QPLL_FBDIV_RATIO_ADDR   0x37

QPLL_FBDIV_RATIO_MASK

#define QPLL_FBDIV_RATIO_MASK   0x0040

QPLL_REFCLK_DIV_M

#define QPLL_REFCLK_DIV_M

(

x

)

Value:

((x) << 11)

QPLL_REFCLK_DIV_M_MASK

#define QPLL_REFCLK_DIV_M_MASK   0xf800

QPLL_REFCLK_DIV_M_OFFSET

#define QPLL_REFCLK_DIV_M_OFFSET   11

RX_CLK25_DIV

#define RX_CLK25_DIV   0x11

RX_CLK25_DIV_MASK

#define RX_CLK25_DIV_MASK   0x07c0

RX_CLK25_DIV_OFFSET

#define RX_CLK25_DIV_OFFSET   6

RX_DFE_LPM_CFG_ADDR

#define RX_DFE_LPM_CFG_ADDR   0x29

RX_DFE_LPM_CFG_MASK

#define RX_DFE_LPM_CFG_MASK   0xffff

RXCDR_CFG0_ADDR

#define RXCDR_CFG0_ADDR   0xa8

RXCDR_CFG0_MASK

#define RXCDR_CFG0_MASK   0xffff

RXCDR_CFG1_ADDR

#define RXCDR_CFG1_ADDR   0xa9

RXCDR_CFG1_MASK

#define RXCDR_CFG1_MASK   0xffff

RXCDR_CFG2_ADDR

#define RXCDR_CFG2_ADDR   0xaa

RXCDR_CFG2_MASK

#define RXCDR_CFG2_MASK   0xffff

RXCDR_CFG3_ADDR

#define RXCDR_CFG3_ADDR   0xab

RXCDR_CFG3_MASK

#define RXCDR_CFG3_MASK   0xffff

RXCDR_CFG4_ADDR

#define RXCDR_CFG4_ADDR   0xac

RXCDR_CFG4_MASK

#define RXCDR_CFG4_MASK   0x00ff

TX_CLK25_DIV

#define TX_CLK25_DIV   0x6a

TX_CLK25_DIV_MASK

#define TX_CLK25_DIV_MASK   0x1f

Function Documentation

xilinx_xcvr_calc_cpll_config()

int xilinx_xcvr_calc_cpll_config	(	struct xilinx_xcvr *	xcvr,
		uint32_t	refclk_khz,
		uint32_t	lane_rate_khz,
		struct xilinx_xcvr_cpll_config *	conf,
		uint32_t *	out_div )

Configure Channel PLL.

Ref: https://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf Page: 48 Vco_Freq = (RefClk * n1 * n2) / m LineRate = (Vco_Freq * 2) / d

xilinx_xcvr_calc_qpll_config()

int xilinx_xcvr_calc_qpll_config	(	struct xilinx_xcvr *	xcvr,
		uint32_t	sys_clk_sel,
		uint32_t	refclk_khz,
		uint32_t	lane_rate_khz,
		struct xilinx_xcvr_qpll_config *	conf,
		uint32_t *	out_div )

Calculate Quad PLL configuration parameters.

Ref: https://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf Page: 55 Vco_Freq = (refclk_khz * n) / m LineRate = Vco_Freq / d

Make sure to not confuse Vco_Freq with fPLLClkout. fPLLClkout = (refclk_khz * n) / (m * 2), so technically Vco_Freq = 2 * fPLLClkout And the 2 is reduced in both equations.

Ref: https://www.xilinx.com/support/documentation/user_guides/ug578-ultrascale-gty-transceivers.pdf Page: 49 For GTY4: LineRate = (2 * Vco_Freq) / d Try Full-rate

xilinx_xcvr_configure_cdr()

int xilinx_xcvr_configure_cdr	(	struct xilinx_xcvr *	xcvr,
		uint32_t	drp_port,
		uint32_t	lane_rate,
		uint32_t	out_div,
		bool	lpm_enable )

Configure the Clock Data Recovery circuit.

xilinx_xcvr_configure_lpm_dfe_mode()

int xilinx_xcvr_configure_lpm_dfe_mode	(	struct xilinx_xcvr *	xcvr,
		uint32_t	drp_port,
		bool	lpm )

Selection of Low-Power mode (LPM) or Decision Feedback Equalization (DFE).

xilinx_xcvr_cpll_calc_lane_rate()

int xilinx_xcvr_cpll_calc_lane_rate	(	struct xilinx_xcvr *	xcvr,
		uint32_t	refclk_hz,
		const struct xilinx_xcvr_cpll_config *	conf,
		uint32_t	out_div )

Calculate Channel PLL lane rate.

xilinx_xcvr_cpll_read_config()

int xilinx_xcvr_cpll_read_config	(	struct xilinx_xcvr *	xcvr,
		uint32_t	drp_port,
		struct xilinx_xcvr_cpll_config *	conf )

Read Channel PLL configuration.

xilinx_xcvr_cpll_write_config()

int xilinx_xcvr_cpll_write_config	(	struct xilinx_xcvr *	xcvr,
		uint32_t	drp_port,
		const struct xilinx_xcvr_cpll_config *	conf )

Write Channel PLL configuration.

xilinx_xcvr_drp_update()

int xilinx_xcvr_drp_update	(	struct xilinx_xcvr *	xcvr,
		uint32_t	drp_port,
		uint32_t	reg,
		uint32_t	mask,
		uint32_t	val )

xilinx_xcvr_gtx2_cpll_read_config()

int xilinx_xcvr_gtx2_cpll_read_config	(	struct xilinx_xcvr *	xcvr,
		uint32_t	drp_port,
		struct xilinx_xcvr_cpll_config *	conf )

xilinx_xcvr_prbs_err_cnt_get()

int xilinx_xcvr_prbs_err_cnt_get	(	struct xilinx_xcvr *	xcvr,
		uint32_t	drp_port,
		uint32_t *	cnt )

Get PRBS error counter value.

xilinx_xcvr_prbsel_enc_get()

int xilinx_xcvr_prbsel_enc_get	(	struct xilinx_xcvr *	xcvr,
		uint32_t	prbs,
		bool	reverse_lu )

Get PRBS generator test pattern control setting.

xilinx_xcvr_qpll_calc_lane_rate()

int xilinx_xcvr_qpll_calc_lane_rate	(	struct xilinx_xcvr *	xcvr,
		uint32_t	refclk_hz,
		const struct xilinx_xcvr_qpll_config *	conf,
		uint32_t	out_div )

Calculate Quad PLL lane rate.

xilinx_xcvr_qpll_read_config()

int xilinx_xcvr_qpll_read_config	(	struct xilinx_xcvr *	xcvr,
		uint32_t	drp_port,
		uint32_t	sys_clk_sel,
		struct xilinx_xcvr_qpll_config *	conf )

Read Quad PLL configuration.

xilinx_xcvr_qpll_write_config()

int xilinx_xcvr_qpll_write_config	(	struct xilinx_xcvr *	xcvr,
		uint32_t	sys_clk_sel,
		uint32_t	drp_port,
		const struct xilinx_xcvr_qpll_config *	conf )

Write Quad PLL configuration.

xilinx_xcvr_read_out_div()

int xilinx_xcvr_read_out_div	(	struct xilinx_xcvr *	xcvr,
		uint32_t	drp_port,
		uint32_t *	rx_out_div,
		uint32_t *	tx_out_div )

Read TX/RXOUT_DIV value.

xilinx_xcvr_write_async_gearbox_en()

int xilinx_xcvr_write_async_gearbox_en	(	struct xilinx_xcvr *	xcvr,
		uint32_t	drp_port,
		bool	en )

TX Asynchronous Gearbox.

xilinx_xcvr_write_out_div()

int xilinx_xcvr_write_out_div	(	struct xilinx_xcvr *	xcvr,
		uint32_t	drp_port,
		int32_t	rx_out_div,
		int32_t	tx_out_div )

Write TX/RXOUT_DIV value.

xilinx_xcvr_write_prog_div()

int xilinx_xcvr_write_prog_div	(	struct xilinx_xcvr *	xcvr,
		uint32_t	drp_port,
		int32_t	rx_prog_div,
		int32_t	tx_prog_div )

Write RX/TX programmable divider ratio.

xilinx_xcvr_write_prog_div_rate()

int xilinx_xcvr_write_prog_div_rate	(	struct xilinx_xcvr *	xcvr,
		uint32_t	drp_port,
		int32_t	rx_rate,
		int32_t	tx_rate )

Set programmable divider ratio (RX|TX_PROGDIV_RATE), pre-divider value.

xilinx_xcvr_write_rx_clk25_div()

int xilinx_xcvr_write_rx_clk25_div	(	struct xilinx_xcvr *	xcvr,
		uint32_t	drp_port,
		uint32_t	div )

Write RX_CLK25_DIV value.

xilinx_xcvr_write_tx_clk25_div()

int xilinx_xcvr_write_tx_clk25_div	(	struct xilinx_xcvr *	xcvr,
		uint32_t	drp_port,
		uint32_t	div )

Write RX_CLK25_DIV value.