Driver for the Xilinx High-speed transceiver dynamic reconfiguration. More...

#include <stdint.h>
#include <stdbool.h>

Include dependency graph for xilinx_transceiver.h:

Classes
struct	xilinx_xcvr
	xilinx_xcvr parameters structure. More...

struct	xilinx_xcvr_drp_ops

struct	clk_ops

struct	xilinx_xcvr_cpll_config
	Structure holding CPLL configuration. More...

struct	xilinx_xcvr_qpll_config
	Structure holding QPLL configuration. More...

Macros
#define	AXI_PCORE_VER(major, minor, letter)

#define	AXI_PCORE_VER_MAJOR(version)

#define	AXI_PCORE_VER_MINOR(version)

#define	AXI_PCORE_VER_LETTER(version)

#define	AXI_REG_VERSION 0x0000

#define	AXI_VERSION(x)

#define	AXI_VERSION_IS(x, y, z)

#define	AXI_VERSION_MAJOR(x)

#define	AXI_REG_FPGA_INFO 0x001C

#define	AXI_REG_FPGA_VOLTAGE 0x0140

#define	AXI_INFO_FPGA_TECH(info)

#define	AXI_INFO_FPGA_FAMILY(info)

#define	AXI_INFO_FPGA_SPEED_GRADE(info)

#define	AXI_INFO_FPGA_DEV_PACKAGE(info)

#define	AXI_INFO_FPGA_VOLTAGE(val)

#define	ENC_8B10B 810

#define	ENC_66B64B 6664

Enumerations
enum	xilinx_xcvr_type { XILINX_XCVR_TYPE_S7_GTX2 = 2 , XILINX_XCVR_TYPE_US_GTH3 = 5 , XILINX_XCVR_TYPE_US_GTH4 = 8 , XILINX_XCVR_TYPE_US_GTY4 = 9 }
	Enum for GT type. More...

enum	xilinx_xcvr_legacy_type { XILINX_XCVR_LEGACY_TYPE_S7_GTX2 , XILINX_XCVR_LEGACY_TYPE_US_GTH3 , XILINX_XCVR_LEGACY_TYPE_US_GTH4 , XILINX_XCVR_LEGACY_TYPE_US_GTY4 = 4 }
	Enum for legacy GT type. More...

enum	xilinx_xcvr_refclk_ppm { PM_200 , PM_700 , PM_1250 }
	Enum for reference clock ppm. More...

enum	axi_fgpa_technology { AXI_FPGA_TECH_UNKNOWN = 0 , AXI_FPGA_TECH_SERIES7 , AXI_FPGA_TECH_ULTRASCALE , AXI_FPGA_TECH_ULTRASCALE_PLUS }
	Enum for technology/generation of the FPGA device. More...

enum	axi_fpga_family { AXI_FPGA_FAMILY_UNKNOWN = 0 , AXI_FPGA_FAMILY_ARTIX , AXI_FPGA_FAMILY_KINTEX , AXI_FPGA_FAMILY_VIRTEX , AXI_FPGA_FAMILY_ZYNQ }
	Enum for family variant of the FPGA device. More...

enum	axi_fpga_speed_grade { AXI_FPGA_SPEED_UNKNOWN = 0 , AXI_FPGA_SPEED_1 = 10 , AXI_FPGA_SPEED_1L = 11 , AXI_FPGA_SPEED_1H = 12 , AXI_FPGA_SPEED_1HV = 13 , AXI_FPGA_SPEED_1LV = 14 , AXI_FPGA_SPEED_2 = 20 , AXI_FPGA_SPEED_2L = 21 , AXI_FPGA_SPEED_2LV = 22 , AXI_FPGA_SPEED_3 = 30 }
	Enum for FPGA's speed-grade. More...

enum	axi_fpga_dev_pack { AXI_FPGA_DEV_UNKNOWN = 0 , AXI_FPGA_DEV_RF , AXI_FPGA_DEV_FL , AXI_FPGA_DEV_FF , AXI_FPGA_DEV_FB , AXI_FPGA_DEV_HC , AXI_FPGA_DEV_FH , AXI_FPGA_DEV_CS , AXI_FPGA_DEV_CP , AXI_FPGA_DEV_FT , AXI_FPGA_DEV_FG , AXI_FPGA_DEV_SB , AXI_FPGA_DEV_RB , AXI_FPGA_DEV_RS , AXI_FPGA_DEV_CL , AXI_FPGA_DEV_SF , AXI_FPGA_DEV_BA , AXI_FPGA_DEV_FA }
	Enum for device package. More...

Functions
int	xilinx_xcvr_configure_cdr (struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t lane_rate, uint32_t out_div, bool lpm_enable)

int	xilinx_xcvr_configure_lpm_dfe_mode (struct xilinx_xcvr *xcvr, uint32_t drp_port, bool lpm)

int	xilinx_xcvr_calc_cpll_config (struct xilinx_xcvr xcvr, uint32_t refclk_khz, uint32_t lane_rate_khz, struct xilinx_xcvr_cpll_config conf, uint32_t *out_div)

int	xilinx_xcvr_cpll_read_config (struct xilinx_xcvr xcvr, uint32_t drp_port, struct xilinx_xcvr_cpll_config conf)

int	xilinx_xcvr_cpll_write_config (struct xilinx_xcvr xcvr, uint32_t drp_port, const struct xilinx_xcvr_cpll_config conf)

int	xilinx_xcvr_cpll_calc_lane_rate (struct xilinx_xcvr xcvr, uint32_t refclk_hz, const struct xilinx_xcvr_cpll_config conf, uint32_t out_div)

int	xilinx_xcvr_calc_qpll_config (struct xilinx_xcvr xcvr, uint32_t sys_clk_sel, uint32_t refclk_khz, uint32_t lane_rate_khz, struct xilinx_xcvr_qpll_config conf, uint32_t *out_div)

int	xilinx_xcvr_qpll_read_config (struct xilinx_xcvr xcvr, uint32_t drp_port, uint32_t sys_clk_sel, struct xilinx_xcvr_qpll_config conf)

int	xilinx_xcvr_qpll_write_config (struct xilinx_xcvr xcvr, uint32_t sys_clk_sel, uint32_t drp_port, const struct xilinx_xcvr_qpll_config conf)

int	xilinx_xcvr_qpll_calc_lane_rate (struct xilinx_xcvr xcvr, uint32_t refclk_hz, const struct xilinx_xcvr_qpll_config conf, uint32_t out_div)

int	xilinx_xcvr_read_out_div (struct xilinx_xcvr xcvr, uint32_t drp_port, uint32_t rx_out_div, uint32_t *tx_out_div)

int	xilinx_xcvr_write_out_div (struct xilinx_xcvr *xcvr, uint32_t drp_port, int32_t rx_out_div, int32_t tx_out_div)

int	xilinx_xcvr_write_rx_clk25_div (struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t div)

int	xilinx_xcvr_write_tx_clk25_div (struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t div)

int	xilinx_xcvr_prbsel_enc_get (struct xilinx_xcvr *xcvr, uint32_t prbs, bool reverse_lu)

int	xilinx_xcvr_prbs_err_cnt_get (struct xilinx_xcvr xcvr, uint32_t drp_port, uint32_t cnt)

int	xilinx_xcvr_write_prog_div_rate (struct xilinx_xcvr *xcvr, uint32_t drp_port, int32_t rx_rate, int32_t tx_rate)

int	xilinx_xcvr_write_prog_div (struct xilinx_xcvr *xcvr, uint32_t drp_port, int32_t rx_prog_div, int32_t tx_prog_div)

int	xilinx_xcvr_write_async_gearbox_en (struct xilinx_xcvr *xcvr, uint32_t drp_port, bool en)

Detailed Description

Driver for the Xilinx High-speed transceiver dynamic reconfiguration.

Author: DBogdan (drago.nosp@m.s.bo.nosp@m.gdan@.nosp@m.anal.nosp@m.og.co.nosp@m.m)

SPDX-License-Identifier: BSD-3-Clause

Macro Definition Documentation

◆ AXI_INFO_FPGA_DEV_PACKAGE

#define AXI_INFO_FPGA_DEV_PACKAGE ( info )

Value:

((info) & 0xff)

◆ AXI_INFO_FPGA_FAMILY

#define AXI_INFO_FPGA_FAMILY ( info )

Value:

(((info) >> 16) & 0xff)

◆ AXI_INFO_FPGA_SPEED_GRADE

#define AXI_INFO_FPGA_SPEED_GRADE ( info )

Value:

(((info) >> 8) & 0xff)

◆ AXI_INFO_FPGA_TECH

#define AXI_INFO_FPGA_TECH ( info )

Value:

((info) >> 24)

◆ AXI_INFO_FPGA_VOLTAGE

#define AXI_INFO_FPGA_VOLTAGE ( val )

Value:

((val) & 0xffff)

◆ AXI_PCORE_VER

#define AXI_PCORE_VER	(	major,
		minor,
		letter )

Value:

((major << 16) | (minor << 8) | letter)

◆ AXI_PCORE_VER_LETTER

#define AXI_PCORE_VER_LETTER ( version )

Value:

(version & 0xff)

◆ AXI_PCORE_VER_MAJOR

#define AXI_PCORE_VER_MAJOR ( version )

Value:

(((version) >> 16) & 0xff)

◆ AXI_PCORE_VER_MINOR

#define AXI_PCORE_VER_MINOR ( version )

Value:

((version >> 8) & 0xff)

◆ AXI_REG_FPGA_INFO

#define AXI_REG_FPGA_INFO 0x001C

◆ AXI_REG_FPGA_VOLTAGE

#define AXI_REG_FPGA_VOLTAGE 0x0140

◆ AXI_REG_VERSION

#define AXI_REG_VERSION 0x0000

◆ AXI_VERSION

#define AXI_VERSION ( x )

Value:

(((x) & 0xffffffff) << 0)

◆ AXI_VERSION_IS

#define AXI_VERSION_IS	(	x,
		y,
		z )

Value:

((x) << 16 | (y) << 8 | (z))

◆ AXI_VERSION_MAJOR

#define AXI_VERSION_MAJOR ( x )

Value:

((x) >> 16)

◆ ENC_66B64B

#define ENC_66B64B 6664

◆ ENC_8B10B

#define ENC_8B10B 810

Enumeration Type Documentation

◆ axi_fgpa_technology

enum axi_fgpa_technology

Enum for technology/generation of the FPGA device.

Enumerator
AXI_FPGA_TECH_UNKNOWN
AXI_FPGA_TECH_SERIES7
AXI_FPGA_TECH_ULTRASCALE
AXI_FPGA_TECH_ULTRASCALE_PLUS

◆ axi_fpga_dev_pack

enum axi_fpga_dev_pack

Enum for device package.

Enumerator
AXI_FPGA_DEV_UNKNOWN
AXI_FPGA_DEV_RF
AXI_FPGA_DEV_FL
AXI_FPGA_DEV_FF
AXI_FPGA_DEV_FB
AXI_FPGA_DEV_HC
AXI_FPGA_DEV_FH
AXI_FPGA_DEV_CS
AXI_FPGA_DEV_CP
AXI_FPGA_DEV_FT
AXI_FPGA_DEV_FG
AXI_FPGA_DEV_SB
AXI_FPGA_DEV_RB
AXI_FPGA_DEV_RS
AXI_FPGA_DEV_CL
AXI_FPGA_DEV_SF
AXI_FPGA_DEV_BA
AXI_FPGA_DEV_FA

◆ axi_fpga_family

enum axi_fpga_family

Enum for family variant of the FPGA device.

Enumerator
AXI_FPGA_FAMILY_UNKNOWN
AXI_FPGA_FAMILY_ARTIX
AXI_FPGA_FAMILY_KINTEX
AXI_FPGA_FAMILY_VIRTEX
AXI_FPGA_FAMILY_ZYNQ

◆ axi_fpga_speed_grade

enum axi_fpga_speed_grade

Enum for FPGA's speed-grade.

Enumerator
AXI_FPGA_SPEED_UNKNOWN
AXI_FPGA_SPEED_1
AXI_FPGA_SPEED_1L
AXI_FPGA_SPEED_1H
AXI_FPGA_SPEED_1HV
AXI_FPGA_SPEED_1LV
AXI_FPGA_SPEED_2
AXI_FPGA_SPEED_2L
AXI_FPGA_SPEED_2LV
AXI_FPGA_SPEED_3

◆ xilinx_xcvr_legacy_type

enum xilinx_xcvr_legacy_type

Enum for legacy GT type.

Enumerator
XILINX_XCVR_LEGACY_TYPE_S7_GTX2
XILINX_XCVR_LEGACY_TYPE_US_GTH3
XILINX_XCVR_LEGACY_TYPE_US_GTH4
XILINX_XCVR_LEGACY_TYPE_US_GTY4

◆ xilinx_xcvr_refclk_ppm

enum xilinx_xcvr_refclk_ppm

Enum for reference clock ppm.

Enumerator
PM_200
PM_700
PM_1250

◆ xilinx_xcvr_type

enum xilinx_xcvr_type

Enum for GT type.

Enumerator
XILINX_XCVR_TYPE_S7_GTX2
XILINX_XCVR_TYPE_US_GTH3
XILINX_XCVR_TYPE_US_GTH4
XILINX_XCVR_TYPE_US_GTY4

Function Documentation

◆ xilinx_xcvr_calc_cpll_config()

int xilinx_xcvr_calc_cpll_config	(	struct xilinx_xcvr *	xcvr,
		uint32_t	refclk_khz,
		uint32_t	lane_rate_khz,
		struct xilinx_xcvr_cpll_config *	conf,
		uint32_t *	out_div )

Configure Channel PLL.

Ref: https://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf Page: 48 Vco_Freq = (RefClk * n1 * n2) / m LineRate = (Vco_Freq * 2) / d

◆ xilinx_xcvr_calc_qpll_config()

int xilinx_xcvr_calc_qpll_config	(	struct xilinx_xcvr *	xcvr,
		uint32_t	sys_clk_sel,
		uint32_t	refclk_khz,
		uint32_t	lane_rate_khz,
		struct xilinx_xcvr_qpll_config *	conf,
		uint32_t *	out_div )

Calculate Quad PLL configuration parameters.

Ref: https://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf Page: 55 Vco_Freq = (refclk_khz * n) / m LineRate = Vco_Freq / d

Make sure to not confuse Vco_Freq with fPLLClkout. fPLLClkout = (refclk_khz * n) / (m * 2), so technically Vco_Freq = 2 * fPLLClkout And the 2 is reduced in both equations.

Ref: https://www.xilinx.com/support/documentation/user_guides/ug578-ultrascale-gty-transceivers.pdf Page: 49 For GTY4: LineRate = (2 * Vco_Freq) / d Try Full-rate

◆ xilinx_xcvr_configure_cdr()

int xilinx_xcvr_configure_cdr	(	struct xilinx_xcvr *	xcvr,
		uint32_t	drp_port,
		uint32_t	lane_rate,
		uint32_t	out_div,
		bool	lpm_enable )

Configure the Clock Data Recovery circuit.

◆ xilinx_xcvr_configure_lpm_dfe_mode()

int xilinx_xcvr_configure_lpm_dfe_mode	(	struct xilinx_xcvr *	xcvr,
		uint32_t	drp_port,
		bool	lpm )

Selection of Low-Power mode (LPM) or Decision Feedback Equalization (DFE).

◆ xilinx_xcvr_cpll_calc_lane_rate()

int xilinx_xcvr_cpll_calc_lane_rate	(	struct xilinx_xcvr *	xcvr,
		uint32_t	refclk_hz,
		const struct xilinx_xcvr_cpll_config *	conf,
		uint32_t	out_div )

Calculate Channel PLL lane rate.

◆ xilinx_xcvr_cpll_read_config()

int xilinx_xcvr_cpll_read_config	(	struct xilinx_xcvr *	xcvr,
		uint32_t	drp_port,
		struct xilinx_xcvr_cpll_config *	conf )

Read Channel PLL configuration.

◆ xilinx_xcvr_cpll_write_config()

int xilinx_xcvr_cpll_write_config	(	struct xilinx_xcvr *	xcvr,
		uint32_t	drp_port,
		const struct xilinx_xcvr_cpll_config *	conf )

Write Channel PLL configuration.

◆ xilinx_xcvr_prbs_err_cnt_get()

int xilinx_xcvr_prbs_err_cnt_get	(	struct xilinx_xcvr *	xcvr,
		uint32_t	drp_port,
		uint32_t *	cnt )

Get PRBS error counter value.

◆ xilinx_xcvr_prbsel_enc_get()

int xilinx_xcvr_prbsel_enc_get	(	struct xilinx_xcvr *	xcvr,
		uint32_t	prbs,
		bool	reverse_lu )

Get PRBS generator test pattern control setting.

◆ xilinx_xcvr_qpll_calc_lane_rate()

int xilinx_xcvr_qpll_calc_lane_rate	(	struct xilinx_xcvr *	xcvr,
		uint32_t	refclk_hz,
		const struct xilinx_xcvr_qpll_config *	conf,
		uint32_t	out_div )

Calculate Quad PLL lane rate.

◆ xilinx_xcvr_qpll_read_config()

int xilinx_xcvr_qpll_read_config	(	struct xilinx_xcvr *	xcvr,
		uint32_t	drp_port,
		uint32_t	sys_clk_sel,
		struct xilinx_xcvr_qpll_config *	conf )

Read Quad PLL configuration.

◆ xilinx_xcvr_qpll_write_config()

int xilinx_xcvr_qpll_write_config	(	struct xilinx_xcvr *	xcvr,
		uint32_t	sys_clk_sel,
		uint32_t	drp_port,
		const struct xilinx_xcvr_qpll_config *	conf )

Write Quad PLL configuration.

◆ xilinx_xcvr_read_out_div()

int xilinx_xcvr_read_out_div	(	struct xilinx_xcvr *	xcvr,
		uint32_t	drp_port,
		uint32_t *	rx_out_div,
		uint32_t *	tx_out_div )

Read TX/RXOUT_DIV value.

◆ xilinx_xcvr_write_async_gearbox_en()

int xilinx_xcvr_write_async_gearbox_en	(	struct xilinx_xcvr *	xcvr,
		uint32_t	drp_port,
		bool	en )

TX Asynchronous Gearbox.

◆ xilinx_xcvr_write_out_div()

int xilinx_xcvr_write_out_div	(	struct xilinx_xcvr *	xcvr,
		uint32_t	drp_port,
		int32_t	rx_out_div,
		int32_t	tx_out_div )

Write TX/RXOUT_DIV value.

◆ xilinx_xcvr_write_prog_div()

int xilinx_xcvr_write_prog_div	(	struct xilinx_xcvr *	xcvr,
		uint32_t	drp_port,
		int32_t	rx_prog_div,
		int32_t	tx_prog_div )

Write RX/TX programmable divider ratio.

◆ xilinx_xcvr_write_prog_div_rate()

int xilinx_xcvr_write_prog_div_rate	(	struct xilinx_xcvr *	xcvr,
		uint32_t	drp_port,
		int32_t	rx_rate,
		int32_t	tx_rate )

Set programmable divider ratio (RX|TX_PROGDIV_RATE), pre-divider value.

◆ xilinx_xcvr_write_rx_clk25_div()

int xilinx_xcvr_write_rx_clk25_div	(	struct xilinx_xcvr *	xcvr,
		uint32_t	drp_port,
		uint32_t	div )

Write RX_CLK25_DIV value.

◆ xilinx_xcvr_write_tx_clk25_div()

int xilinx_xcvr_write_tx_clk25_div	(	struct xilinx_xcvr *	xcvr,
		uint32_t	drp_port,
		uint32_t	div )

Write RX_CLK25_DIV value.

Classes

Macros

Enumerations

Functions

Detailed Description

Macro Definition Documentation

◆ AXI_INFO_FPGA_DEV_PACKAGE

◆ AXI_INFO_FPGA_FAMILY

◆ AXI_INFO_FPGA_SPEED_GRADE

◆ AXI_INFO_FPGA_TECH

◆ AXI_INFO_FPGA_VOLTAGE

◆ AXI_PCORE_VER

◆ AXI_PCORE_VER_LETTER

◆ AXI_PCORE_VER_MAJOR

◆ AXI_PCORE_VER_MINOR

◆ AXI_REG_FPGA_INFO

◆ AXI_REG_FPGA_VOLTAGE

◆ AXI_REG_VERSION

◆ AXI_VERSION

◆ AXI_VERSION_IS

◆ AXI_VERSION_MAJOR

◆ ENC_66B64B

◆ ENC_8B10B

Enumeration Type Documentation

◆ axi_fgpa_technology

◆ axi_fpga_dev_pack

◆ axi_fpga_family

◆ axi_fpga_speed_grade

◆ xilinx_xcvr_legacy_type

◆ xilinx_xcvr_refclk_ppm

◆ xilinx_xcvr_type

Function Documentation

◆ xilinx_xcvr_calc_cpll_config()

◆ xilinx_xcvr_calc_qpll_config()

◆ xilinx_xcvr_configure_cdr()

◆ xilinx_xcvr_configure_lpm_dfe_mode()

◆ xilinx_xcvr_cpll_calc_lane_rate()

◆ xilinx_xcvr_cpll_read_config()

◆ xilinx_xcvr_cpll_write_config()

◆ xilinx_xcvr_prbs_err_cnt_get()

◆ xilinx_xcvr_prbsel_enc_get()

◆ xilinx_xcvr_qpll_calc_lane_rate()

◆ xilinx_xcvr_qpll_read_config()

◆ xilinx_xcvr_qpll_write_config()

◆ xilinx_xcvr_read_out_div()

◆ xilinx_xcvr_write_async_gearbox_en()

◆ xilinx_xcvr_write_out_div()

◆ xilinx_xcvr_write_prog_div()

◆ xilinx_xcvr_write_prog_div_rate()

◆ xilinx_xcvr_write_rx_clk25_div()

◆ xilinx_xcvr_write_tx_clk25_div()