|
| enum | xilinx_xcvr_type {
XILINX_XCVR_TYPE_S7_GTX2 = 2
,
XILINX_XCVR_TYPE_US_GTH3 = 5
,
XILINX_XCVR_TYPE_US_GTH4 = 8
,
XILINX_XCVR_TYPE_US_GTY4 = 9
} |
| | Enum for GT type. More...
|
| |
| enum | xilinx_xcvr_legacy_type {
XILINX_XCVR_LEGACY_TYPE_S7_GTX2
,
XILINX_XCVR_LEGACY_TYPE_US_GTH3
,
XILINX_XCVR_LEGACY_TYPE_US_GTH4
,
XILINX_XCVR_LEGACY_TYPE_US_GTY4 = 4
} |
| | Enum for legacy GT type. More...
|
| |
| enum | xilinx_xcvr_refclk_ppm {
PM_200
,
PM_700
,
PM_1250
} |
| | Enum for reference clock ppm. More...
|
| |
| enum | axi_fgpa_technology {
AXI_FPGA_TECH_UNKNOWN = 0
,
AXI_FPGA_TECH_SERIES7
,
AXI_FPGA_TECH_ULTRASCALE
,
AXI_FPGA_TECH_ULTRASCALE_PLUS
} |
| | Enum for technology/generation of the FPGA device. More...
|
| |
| enum | axi_fpga_family {
AXI_FPGA_FAMILY_UNKNOWN = 0
,
AXI_FPGA_FAMILY_ARTIX
,
AXI_FPGA_FAMILY_KINTEX
,
AXI_FPGA_FAMILY_VIRTEX
,
AXI_FPGA_FAMILY_ZYNQ
} |
| | Enum for family variant of the FPGA device. More...
|
| |
| enum | axi_fpga_speed_grade {
AXI_FPGA_SPEED_UNKNOWN = 0
,
AXI_FPGA_SPEED_1 = 10
,
AXI_FPGA_SPEED_1L = 11
,
AXI_FPGA_SPEED_1H = 12
,
AXI_FPGA_SPEED_1HV = 13
,
AXI_FPGA_SPEED_1LV = 14
,
AXI_FPGA_SPEED_2 = 20
,
AXI_FPGA_SPEED_2L = 21
,
AXI_FPGA_SPEED_2LV = 22
,
AXI_FPGA_SPEED_3 = 30
} |
| | Enum for FPGA's speed-grade. More...
|
| |
| enum | axi_fpga_dev_pack {
AXI_FPGA_DEV_UNKNOWN = 0
,
AXI_FPGA_DEV_RF
,
AXI_FPGA_DEV_FL
,
AXI_FPGA_DEV_FF
,
AXI_FPGA_DEV_FB
,
AXI_FPGA_DEV_HC
,
AXI_FPGA_DEV_FH
,
AXI_FPGA_DEV_CS
,
AXI_FPGA_DEV_CP
,
AXI_FPGA_DEV_FT
,
AXI_FPGA_DEV_FG
,
AXI_FPGA_DEV_SB
,
AXI_FPGA_DEV_RB
,
AXI_FPGA_DEV_RS
,
AXI_FPGA_DEV_CL
,
AXI_FPGA_DEV_SF
,
AXI_FPGA_DEV_BA
,
AXI_FPGA_DEV_FA
} |
| | Enum for device package. More...
|
| |
|
| int | xilinx_xcvr_configure_cdr (struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t lane_rate, uint32_t out_div, bool lpm_enable) |
| |
| int | xilinx_xcvr_configure_lpm_dfe_mode (struct xilinx_xcvr *xcvr, uint32_t drp_port, bool lpm) |
| |
| int | xilinx_xcvr_calc_cpll_config (struct xilinx_xcvr *xcvr, uint32_t refclk_khz, uint32_t lane_rate_khz, struct xilinx_xcvr_cpll_config *conf, uint32_t *out_div) |
| |
| int | xilinx_xcvr_cpll_read_config (struct xilinx_xcvr *xcvr, uint32_t drp_port, struct xilinx_xcvr_cpll_config *conf) |
| |
| int | xilinx_xcvr_cpll_write_config (struct xilinx_xcvr *xcvr, uint32_t drp_port, const struct xilinx_xcvr_cpll_config *conf) |
| |
| int | xilinx_xcvr_cpll_calc_lane_rate (struct xilinx_xcvr *xcvr, uint32_t refclk_hz, const struct xilinx_xcvr_cpll_config *conf, uint32_t out_div) |
| |
| int | xilinx_xcvr_calc_qpll_config (struct xilinx_xcvr *xcvr, uint32_t sys_clk_sel, uint32_t refclk_khz, uint32_t lane_rate_khz, struct xilinx_xcvr_qpll_config *conf, uint32_t *out_div) |
| |
| int | xilinx_xcvr_qpll_read_config (struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t sys_clk_sel, struct xilinx_xcvr_qpll_config *conf) |
| |
| int | xilinx_xcvr_qpll_write_config (struct xilinx_xcvr *xcvr, uint32_t sys_clk_sel, uint32_t drp_port, const struct xilinx_xcvr_qpll_config *conf) |
| |
| int | xilinx_xcvr_qpll_calc_lane_rate (struct xilinx_xcvr *xcvr, uint32_t refclk_hz, const struct xilinx_xcvr_qpll_config *conf, uint32_t out_div) |
| |
| int | xilinx_xcvr_read_out_div (struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t *rx_out_div, uint32_t *tx_out_div) |
| |
| int | xilinx_xcvr_write_out_div (struct xilinx_xcvr *xcvr, uint32_t drp_port, int32_t rx_out_div, int32_t tx_out_div) |
| |
| int | xilinx_xcvr_write_rx_clk25_div (struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t div) |
| |
| int | xilinx_xcvr_write_tx_clk25_div (struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t div) |
| |
| int | xilinx_xcvr_prbsel_enc_get (struct xilinx_xcvr *xcvr, uint32_t prbs, bool reverse_lu) |
| |
| int | xilinx_xcvr_prbs_err_cnt_get (struct xilinx_xcvr *xcvr, uint32_t drp_port, uint32_t *cnt) |
| |
| int | xilinx_xcvr_write_prog_div_rate (struct xilinx_xcvr *xcvr, uint32_t drp_port, int32_t rx_rate, int32_t tx_rate) |
| |
| int | xilinx_xcvr_write_prog_div (struct xilinx_xcvr *xcvr, uint32_t drp_port, int32_t rx_prog_div, int32_t tx_prog_div) |
| |
| int | xilinx_xcvr_write_async_gearbox_en (struct xilinx_xcvr *xcvr, uint32_t drp_port, bool en) |
| |
Driver for the Xilinx High-speed transceiver dynamic reconfiguration.
- Author
- DBogdan (drago.nosp@m.s.bo.nosp@m.gdan@.nosp@m.anal.nosp@m.og.co.nosp@m.m)
Copyright 2018(c) Analog Devices, Inc.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
- Neither the name of Analog Devices, Inc. nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
