adi.Phaser

The adi.Phaser system object is an API to control the
ADALM-PHASER X/Ku Band Beamforming Developer Platform.

rx = adi.Phaser;
rx = adi.Phaser('uri','ip:ip:192.168.2.1');

Stingray X/Ku Band Beamforming Developer Platform Wiki

Creation

The class can be instantiated in the following way with and without property name value pairs.

dev = adi.Phaser
dev = adi.Phaser(Name, Value)

Properties

Unless otherwise indicated, properties are non-tunable, which means you cannot change their values after calling the object. Objects lock when you call them, and the release function unlocks them.

If a property is tunable, you can change its value at any time.

For more information on changing property values, see System Design in MATLAB Using System Objects.

EnablePLL +

Enable onboard PLL which is the main LO source. This controls V_CTRL_1

EnableTxPLL +

Enable PLL to feed the Tx LO. This controls V_CTRL_2

NumADAR1000s +

Mode +

Mode is a cellarray where each element addresses individual ADAR1000's. Each cell must contain a string of value 'Rx', 'Tx', or 'disabled' to set the modes.

LNABiasOutEnable +

Enable output of LNA bias DAC. LNABiasOutEnable is an array where each element addresses individual ADAR1000's. Each element must be a logical true (to enable) or false (to not enable).

LNABiasOn +

External Bias for External LNAs. LNABiasOn is an array where each element addresses individual ADAR1000's.

BeamMemEnable +

Enable beam memory. BeamMemEnable is an array where each element addresses individual ADAR1000's. Each element must be a logical true (to enable) or false (to not enable).

BiasDACEnable +

Enable PA and LNA bias DACs. BiasDACEnable is an array where each element addresses individual ADAR1000's. Each element must be a logical true (to enable) or false (to not enable).

BiasDACMode +

External Amplifier Bias Control. BiasDACMode is a cellarray where each element addresses individual ADAR1000's. Each cell must contain a string of values 'On' or 'Off' to set the modes.

BiasMemEnable +

Enable bias memory. BiasMemEnable is an array where each element addresses individual ADAR1000's. Each element must be a logical true (to enable) or false (to not enable).

CommonMemEnable +

CommonMemEnable is an array where each element addresses individual ADAR1000's. Each element must be a logical true (to enable) or false (to not enable).

CommonRxBeamState +

Static Rx Beam Position Load. CommonRxBeamState is an array where each element addresses individual ADAR1000's.

CommonTxBeamState +

Static Tx Beam Position Load. CommonTxBeamState is an array where each element addresses individual ADAR1000's.

ExternalTRPin +

Select Tx/Rx output driver. TxRxSwitchControl is a cellarray where each element addresses individual ADAR1000's. Each cell must contain a string of values 'Pos' or 'Neg' to set the modes.

ExternalTRPolarity +

Controls Sense of Tx/Rx Switch Driver Output. ExternalTRPolarity is an array where each element addresses individual ADAR1000's. Each element must be a logical true (to enable) or false (to not enable).

LNABiasOff +

External Bias for External LNAs. LNABiasOff is an array where each element addresses individual ADAR1000's.

PolState +

Control for External Polarity Switch Drivers. PolSwitchEnable is an array where each element addresses individual ADAR1000's. Each element must be a logical true (to enable) or false (to not enable).

PolSwitchEnable +

Enables Switch Driver for External Polarization Switch. PolSwitchEnable is an array where each element addresses individual ADAR1000's. Each element must be a logical true (to enable) or false (to not enable).

RxLNABiasCurrent +

Set LNA bias current. RxLNABiasCurrent is an array where each element addresses individual ADAR1000's.

RxLNAEnable +

Enables Rx LNA. RxLNAEnable is an array where each element addresses individual ADAR1000's. Each element must be a logical true (to enable) or false (to not enable).

RxToTxDelay1 +

LNA Bias off to TR Switch Delay. RxToTxDelay1 is an array where each element addresses individual ADAR1000's.

RxToTxDelay2 +

TR Switch to PA Bias on Delay. RxToTxDelay2 is an array where each element addresses individual ADAR1000's.

RxVGAEnable +

Enable Rx Channel VGAs. RxVGAEnable is an array where each element addresses individual ADAR1000's. Each element must be a logical true (to enable) or false (to not enable).

RxVGABiasCurrentVM +

Apply Rx bias current. RxVGABiasCurrentVM is an array where each element addresses individual ADAR1000's.

RxVMEnable +

Enable Rx Channel Vector Modulators. RxVMEnable is an array where each element addresses individual ADAR1000's. Each element must be a logical true (to enable) or false (to not enable).

SequencerEnable +

Enable sequencer. Sequencer is an array where each element addresses individual ADAR1000's. Each element must be a logical true (to enable) or false (to not enable).

TRSwitchEnable +

Enables Switch Driver for External Tx/Rx Switch. TRSwitchEnable is an array where each element addresses individual ADAR1000's. Each element must be a logical true (to enable) or false (to not enable).

TxPABiasCurrent +

Set Tx driver bias current. TxPABiasCurrent is an array where each element addresses individual ADAR1000's.

TxPAEnable +

Enables the Tx channel drivers. TxToRxDelay1 is an array where each element addresses individual ADAR1000's. Each element must be a logical true (to enable) or false (to not enable).

TxToRxDelay1 +

PA Bias off to TR Switch Delay. TxToRxDelay1 is an array where each element addresses individual ADAR1000's.

TxToRxDelay2 +

TR Switch to LNA Bias on Delay. TxToRxDelay2 is an array where each element addresses individual ADAR1000's.

TxVGAEnable +

Enable Tx Channel VGAs. TxVGAEnable is an array where each element addresses individual ADAR1000's. Each element must be a logical true (to enable) or false (to not enable).

TxVGABiasCurrentVM +

Apply Tx bias current. TxVGABiasCurrentVM is an array where each element addresses individual ADAR1000's.

TxVMEnable +

Enable Tx Channel Vector Modulators. TxVMEnable is an array where each element addresses individual ADAR1000's. Each element must be a logical true (to enable) or false (to not enable).

TxRxSwitchControl +

Set source of control for Rx and Tx switching. TxRxSwitchControl is a cellarray where each element addresses individual ADAR1000's. Each cell must contain a string of values 'spi' or 'external' to set the modes.

DetectorEnable +

DetectorEnable is an array where each element addresses each channel of each ADAR1000.

DetectorPower +

DetectorPower is an array where each element addresses each channel of each ADAR1000.

PABiasOff +

Apply bias off to external PA. PABiasOff is an array where each element addresses each channel of each ADAR1000.

PABiasOn +

Apply bias on to external PA. PABiasOn is an array where each element addresses each channel of each ADAR1000.

RxAttn +

Attenuate Rx channels. RxAttn is an array where each element addresses each channel of each ADAR1000. Each element must be a logical true (to attenuate) or false (to not attenuate).

RxBeamState +

Load Rx Position. RxBeamState is an array where each element addresses each channel of each ADAR1000. Each element must be a value between 0 and 360.

RxPowerDown +

Power down Rx channels. RxPowerDown is a logical array where each element addresses each channel of each ADAR1000. Each element must be a logical false (to power up) or true (to power down).

RxGain +

Apply gain to Rx channels. RxGain is an array where each element addresses each channel of each ADAR1000. Each element must be a value between 0 and 127.

RxPhase +

Apply phase to Rx channels. RxPhase is an array where each element addresses each channel of each ADAR1000. Each element must be a value between 0 and 360.

TxAttn +

Attenuate Tx channels. TxAttn is an array where each element addresses each channel of each ADAR1000. Each element must be a logical true (to attenuate) or false (to not attenuate).

TxBeamState +

Load Tx Position. TxBeamState is an array where each element addresses each channel of each ADAR1000. Each element must be a value between 0 and 360.

TxPowerDown +

Power down Tx channels. TxPowerDown is a logical array where each element addresses each channel of each ADAR1000. Each element must be a logical false (to power up) or true (to power down).

TxGain +

Apply gain to Tx channels. TxGain is an array where each element addresses each channel of each ADAR1000. Each element must be a value between 0 and 127.

TxPhase +

Apply phase to Tx channels. TxPhase is an array where each element addresses each channel of each ADAR1000. Each element must be a value between 0 and 360.

RxSequencerStart +

RxSequencerStart Rx Sequencer Start RxSequencerStart is a logical array where each element addresses each channel of each ADAR1000. Each element must be a logical false or true.

RxSequencerStop +

RxSequencerStop is a logical array where each element addresses each channel of each ADAR1000. Each element must be a logical false or true.

TxSequencerStart +

TxSequencerStart Tx Sequencer Start TxSequencerStart is a logical array where each element addresses each channel of each ADAR1000. Each element must be a logical false or true.

TxSequencerStop +

TxSequencerStop is a logical array where each element addresses each channel of each ADAR1000. Each element must be a logical false or true.

Temp +

Get temperature of X-band Development Platform.

TargetFrequency +

ADAR1000 target frequency

ElementSpacing +

ADAR1000 element spacing

uri +

Hostname or IP address of remote libIIO deviceHelp for adi.Phaser/uri is inherited from superclass matlabshared.libiio.base

channelCount +

Number of enabled channelsHelp for adi.Phaser/channelCount is inherited from superclass matlabshared.libiio.base

DataTimeout +

Timeout for I/O operations (in seconds) 0 = non-blocking (or default context timeout) Inf = infiniteHelp for adi.Phaser/DataTimeout is inherited from superclass matlabshared.libiio.base

EnabledChannels +

Indexs of channels to be enabled. Input should be a [1xN] vector with the indexes of channels to be enabled. Order is irrelevant

Frequency +

Set output frequency of synthesizer in Hz. When the synthesizer is ramping this is the start frequencyHelp for adi.Phaser/Frequency is inherited from superclass adi.internal.ADF4159

FrequencyDeviationRange +

Set upper bound on frequency ramp from Frequency property in Hz. This is only applicable when RampMode is not set to "disabled"Help for adi.Phaser/FrequencyDeviationRange is inherited from superclass adi.internal.ADF4159

FrequencyDeviationStep +

Set step size in Hz of synthesizer ramp. This is only applicable when RampMode is not set to "disabled".Help for adi.Phaser/FrequencyDeviationStep is inherited from superclass adi.internal.ADF4159

FrequencyDeviationTime +

Set time in uSeconds to reach ramp peak value. This is only applicable when RampMode is not set to "disabled"Help for adi.Phaser/FrequencyDeviationTime is inherited from superclass adi.internal.ADF4159

RampMode +

Set ramp waveform. Options are: - "disabled" - "continuous_sawtooth" - "continuous_triangular" - "single_sawtooth_burst" - "single_ramp_burst"Help for adi.Phaser/RampMode is inherited from superclass adi.internal.ADF4159

Powerdown +

When true output will be disabled. Writing to this value will also update all settings of deviceHelp for adi.Phaser/Powerdown is inherited from superclass adi.internal.ADF4159

DelayStartWord +

Set start delay of each ramp in PFD or PFD*CLK1 clock cycles. This is a 12-bit numberHelp for adi.Phaser/DelayStartWord is inherited from superclass adi.internal.ADF4159

DelayClockSource +

Set clock use to determine ramp delay. Options are: - "PFD" - "PFD*CLK1"Help for adi.Phaser/DelayClockSource is inherited from superclass adi.internal.ADF4159

DelayStartEnable +

Enable delaying of ramp signal at start of first ramp generationHelp for adi.Phaser/DelayStartEnable is inherited from superclass adi.internal.ADF4159

RampDelayEnable +

Enable delaying of ramp signal at start of each ramp generationHelp for adi.Phaser/RampDelayEnable is inherited from superclass adi.internal.ADF4159

TriggerDelayEnable +

Enable ramp start delay when controlled by external triggerHelp for adi.Phaser/TriggerDelayEnable is inherited from superclass adi.internal.ADF4159

TriggerEnable +

Allow for use of external trigger on TX Data pin to start rampHelp for adi.Phaser/TriggerEnable is inherited from superclass adi.internal.ADF4159

SingleFullTriangleEnable +

Enable sending of single full triangular wave. This is applicable when RampMode is in "single_ramp_burst"Help for adi.Phaser/SingleFullTriangleEnable is inherited from superclass adi.internal.ADF4159

BurstCount +

Configure number of bursts in TDD controllerHelp for adi.Phaser/BurstCount is inherited from superclass adi.internal.AXICoreTDD

CounterInt +

Configure TDD internal counter start valueHelp for adi.Phaser/CounterInt is inherited from superclass adi.internal.AXICoreTDD

DMAGateingMode +

Configure TDD DMA gate 0 - none, 1 - rx_only, 2 - tx_only, 3 - rx_txHelp for adi.Phaser/DMAGateingMode is inherited from superclass adi.internal.AXICoreTDD

Enable +

Enable or disable the TDD engineHelp for adi.Phaser/Enable is inherited from superclass adi.internal.AXICoreTDD

EnableMode +

Configure TDD controller RX/TX mode 1 - rx_only, 2 - tx_only, 3 - rx_txHelp for adi.Phaser/EnableMode is inherited from superclass adi.internal.AXICoreTDD

FrameLength +

TDD Frame LengthHelp for adi.Phaser/FrameLength is inherited from superclass adi.internal.AXICoreTDD

Secondary +

Enable secondary times. Allows one signal to go high twice at two times within a single frame.Help for adi.Phaser/Secondary is inherited from superclass adi.internal.AXICoreTDD

SyncTerminalType +

Sync Terminal TypeHelp for adi.Phaser/SyncTerminalType is inherited from superclass adi.internal.AXICoreTDD

TxDPoff +

TDD: TX DMA port timing parameters in ms. Format [primary_off secondary_off]Help for adi.Phaser/TxDPoff is inherited from superclass adi.internal.AXICoreTDD

TxDPon +

TDD: TX DMA port timing parameters in ms. Format [primary_on secondary_on]Help for adi.Phaser/TxDPon is inherited from superclass adi.internal.AXICoreTDD

TxOff +

TDD: TX RF port timing parameters in ms. Format [primary_off secondary_off]Help for adi.Phaser/TxOff is inherited from superclass adi.internal.AXICoreTDD

TxOn +

TDD: TX RF port timing parameters in ms. Format [primary_on secondary_on]Help for adi.Phaser/TxOn is inherited from superclass adi.internal.AXICoreTDD

TxVCOoff +

TDD: TX VCO port timing parameters in ms. Format [primary_off secondary_off]Help for adi.Phaser/TxVCOoff is inherited from superclass adi.internal.AXICoreTDD

TxVCOon +

TDD: TX VCO port timing parameters in ms. Format [primary_on secondary_on]Help for adi.Phaser/TxVCOon is inherited from superclass adi.internal.AXICoreTDD

RxDPoff +

TDD: RX DMA port timing parameters in ms. Format [primary_off secondary_off]Help for adi.Phaser/RxDPoff is inherited from superclass adi.internal.AXICoreTDD

RxDPon +

TDD: RX DMA port timing parameters in ms. Format [primary_on secondary_on]Help for adi.Phaser/RxDPon is inherited from superclass adi.internal.AXICoreTDD

RxOff +

TDD: RX RF port timing parameters in ms. Format [primary_off secondary_off]Help for adi.Phaser/RxOff is inherited from superclass adi.internal.AXICoreTDD

RxOn +

TDD: RX RF port timing parameters in ms. Format [primary_on secondary_on]Help for adi.Phaser/RxOn is inherited from superclass adi.internal.AXICoreTDD

RxVCOoff +

TDD: RX VCO port timing parameters in ms. Format [primary_off secondary_off]Help for adi.Phaser/RxVCOoff is inherited from superclass adi.internal.AXICoreTDD

RxVCOon +

TDD: RX VCO port timing parameters in ms. Format [primary_on secondary_on]Help for adi.Phaser/RxVCOon is inherited from superclass adi.internal.AXICoreTDD