adrv9371 Reference Design Integration#

This page outlines the HDL reference design integration for the adrv9371 reference design for the Analog Devices AD9371 component. The IP-Core Generation follow is available on the based on the following base HDL reference design for the following board and design variants:

Reference Design#

../../_images/rd_jesd_custom.svg

HDL Reference Design with Custom IP from HDL-Coder. Click on sub-blocks for more documentation.#

The IP-Core generation flow will integrate IP generated from Simulink subsystem into an ADI authored reference design. Depending on the FPGA carrier and FMC card or SoM, this will support different IP locations based on the diagram above.

HDL Worflow Advisor Port Mappings#

When using the HDL Worflow Advisor, the following port mappings are used to connect the reference design to the HDL-Coder generated IP-Core:

Type

Target Platform Interface (MATLAB)

Reference Design Connection (Vivado)

Width

Reference Design Variant

VALID-OUT

util_ad9371_rx_cpack/fifo_wr_en

1

RX

VALID-OUT

rx_ad9371_tpl_core/adc_valid_0

1

RX

DATA-OUT

util_ad9371_rx_cpack/fifo_wr_data_0

16

RX

DATA-OUT

util_ad9371_rx_cpack/fifo_wr_data_1

16

RX

DATA-OUT

util_ad9371_rx_cpack/fifo_wr_data_2

16

RX

DATA-OUT

util_ad9371_rx_cpack/fifo_wr_data_3

16

RX

DATA-OUT

rx_ad9371_tpl_core/adc_data_0

16

RX

DATA-OUT

rx_ad9371_tpl_core/adc_data_1

16

RX

DATA-OUT

rx_ad9371_tpl_core/adc_data_2

16

RX

DATA-OUT

rx_ad9371_tpl_core/adc_data_3

16

RX

VALID-OUT

util_ad9371_tx_upack/fifo_rd_valid

1

TX

VALID-OUT

util_ad9371_tx_upack/fifo_rd_en

1

TX

DATA-OUT

tx_ad9371_tpl_core/dac_data_0

32

TX

DATA-OUT

tx_ad9371_tpl_core/dac_data_1

32

TX

DATA-OUT

tx_ad9371_tpl_core/dac_data_2

32

TX

DATA-OUT

tx_ad9371_tpl_core/dac_data_3

32

TX

DATA-OUT

util_ad9371_tx_upack/fifo_rd_data_0

32

TX

DATA-OUT

util_ad9371_tx_upack/fifo_rd_data_1

32

TX

DATA-OUT

util_ad9371_tx_upack/fifo_rd_data_2

32

TX

DATA-OUT

util_ad9371_tx_upack/fifo_rd_data_3

32

TX