BitBangSpiConfig Fields

Bit bang SPI clock phase. If set to false (0) data is sampled on the clock active to inactive edge, and updated on the inactive to active edge. If set to true (1), data is updated on the clock active to inactive transition, and data is sampled on the inactive to active edge. The CPHA/CPOL settings used are based on this diagram: https://en.wikipedia.org/wiki/Serial_Peripheral_Interface#/media/File:SPI_timing_diagram2.svg

Bit bang SPI clock polarity. True (1) is idle high, False (0) is idle low.

Chip select pin for bit bang SPI

Number of timer ticks from last sclk edge to CS rising edge

Number of timer ticks from CS falling edge to first sclk edge

MISO (master is, slave out) pin for bit bang SPI

MOSI (master out, slave in) pin for bit bang SPI

SCLK pin for bit bang SPI

Half SCLK period timer ticks

Stall time timer ticks