ADI iSensor FX3 Firmware  v2.9.4-pub
Firmware for the Analog Devices EVAL-ADIS-FX3 IMU Evaluation Platform. This firmware can be compiled using the Cypress EZ USB Suite IDE
gctlaon_regs.h
Go to the documentation of this file.
1 
7 /*
8  *
9  * File: gctlaon_regs.h
10  *
11  * Copyright (c) 2010-13 Cypress Semiconductor. All Rights Reserved
12  * UNPUBLISHED, LICENSED SOFTWARE.
13  *
14  * CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF CYPRESS.
15  *
16  * Description:
17  * Global Control Always-On registers for the EZ-USB FX3 Device.
18  *
19  * This file is auto generated from register spreadsheet.
20  * DO NOT MODIFY THIS FILE
21  *
22  * Use of this file is governed by the license agreement included in the file
23  *
24  * <install>/license/license.txt
25  *
26  * where <install> is the Cypress software installation root directory path.
27  */
28 
29 
30 #ifndef _INCLUDED_GCTLAON_REGS_H_
31 #define _INCLUDED_GCTLAON_REGS_H_
32 
33 #include <cyu3types.h>
34 
35 #define GCTLAON_BASE_ADDR (0xe0050000)
36 
37 typedef struct
38 {
39  uvint32_t control; /* 0xe0050000 */
40  uvint32_t wakeup_en; /* 0xe0050004 */
41  uvint32_t wakeup_polarity; /* 0xe0050008 */
42  uvint32_t wakeup_event; /* 0xe005000c */
43  uvint32_t freeze; /* 0xe0050010 */
44  uvint32_t watchdog_cs; /* 0xe0050014 */
45  uvint32_t watchdog_timer0; /* 0xe0050018 */
46  uvint32_t watchdog_timer1; /* 0xe005001c */
47 } GCTLAON_REGS_T, *PGCTLAON_REGS_T;
48 
49 #define GCTLAON ((PGCTLAON_REGS_T) GCTLAON_BASE_ADDR)
50 
51 
52 /*
53  Main GCTL control register for power, reset, boot
54  */
55 #define CY_U3P_GCTL_CONTROL_ADDRESS (0xe0050000)
56 #define CY_U3P_GCTL_CONTROL (*(uvint32_t *)(0xe0050000))
57 #define CY_U3P_GCTL_CONTROL_DEFAULT (0xde040001)
58 
59 /*
60  Indicates system woke up through a power-on-reset or RESET# pin reset
61  sequence. If firmware does not clear this bit it will stay 1 even through
62  software reset, standby and suspend sequences. This bit is visible in
63  PP_INIT. (connected to HardHard Reset)
64  */
65 #define CY_U3P_GCTL_POR (1u << 0) /* <0:0> RW1S:RW0C:1:No */
66 
67 
68 /*
69  Indicates system woke up from a s/w induced hard reset sequence (from
70  HARD_RESET_N below or PP_INIT.HARD_RESET_N). If firmware does not clear
71  this bit it will stay 1 even through standby and suspend sequences. This
72  bit is visible in PP_INIT. (connected to HardHard Reset)
73  */
74 #define CY_U3P_GCTL_SW_RESET (1u << 1) /* <1:1> RW1S:RW0C:0:No */
75 
76 
77 /*
78  Indicates system woke up from a watchdog timer induced hard reset (see
79  GCTL_WATCHDOG_CS). If firmware does not clear this bit it will stay 1
80  even through standby and suspend sequences. This bit is visible in PP_INIT.
81  (connected to HardHard Reset)
82  */
83 #define CY_U3P_GCTL_WDT_RESET (1u << 2) /* <2:2> RW1S:RW0C:0:No */
84 
85 
86 /*
87  Indicates system woke up from standby mode (see architecture spec for
88  details). If firmware does not clear this bit it will stay 1 even through
89  suspend sequences. This bit is visible in PP_INIT. (connected to HardHard
90  Reset)
91  */
92 #define CY_U3P_GCTL_WAKEUP_PWR (1u << 3) /* <3:3> RW1S:RW0C:0:No */
93 
94 
95 /*
96  Indicates system woke up from suspend state (see architecture spec for
97  details). If firmware does not clear this bit it will stay 1 even through
98  standby sequences. This bit is visible in PP_INIT. (connected to HardHard
99  Reset)
100  */
101 #define CY_U3P_GCTL_WAKEUP_CLK (1u << 4) /* <4:4> RW1S:RW0C:0:No */
102 
103 
104 /*
105  This bit is used by the BootROM code to indicate that it has completed.
106  BootROM sets this bit just before it jumps into the firmware start address.
107  This bit can be used by a host processor to observe a completed boot
108  process of a corrupt firmware image. (Connected to Partial Reset)
109  */
110 #define CY_U3P_GCTL_BOOT_COMPLETE (1u << 8) /* <8:8> R:RW:0:N/A */
111 
112 
113 /*
114  Indicates that the CPU is in debug mode. This bit is tied to a ARM926
115  CPU output signal and is read-only for software. (Connected to CPU Reset)
116  */
117 #define CY_U3P_GCTL_DEBUG_MODE (1u << 9) /* <9:9> RW:R:0:N/A */
118 
119 
120 /*
121  Indicates that system RAM arrays are powered off when main power gate
122  is switched off (standby mode) through MAIN_POWER_EN. Default is that
123  arrays remain powered up and retain information. This bit is reset on
124  pin, POR, or watchdog reset only. (Connected to HardHard Reset)
125  */
126 #define CY_U3P_GCTL_RAM_SLEEP (1u << 10) /* <10:10> R:RW:0:N/A */
127 
128 
129 /*
130  When 1 any interrupt cause bit set in GCTL_WAKEUP_EV will force INT# pin
131  to low. This is intended to enable forwarding of wakeup events to the
132  application processor when reference clock is disabled (so AP can wakeup
133  and turn it on). When using this option, it is important to clear the
134  wakeup events in order to prevent INT# to remain asserted. This bit is
135  reset on pin, POR, or watchdog reset only. (Connected to HardHard Reset)
136  */
137 #define CY_U3P_GCTL_WAKEUP_AP_INT (1u << 11) /* <11:11> R:RW:0:N/A */
138 
139 
140 /*
141  Enables the wakeup interrupt to the CPU. This bit is reset on pin, POR,
142  or watchdog reset only. (Connected to HardHard Reset)
143  */
144 #define CY_U3P_GCTL_WAKEUP_CPU_INT (1u << 12) /* <12:12> R:RW:0:No */
145 
146 
147 /*
148  Enables BIST controller for SysMem. This removes SysMem from system bus;
149  CPU execution can only be fom ITCM/DTCM. (Connected to Partial Reset)
150  */
151 #define CY_U3P_GCTL_SYSMEM_BIST_EN (1u << 14) /* <14:14> R:RW:0:No */
152 
153 
154 /*
155  This bit is reset on pin, POR, or watchdog reset only.
156  0: Wait for CPU to go to SBYWFI state before executing MAIN_POWER_EN=0/MAIN_CLOCK_EN=0
157  1: Do not wait for CPU to go to SBYWFI state, execute immediately.
158  (Connected to HardHard Reset)
159  */
160 #define CY_U3P_GCTL_NO_SBYWFI (1u << 15) /* <15:15> R:RW:0:No */
161 
162 
163 /*
164  Prohibits writing to GCTL_WATCHDOG registers when not equal 0.
165  Requires at least two different writes to unlock.
166  Writing to this field has the following effect:
167  0: No effect
168  1: Clears bit 0
169  2: Clears bit 1
170  3: Sets both bits 0 and 1
171  Note that this field is 2 bits to force multiple writes only. It represents
172  only a single write protect signal protecting all WATCHDOG registers at
173  the same time. (Connected to HardHard Reset)
174  */
175 #define CY_U3P_GCTL_WDT_PROTECT_MASK (0x00030000) /* <16:17> R:RW:0:Yes */
176 #define CY_U3P_GCTL_WDT_PROTECT_POS (16)
177 
178 
179 /*
180  USB D+/D- analog switch
181  0: USB Mode. Connects D+/D- to USB PHY
182  1: Bypass mode. Connects D+/D- to SWD+/SWD- pads (analog)
183  This switch takes precedence over CARKIT switch. (Connected to HardHard
184  Reset).
185  */
186 #define CY_U3P_GCTL_ANALOG_SWITCH (1u << 18) /* <18:18> R:RW:1:Yes */
187 
188 
189 /*
190  Enables the main regulators in USB IO Subsystem. These regulators supply
191  the 2.5/3.3V to the USB2 and USB3 PHY's. Power to the USB HS Switch is
192  separate and is always supplied when VBUS/VBAT is present. (Connected
193  to Partial Reset).
194  */
195 #define CY_U3P_GCTL_USB_POWER_EN (1u << 21) /* <21:21> R:RW:0:Yes */
196 
197 
198 /*
199  Enables the use of VBAT in the USB IO Subsystem when both VBUS and VBAT
200  supplies are present. Once set, this bit should not be cleared without
201  taking
202  special precautions. See the PAS for details.
203  0: Use only VBUS input voltage for USB PHY/Switch regulators when both
204  VBUS and VBAT supplies are present
205  1: Use VBAT input voltage when present VBUS and VBAT supplies are present.
206  (Connected to Partial Reset).
207  */
208 #define CY_U3P_GCTL_USB_VBAT_EN (1u << 22) /* <22:22> R:RW:0:No */
209 
210 
211 /*
212  Forces all IOs with hold capability (as specified in Architecture Spec)
213  to sample and hold their current state (drive strength, pull up/downs,
214  in/out state, drive high/low) or be forced to a given state as specified
215  in GCTL_FREEZE. This bit must be set together with MAIN_POWER_EN and
216  may be set together with MAIN_CLOCK_EN). It must be cleared after wakeup
217  after IO configuration registers and port functions have been properly
218  re-initialized. This bit is reset on pin, POR, or watchdog reset only.
219  (Connected to Hard Reset).
220  */
221 #define CY_U3P_GCTL_FREEZE_IO (1u << 24) /* <24:24> R:RW:0:No */
222 
223 
224 /*
225  Software clears this bit to turn off all clock PLLs. Only the external
226  32kHz wakeup clock is still available. All domains remain powered and
227  retain state. System will wakeup from any enabled wakeup source (enabled
228  in GCTL_WAKEUP_EN) and set WAKEUP_CLK bit. If a write to 0 persists at
229  1, then there are wakeup events that first need to be handled and cleared
230  in the WAKEUP_EVENT register. (Connected to HardHard Reset).
231  */
232 #define CY_U3P_GCTL_MAIN_CLOCK_EN (1u << 25) /* <25:25> RW1S:RW0C:1:Yes */
233 
234 
235 /*
236  Software clears this bit to turn off main power gates. Only wakup and
237  system memory domains (see RAM_SLEEP) will remain powered. System will
238  wakeup from any enabled wakeup source (enabled in GCTL_WAKEUP_EN) and
239  set WAKEUP_PWR bit. If a write to 0 persists at '1', then there are wakeup
240  events that first need to be handled and cleared in the WAKEUP_EVENT register.
241  (Connected to HardHard Reset).
242  */
243 #define CY_U3P_GCTL_MAIN_POWER_EN (1u << 26) /* <26:26> RW1S:RW0C:1:Yes */
244 
245 
246 /*
247  Software may clear this bit to disable boot ROM access by the CPU (or
248  any other peripheral). Once cleared this bit can not be set back to 1.
249  This bit is set by hardware after a CPU or a chip reset; it is not set
250  after a wakeup from suspend. (Connected to CPU Reset).
251  */
252 #define CY_U3P_GCTL_BOOTROM_EN (1u << 28) /* <28:28> R:RW0C:1:Yes */
253 
254 
255 /*
256  Software sets this bit to indicate to boot ROM that no new firmware shall
257  be loaded. Exact warm boot process is detailed in the boot ROM specification.
258  This bit is not reset when going through a CPU_RESET or HARD_RESET.
259  It is reset only when going through a pin, POR or WATCHDOG reset. (Connected
260  to Hard Reset)
261  */
262 #define CY_U3P_GCTL_WARM_BOOT (1u << 29) /* <29:29> -:RW:0:N/A */
263 
264 
265 /*
266  Firmware clears this bit to effect a CPU reset (aka reboot). This bit
267  will automatically re-assert as part of the reset sequence. No other blocks
268  or registers expect cpu_top are affected. The CPU will enter the boot
269  ROM, that will use the WARM_BOOT flag to determine whether to reload firmware.
270  This function is also available in PP_INIT. (Connected to Partial Reset).
271  */
272 #define CY_U3P_GCTL_CPU_RESET_N (1u << 30) /* <30:30> RW1S:RW0C:1:No */
273 
274 
275 /*
276  Firmware clears this bit to effect a global hard reset (all blocks, all
277  flops). This is equivalent to toggling the RESET pin on the device, except
278  that WARM_BOOT (above) will not be cleared). This function is also available
279  in PP_INIT. (Connected to Partial Reset).
280  */
281 #define CY_U3P_GCTL_HARD_RESET_N (1u << 31) /* <31:31> R:RW0C:1:No */
282 
283 
284 
285 /*
286  Wakeup enable register
287  */
288 #define CY_U3P_GCTL_WAKEUP_EN_ADDRESS (0xe0050004)
289 #define CY_U3P_GCTL_WAKEUP_EN (*(uvint32_t *)(0xe0050004))
290 #define CY_U3P_GCTL_WAKEUP_EN_DEFAULT (0x00000000)
291 
292 /*
293  Enables wakeup from the PIB CTL0 pin (CE# typically). Wakeup occurs on
294  any change on this pin after wakeup.
295  */
296 #define CY_U3P_GCTL_EN_PIB_CTRL0 (1u << 0) /* <0:0> R:RW:0:Yes */
297 
298 
299 /*
300  Enable wakeup from a CMD5 on the PIB_CMD pin. This wakeup source does
301  not work from standby mode.
302  */
303 #define CY_U3P_GCTL_EN_PIB_CMD (1u << 1) /* <1:1> R:RW:0:Yes */
304 
305 
306 /*
307  Enables wakeup from the PIB_CLK pin. Wakeup occurs on any change on this
308  pin after wakeup.
309  */
310 #define CY_U3P_GCTL_EN_PIB_CLK (1u << 2) /* <2:2> R:RW:0:Yes */
311 
312 
313 /*
314  Enables wakeup from the S0 SDIO_INT pin (SD0). Wakeup occurs when the
315  level set in POL_S0_SDIO_INT is detected.
316  */
317 #define CY_U3P_GCTL_EN_S0_SDIO_INT (1u << 3) /* <3:3> R:RW:0:Yes */
318 
319 
320 /*
321  Enables wakeup from the S1 SDIO_INT pin (SD1). Wakeup occurs when the
322  level set in POL_S1_SDIO_INT is detected.
323  */
324 #define CY_U3P_GCTL_EN_S1_SDIO_INT (1u << 4) /* <4:4> R:RW:0:Yes */
325 
326 
327 /*
328  Enables wakeup from the S0S1_INS pin (card insertion). Wakeup occurs
329  when the level set in POL_S0S1_INS_INT is detected.
330  */
331 #define CY_U3P_GCTL_EN_S0S1_INS (1u << 5) /* <5:5> R:RW:0:Yes */
332 
333 
334 /*
335  Enables wakeup from the UART_CTS pin. Wakeup occurs when the level set
336  in POL_UART_CTS is detected.
337  */
338 #define CY_U3P_GCTL_EN_UART_CTS (1u << 6) /* <6:6> R:RW:0:Yes */
339 
340 
341 /*
342  Enables wakeup when USB2 D+ line transitions to from 1 to 0 (USB RESUME)
343  or from 0 to 1 (CONNECT in host mode).
344  This wakeup source does not work from standby mode.
345  */
346 #define CY_U3P_GCTL_EN_UIB_DP (1u << 7) /* <7:7> R:RW:0:Yes */
347 
348 
349 /*
350  Enables wakeup when USB2 D+ line transitions to from 0 to 1 or from 1
351  to 0 (CONNECT in host mode).
352  This wakeup source does not work from standby mode.
353  */
354 #define CY_U3P_GCTL_EN_UIB_DM (1u << 8) /* <8:8> R:RW:0:Yes */
355 
356 
357 /*
358  Enables wakeup when an impedance change is detected on the USB2 OTGID
359  pin (USB ATTACH event).
360  This wakeup source does not work from standby mode.
361  */
362 #define CY_U3P_GCTL_EN_UIB_OTGID (1u << 9) /* <9:9> R:RW:0:Yes */
363 
364 
365 /*
366  Enables wakeup when an LFPS signal appears on the USB3 SSRX pins.
367  This wakeup source does not work from standby mode.
368  */
369 #define CY_U3P_GCTL_EN_UIB_SSRX (1u << 10) /* <10:10> R:RW:0:Yes */
370 
371 
372 /*
373  Enables wakeup when VBUS is asserted. Works in either standby or suspend
374  modes.
375  */
376 #define CY_U3P_GCTL_EN_UIB_VBUS (1u << 11) /* <11:11> R:RW:0:Yes */
377 
378 
379 /*
380  Enables wakeup when WatchDog #1 generates an interrupt.
381  */
382 #define CY_U3P_GCTL_EN_WATCHDOG1 (1u << 12) /* <12:12> R:RW:0:Yes */
383 
384 
385 /*
386  Enables wakeup when WatchDog #2 generates an interrupt.
387  */
388 #define CY_U3P_GCTL_EN_WATCHDOG2 (1u << 13) /* <13:13> R:RW:0:Yes */
389 
390 
391 
392 /*
393  Wakeup signal polarity register
394  */
395 #define CY_U3P_GCTL_WAKEUP_POLARITY_ADDRESS (0xe0050008)
396 #define CY_U3P_GCTL_WAKEUP_POLARITY (*(uvint32_t *)(0xe0050008))
397 #define CY_U3P_GCTL_WAKEUP_POLARITY_DEFAULT (0x00000800)
398 
399 /*
400  Polarity of the SDIO_INT signal:
401  0: Wakeup when low (Applicable for SDIO interrupt wake up)
402  1: Wakeup when high (Not required for SDIO interrupt wake up)
403  */
404 #define CY_U3P_GCTL_POL_S0_SDIO_INT (1u << 3) /* <3:3> R:RW:0:Yes */
405 
406 
407 /*
408  Polarity of the SDIO_INT signal:
409  0: Wakeup when low (Applicable for SDIO interrupt wake up)
410  1: Wakeup when high (Not required for SDIO interrupt wake up)
411  */
412 #define CY_U3P_GCTL_POL_S1_SDIO_INT (1u << 4) /* <4:4> R:RW:0:Yes */
413 
414 
415 /*
416  Polarity of the S0S1_INS signal:
417  0: Wakeup when low
418  1: Wakeup when high
419  */
420 #define CY_U3P_GCTL_POL_S0S1_INS (1u << 5) /* <5:5> R:RW:0:Yes */
421 
422 
423 /*
424  Polarity of the UART_CTS signal:
425  0: Wakeup when low
426  1: Wakeup when high
427  */
428 #define CY_U3P_GCTL_POL_UART_CTS (1u << 6) /* <6:6> R:RW:0:Yes */
429 
430 
431 /*
432  Polarity of the USB D+ signal:
433  0: Wakeup when low
434  1: Wakeup when high
435  */
436 #define CY_U3P_GCTL_POL_UIB_DP (1u << 7) /* <7:7> R:RW:0:Yes */
437 
438 
439 /*
440  Polarity of the USB D- signal:
441  0: Wakeup when low
442  1: Wakeup when high
443  */
444 #define CY_U3P_GCTL_POL_UIB_DM (1u << 8) /* <8:8> R:RW:0:Yes */
445 
446 
447 /*
448  Polarity of the VBUS signal:
449  0: Wakeup when low
450  1: Wakeup when high
451  */
452 #define CY_U3P_GCTL_POL_UIB_VBUS (1u << 11) /* <11:11> R:RW:1:Yes */
453 
454 
455 
456 /*
457  Wakeup event register
458  */
459 #define CY_U3P_GCTL_WAKEUP_EVENT_ADDRESS (0xe005000c)
460 #define CY_U3P_GCTL_WAKEUP_EVENT (*(uvint32_t *)(0xe005000c))
461 #define CY_U3P_GCTL_WAKEUP_EVENT_DEFAULT (0x00000000)
462 
463 /*
464  Indicates this wakeup source was the reason for system wakeup from standby/suspend
465  mode. See GCTL_WAKEUP_EN for more info.
466  */
467 #define CY_U3P_GCTL_EV_PIB_CTRL0 (1u << 0) /* <0:0> RW1S:RW1C:0:Yes */
468 
469 
470 /*
471  Indicates this wakeup source was the reason for system wakeup from standby/suspend
472  mode. See GCTL_WAKEUP_EN for more info.
473  */
474 #define CY_U3P_GCTL_EV_PIB_CMD (1u << 1) /* <1:1> RW1S:RW1C:0:Yes */
475 
476 
477 /*
478  Indicates this wakeup source was the reason for system wakeup from standby/suspend
479  mode. See GCTL_WAKEUP_EN for more info.
480  */
481 #define CY_U3P_GCTL_EV_PIB_CLK (1u << 2) /* <2:2> RW1S:RW1C:0:Yes */
482 
483 
484 /*
485  Indicates this wakeup source was the reason for system wakeup from standby/suspend
486  mode. See GCTL_WAKEUP_EN for more info.
487  */
488 #define CY_U3P_GCTL_EV_S0_SDIO_INT (1u << 3) /* <3:3> RW1S:RW1C:0:Yes */
489 
490 
491 /*
492  Indicates this wakeup source was the reason for system wakeup from standby/suspend
493  mode. See GCTL_WAKEUP_EN for more info.
494  */
495 #define CY_U3P_GCTL_EV_S1_SDIO_INT (1u << 4) /* <4:4> RW1S:RW1C:0:Yes */
496 
497 
498 /*
499  Indicates this wakeup source was the reason for system wakeup from standby/suspend
500  mode. See GCTL_WAKEUP_EN for more info.
501  */
502 #define CY_U3P_GCTL_EV_S0S1_INS (1u << 5) /* <5:5> RW1S:RW1C:0:Yes */
503 
504 
505 /*
506  Indicates this wakeup source was the reason for system wakeup from standby/suspend
507  mode. See GCTL_WAKEUP_EN for more info.
508  */
509 #define CY_U3P_GCTL_EV_UART_CTS (1u << 6) /* <6:6> RW1S:RW1C:0:Yes */
510 
511 
512 /*
513  Indicates this wakeup source was the reason for system wakeup from standby/suspend
514  mode. See GCTL_WAKEUP_EN for more info.
515  */
516 #define CY_U3P_GCTL_EV_UIB_DP (1u << 7) /* <7:7> RW1S:RW1C:0:Yes */
517 
518 
519 /*
520  Indicates this wakeup source was the reason for system wakeup from standby/suspend
521  mode. See GCTL_WAKEUP_EN for more info.
522  */
523 #define CY_U3P_GCTL_EV_UIB_DM (1u << 8) /* <8:8> RW1S:RW1C:0:Yes */
524 
525 
526 /*
527  Indicates this wakeup source was the reason for system wakeup from standby/suspend
528  mode. See GCTL_WAKEUP_EN for more info.
529  */
530 #define CY_U3P_GCTL_EV_UIB_OTGID (1u << 9) /* <9:9> RW1S:RW1C:0:Yes */
531 
532 
533 /*
534  Indicates this wakeup source was the reason for system wakeup from standby/suspend
535  mode. See GCTL_WAKEUP_EN for more info.
536  */
537 #define CY_U3P_GCTL_EV_UIB_SSRX (1u << 10) /* <10:10> RW1S:RW1C:0:Yes */
538 
539 
540 /*
541  Indicates this wakeup source was the reason for system wakeup from standby/suspend
542  mode. See GCTL_WAKEUP_EN for more info.
543  */
544 #define CY_U3P_GCTL_EV_UIB_VBUS (1u << 11) /* <11:11> RW1S:RW1C:0:Yes */
545 
546 
547 /*
548  Indicates this wakeup source was the reason for system wakeup from standby/suspend
549  mode. See GCTL_WAKEUP_EN for more info.
550  */
551 #define CY_U3P_GCTL_EV_WATCHDOG1 (1u << 12) /* <12:12> RW1S:RW1C:0:Yes */
552 
553 
554 /*
555  Indicates this wakeup source was the reason for system wakeup from standby/suspend
556  mode. See GCTL_WAKEUP_EN for more info.
557  */
558 #define CY_U3P_GCTL_EV_WATCHDOG2 (1u << 13) /* <13:13> RW1S:RW1C:0:Yes */
559 
560 
561 
562 /*
563  IO Freeze control register
564  */
565 #define CY_U3P_GCTL_FREEZE_ADDRESS (0xe0050010)
566 #define CY_U3P_GCTL_FREEZE (*(uvint32_t *)(0xe0050010))
567 #define CY_U3P_GCTL_FREEZE_DEFAULT (0x00000000)
568 
569 /*
570  Frozen state of IOs in the P domain
571  0: Sample and hold state
572  1: High impedance
573  2: Drive 0 at full strength (outputs only)
574  3: Drive 1 at full strength (outputs only)
575  Note that states 2,3 will only override the output value driven to a fixed
576  value, but will not change the drive mode of a pin from off to on. In
577  other words, pins that are currently inputs will remain inputs and not
578  be forced to drive.
579  */
580 #define CY_U3P_GCTL_PFRZ_MASK (0x00000003) /* <0:1> R:RW:0:No */
581 #define CY_U3P_GCTL_PFRZ_POS (0)
582 
583 
584 /*
585  Frozen state of IOs in the S0 domain.
586  */
587 #define CY_U3P_GCTL_S0FRZ_MASK (0x0000000c) /* <2:3> R:RW:0:No */
588 #define CY_U3P_GCTL_S0FRZ_POS (2)
589 
590 
591 /*
592  Frozen state of IOs in the S1 domain.
593  */
594 #define CY_U3P_GCTL_S1FRZ_MASK (0x00000030) /* <4:5> R:RW:0:No */
595 #define CY_U3P_GCTL_S1FRZ_POS (4)
596 
597 
598 /*
599  Frozen state of IOs in the L domain.
600  */
601 #define CY_U3P_GCTL_LFRZ_MASK (0x000000c0) /* <6:7> R:RW:0:No */
602 #define CY_U3P_GCTL_LFRZ_POS (6)
603 
604 
605 /*
606  Controls two watchdog timers. Each timer can be used in free-running,
607  interrupt or reset mode and has a selectable number of significant bits.
608  Frequency is fixed at 32768Hz, and counters count down only. This register
609  can be protected against unwanted writes by firmware (see GCTL_CONTROL).
610  */
611 /*
612  Once the backup clock divider was activated (BACKUP_CLK=1), special care
613  must be taken to change the divider value. The procedure is as follows:
614  */
615 /*
616  1) Set GCTL_WATCHDOG_CS.BACKUP_CLK = 0
617  */
618 /*
619  2) Wait a sufficiently long amount of time to allow clock to shut off
620  */
621 /*
622  3) Change GCTL_WATCHDOG_CS.BACKUP_DIVIDER as desired and set GCTL_WATCHDOG_CS.BACKUP_CLK
623  = 1
624  */
625 /*
626  The "sufficiently long amount of time" can be calculated as follows:
627  */
628 /*
629  Number of mmio clocks to wait = (backup clock period / mmio clock period)
630  + 5
631  */
632 
633 /*
634  Watchdog timers command and control
635  */
636 /*
637 
638  */
639 #define CY_U3P_GCTL_WATCHDOG_CS_ADDRESS (0xe0050014)
640 #define CY_U3P_GCTL_WATCHDOG_CS (*(uvint32_t *)(0xe0050014))
641 #define CY_U3P_GCTL_WATCHDOG_CS_DEFAULT (0x00010303)
642 
643 /*
644  Counter mode:
645  0: Free running mode, counter wraps around after 32 bits.
646  1: Interrupt mode, interrupt when COUNTER & ~((~0)<<BITS) = 0.
647  2: Reset mode, full chip RESET when COUNTER & ~((~0)<<BITS) = 0.
648  3: Disable - counter does not run
649  */
650 #define CY_U3P_GCTL_MODE0_MASK (0x00000003) /* <0:1> R:RW:3:Yes */
651 #define CY_U3P_GCTL_MODE0_POS (0)
652 
653 
654 /*
655  Interrupt signal (Mode 1 only).
656  */
657 #define CY_U3P_GCTL_INTR0 (1u << 2) /* <2:2> RW1S:RW1C:0:Yes */
658 
659 
660 /*
661  Number of least significant bits to be used when checking for counter
662  limit (only useful for MODE=1,2)
663  */
664 #define CY_U3P_GCTL_BITS0_MASK (0x000000f8) /* <3:7> R:RW:0:Yes */
665 #define CY_U3P_GCTL_BITS0_POS (3)
666 
667 
668 /*
669  Counter mode:
670  0: Free running mode, counter wraps around after 32 bits.
671  1: Interrupt mode, interrupt when COUNTER & ~((~0)<<BITS) = 0.
672  2: Reset mode, full chip RESET when COUNTER & ~((~0)<<BITS) = 0.
673  3: Disable - counter does not run
674  */
675 #define CY_U3P_GCTL_MODE1_MASK (0x00000300) /* <8:9> R:RW:3:Yes */
676 #define CY_U3P_GCTL_MODE1_POS (8)
677 
678 
679 /*
680  Interrupt signal (Mode 1 only).
681  */
682 #define CY_U3P_GCTL_INTR1 (1u << 10) /* <10:10> RW1S:RW1C:0:Yes */
683 
684 
685 /*
686  Number of least significant bits to be used when checking for counter
687  limit (only useful for MODE=1,2)
688  */
689 #define CY_U3P_GCTL_BITS1_MASK (0x0000f800) /* <11:15> R:RW:0:Yes */
690 #define CY_U3P_GCTL_BITS1_POS (11)
691 
692 
693 /*
694  Divider used to generate a 'backup' 32kHz clock. This is relevant for
695  systems where no 32kHz is present as an input signal. The external reference
696  clock (OSCCLK) is divided by (BACKUP_DIVIDER+1) - in other words a value
697  of 1 means divider by 2. The behavior of the dividier is underfined when
698  this value is 0.
699  */
700 #define CY_U3P_GCTL_BACKUP_DIVIDER_MASK (0x7fff0000) /* <16:30> R:RW:1:No */
701 #define CY_U3P_GCTL_BACKUP_DIVIDER_POS (16)
702 
703 
704 /*
705  Switches the watchdog clocks from the 32kHz clock input to a 'backup'
706  32kHz clock derived from the main reference clock using BACKUP_DIVIDER.
707  */
708 #define CY_U3P_GCTL_BACKUP_CLK (1u << 31) /* <31:31> R:RW:0:Yes */
709 
710 
711 
712 /*
713  Watchdog timer value 0
714  */
715 /*
716  Watchdog timer/counter. Counts down and generates interrupt/reset when
717  reaching low-limit (see GCTL_WATCHDOG_CS). Counter is free running and
718  wraps around after 32 bits. In watchdog mode this value must be reloaded
719  periodically to avoid full chip reset. This register can be protected
720  against unwanted writes by firmware (see GCTL_CONTROL).
721  */
722 #define CY_U3P_GCTL_WATCHDOG_TIMER0_ADDRESS (0xe0050018)
723 #define CY_U3P_GCTL_WATCHDOG_TIMER0 (*(uvint32_t *)(0xe0050018))
724 #define CY_U3P_GCTL_WATCHDOG_TIMER0_DEFAULT (0xffffffff)
725 
726 /*
727  Current counter value. Please note that due to synchronization it may
728  take up to 100us before a value written to this register can be read back.
729  Earlier reads will return the previous value.
730  */
731 #define CY_U3P_GCTL_COUNTER_MASK (0xffffffff) /* <0:31> R:RW:0xFFFFFFFF:Yes */
732 #define CY_U3P_GCTL_COUNTER_POS (0)
733 
734 
735 
736 /*
737  Watchdog timer value 0
738  */
739 /*
740  Watchdog timer/counter. Counts down and generates interrupt/reset when
741  reaching low-limit (see GCTL_WATCHDOG_CS). Counter is free running and
742  wraps around after 32 bits. In watchdog mode this value must be reloaded
743  periodically to avoid full chip reset. This register can be protected
744  against unwanted writes by firmware (see GCTL_CONTROL).
745  */
746 #define CY_U3P_GCTL_WATCHDOG_TIMER1_ADDRESS (0xe005001c)
747 #define CY_U3P_GCTL_WATCHDOG_TIMER1 (*(uvint32_t *)(0xe005001c))
748 #define CY_U3P_GCTL_WATCHDOG_TIMER1_DEFAULT (0xffffffff)
749 
750 /*
751  Current counter value. Please note that due to synchronization it may
752  take up to 100us before a value written to this register can be read back.
753  Earlier reads will return the previous value.
754  */
755 #define CY_U3P_GCTL_COUNTER_MASK (0xffffffff) /* <0:31> R:RW:0xFFFFFFFF:Yes */
756 #define CY_U3P_GCTL_COUNTER_POS (0)
757 
758 
759 
760 #endif /* _INCLUDED_GCTLAON_REGS_H_ */
761 
762 /*[]*/
GCTLAON_REGS_T
Definition: gctlaon_regs.h:38
Generated by doxygen 1.8.20