Macros
#define	MXC_F_DMA_CFG_CHIEN_POS 0

#define	MXC_F_DMA_CFG_CHIEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHIEN_POS))

#define	MXC_F_DMA_CFG_RLDEN_POS 1

#define	MXC_F_DMA_CFG_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_RLDEN_POS))

#define	MXC_F_DMA_CFG_PRI_POS 2

#define	MXC_F_DMA_CFG_PRI ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PRI_POS))

#define	MXC_V_DMA_CFG_PRI_HIGH ((uint32_t)0x0UL)

#define	MXC_S_DMA_CFG_PRI_HIGH (MXC_V_DMA_CFG_PRI_HIGH << MXC_F_DMA_CFG_PRI_POS)

#define	MXC_V_DMA_CFG_PRI_MEDHIGH ((uint32_t)0x1UL)

#define	MXC_S_DMA_CFG_PRI_MEDHIGH (MXC_V_DMA_CFG_PRI_MEDHIGH << MXC_F_DMA_CFG_PRI_POS)

#define	MXC_V_DMA_CFG_PRI_MEDLOW ((uint32_t)0x2UL)

#define	MXC_S_DMA_CFG_PRI_MEDLOW (MXC_V_DMA_CFG_PRI_MEDLOW << MXC_F_DMA_CFG_PRI_POS)

#define	MXC_V_DMA_CFG_PRI_LOW ((uint32_t)0x3UL)

#define	MXC_S_DMA_CFG_PRI_LOW (MXC_V_DMA_CFG_PRI_LOW << MXC_F_DMA_CFG_PRI_POS)

#define	MXC_F_DMA_CFG_REQSEL_POS 4

#define	MXC_F_DMA_CFG_REQSEL ((uint32_t)(0x3FUL << MXC_F_DMA_CFG_REQSEL_POS))

#define	MXC_V_DMA_CFG_REQSEL_MEMTOMEM ((uint32_t)0x0UL)

#define	MXC_S_DMA_CFG_REQSEL_MEMTOMEM (MXC_V_DMA_CFG_REQSEL_MEMTOMEM << MXC_F_DMA_CFG_REQSEL_POS)

#define	MXC_V_DMA_CFG_REQSEL_SPI0RX ((uint32_t)0x1UL)

#define	MXC_S_DMA_CFG_REQSEL_SPI0RX (MXC_V_DMA_CFG_REQSEL_SPI0RX << MXC_F_DMA_CFG_REQSEL_POS)

#define	MXC_V_DMA_CFG_REQSEL_SPI1RX ((uint32_t)0x2UL)

#define	MXC_S_DMA_CFG_REQSEL_SPI1RX (MXC_V_DMA_CFG_REQSEL_SPI1RX << MXC_F_DMA_CFG_REQSEL_POS)

#define	MXC_V_DMA_CFG_REQSEL_I2C0RX ((uint32_t)0x7UL)

#define	MXC_S_DMA_CFG_REQSEL_I2C0RX (MXC_V_DMA_CFG_REQSEL_I2C0RX << MXC_F_DMA_CFG_REQSEL_POS)

#define	MXC_V_DMA_CFG_REQSEL_UART0RX ((uint32_t)0x1CUL)

#define	MXC_S_DMA_CFG_REQSEL_UART0RX (MXC_V_DMA_CFG_REQSEL_UART0RX << MXC_F_DMA_CFG_REQSEL_POS)

#define	MXC_V_DMA_CFG_REQSEL_SPI0TX ((uint32_t)0x21UL)

#define	MXC_S_DMA_CFG_REQSEL_SPI0TX (MXC_V_DMA_CFG_REQSEL_SPI0TX << MXC_F_DMA_CFG_REQSEL_POS)

#define	MXC_V_DMA_CFG_REQSEL_SPI1TX ((uint32_t)0x22UL)

#define	MXC_S_DMA_CFG_REQSEL_SPI1TX (MXC_V_DMA_CFG_REQSEL_SPI1TX << MXC_F_DMA_CFG_REQSEL_POS)

#define	MXC_V_DMA_CFG_REQSEL_I2C0TX ((uint32_t)0x27UL)

#define	MXC_S_DMA_CFG_REQSEL_I2C0TX (MXC_V_DMA_CFG_REQSEL_I2C0TX << MXC_F_DMA_CFG_REQSEL_POS)

#define	MXC_V_DMA_CFG_REQSEL_UART0TX ((uint32_t)0x3CUL)

#define	MXC_S_DMA_CFG_REQSEL_UART0TX (MXC_V_DMA_CFG_REQSEL_UART0TX << MXC_F_DMA_CFG_REQSEL_POS)

#define	MXC_F_DMA_CFG_REQWAIT_POS 10

#define	MXC_F_DMA_CFG_REQWAIT ((uint32_t)(0x1UL << MXC_F_DMA_CFG_REQWAIT_POS))

#define	MXC_F_DMA_CFG_TOSEL_POS 11

#define	MXC_F_DMA_CFG_TOSEL ((uint32_t)(0x7UL << MXC_F_DMA_CFG_TOSEL_POS))

#define	MXC_V_DMA_CFG_TOSEL_TO4 ((uint32_t)0x0UL)

#define	MXC_S_DMA_CFG_TOSEL_TO4 (MXC_V_DMA_CFG_TOSEL_TO4 << MXC_F_DMA_CFG_TOSEL_POS)

#define	MXC_V_DMA_CFG_TOSEL_TO8 ((uint32_t)0x1UL)

#define	MXC_S_DMA_CFG_TOSEL_TO8 (MXC_V_DMA_CFG_TOSEL_TO8 << MXC_F_DMA_CFG_TOSEL_POS)

#define	MXC_V_DMA_CFG_TOSEL_TO16 ((uint32_t)0x2UL)

#define	MXC_S_DMA_CFG_TOSEL_TO16 (MXC_V_DMA_CFG_TOSEL_TO16 << MXC_F_DMA_CFG_TOSEL_POS)

#define	MXC_V_DMA_CFG_TOSEL_TO32 ((uint32_t)0x3UL)

#define	MXC_S_DMA_CFG_TOSEL_TO32 (MXC_V_DMA_CFG_TOSEL_TO32 << MXC_F_DMA_CFG_TOSEL_POS)

#define	MXC_V_DMA_CFG_TOSEL_TO64 ((uint32_t)0x4UL)

#define	MXC_S_DMA_CFG_TOSEL_TO64 (MXC_V_DMA_CFG_TOSEL_TO64 << MXC_F_DMA_CFG_TOSEL_POS)

#define	MXC_V_DMA_CFG_TOSEL_TO128 ((uint32_t)0x5UL)

#define	MXC_S_DMA_CFG_TOSEL_TO128 (MXC_V_DMA_CFG_TOSEL_TO128 << MXC_F_DMA_CFG_TOSEL_POS)

#define	MXC_V_DMA_CFG_TOSEL_TO256 ((uint32_t)0x6UL)

#define	MXC_S_DMA_CFG_TOSEL_TO256 (MXC_V_DMA_CFG_TOSEL_TO256 << MXC_F_DMA_CFG_TOSEL_POS)

#define	MXC_V_DMA_CFG_TOSEL_TO512 ((uint32_t)0x7UL)

#define	MXC_S_DMA_CFG_TOSEL_TO512 (MXC_V_DMA_CFG_TOSEL_TO512 << MXC_F_DMA_CFG_TOSEL_POS)

#define	MXC_F_DMA_CFG_PSSEL_POS 14

#define	MXC_F_DMA_CFG_PSSEL ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PSSEL_POS))

#define	MXC_V_DMA_CFG_PSSEL_DIS ((uint32_t)0x0UL)

#define	MXC_S_DMA_CFG_PSSEL_DIS (MXC_V_DMA_CFG_PSSEL_DIS << MXC_F_DMA_CFG_PSSEL_POS)

#define	MXC_V_DMA_CFG_PSSEL_DIV256 ((uint32_t)0x1UL)

#define	MXC_S_DMA_CFG_PSSEL_DIV256 (MXC_V_DMA_CFG_PSSEL_DIV256 << MXC_F_DMA_CFG_PSSEL_POS)

#define	MXC_V_DMA_CFG_PSSEL_DIV64K ((uint32_t)0x2UL)

#define	MXC_S_DMA_CFG_PSSEL_DIV64K (MXC_V_DMA_CFG_PSSEL_DIV64K << MXC_F_DMA_CFG_PSSEL_POS)

#define	MXC_V_DMA_CFG_PSSEL_DIV16M ((uint32_t)0x3UL)

#define	MXC_S_DMA_CFG_PSSEL_DIV16M (MXC_V_DMA_CFG_PSSEL_DIV16M << MXC_F_DMA_CFG_PSSEL_POS)

#define	MXC_F_DMA_CFG_SRCWD_POS 16

#define	MXC_F_DMA_CFG_SRCWD ((uint32_t)(0x3UL << MXC_F_DMA_CFG_SRCWD_POS))

#define	MXC_V_DMA_CFG_SRCWD_BYTE ((uint32_t)0x0UL)

#define	MXC_S_DMA_CFG_SRCWD_BYTE (MXC_V_DMA_CFG_SRCWD_BYTE << MXC_F_DMA_CFG_SRCWD_POS)

#define	MXC_V_DMA_CFG_SRCWD_HALFWORD ((uint32_t)0x1UL)

#define	MXC_S_DMA_CFG_SRCWD_HALFWORD (MXC_V_DMA_CFG_SRCWD_HALFWORD << MXC_F_DMA_CFG_SRCWD_POS)

#define	MXC_V_DMA_CFG_SRCWD_WORD ((uint32_t)0x2UL)

#define	MXC_S_DMA_CFG_SRCWD_WORD (MXC_V_DMA_CFG_SRCWD_WORD << MXC_F_DMA_CFG_SRCWD_POS)

#define	MXC_F_DMA_CFG_SRCINC_POS 18

#define	MXC_F_DMA_CFG_SRCINC ((uint32_t)(0x1UL << MXC_F_DMA_CFG_SRCINC_POS))

#define	MXC_F_DMA_CFG_DSTWD_POS 20

#define	MXC_F_DMA_CFG_DSTWD ((uint32_t)(0x3UL << MXC_F_DMA_CFG_DSTWD_POS))

#define	MXC_V_DMA_CFG_DSTWD_BYTE ((uint32_t)0x0UL)

#define	MXC_S_DMA_CFG_DSTWD_BYTE (MXC_V_DMA_CFG_DSTWD_BYTE << MXC_F_DMA_CFG_DSTWD_POS)

#define	MXC_V_DMA_CFG_DSTWD_HALFWORD ((uint32_t)0x1UL)

#define	MXC_S_DMA_CFG_DSTWD_HALFWORD (MXC_V_DMA_CFG_DSTWD_HALFWORD << MXC_F_DMA_CFG_DSTWD_POS)

#define	MXC_V_DMA_CFG_DSTWD_WORD ((uint32_t)0x2UL)

#define	MXC_S_DMA_CFG_DSTWD_WORD (MXC_V_DMA_CFG_DSTWD_WORD << MXC_F_DMA_CFG_DSTWD_POS)

#define	MXC_F_DMA_CFG_DSTINC_POS 22

#define	MXC_F_DMA_CFG_DSTINC ((uint32_t)(0x1UL << MXC_F_DMA_CFG_DSTINC_POS))

#define	MXC_F_DMA_CFG_BRST_POS 24

#define	MXC_F_DMA_CFG_BRST ((uint32_t)(0x1FUL << MXC_F_DMA_CFG_BRST_POS))

#define	MXC_F_DMA_CFG_CHDIEN_POS 30

#define	MXC_F_DMA_CFG_CHDIEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHDIEN_POS))

#define	MXC_F_DMA_CFG_CTZIEN_POS 31

#define	MXC_F_DMA_CFG_CTZIEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CTZIEN_POS))

Detailed Description

DMA Channel Configuration Register.

Macro Definition Documentation

◆ MXC_F_DMA_CFG_BRST

#define MXC_F_DMA_CFG_BRST ((uint32_t)(0x1FUL << MXC_F_DMA_CFG_BRST_POS))

CFG_BRST Mask

◆ MXC_F_DMA_CFG_BRST_POS

#define MXC_F_DMA_CFG_BRST_POS 24

CFG_BRST Position

◆ MXC_F_DMA_CFG_CHDIEN

#define MXC_F_DMA_CFG_CHDIEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHDIEN_POS))

CFG_CHDIEN Mask

◆ MXC_F_DMA_CFG_CHDIEN_POS

#define MXC_F_DMA_CFG_CHDIEN_POS 30

CFG_CHDIEN Position

◆ MXC_F_DMA_CFG_CHIEN

#define MXC_F_DMA_CFG_CHIEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHIEN_POS))

CFG_CHIEN Mask

◆ MXC_F_DMA_CFG_CHIEN_POS

#define MXC_F_DMA_CFG_CHIEN_POS 0

CFG_CHIEN Position

◆ MXC_F_DMA_CFG_CTZIEN

#define MXC_F_DMA_CFG_CTZIEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CTZIEN_POS))

CFG_CTZIEN Mask

◆ MXC_F_DMA_CFG_CTZIEN_POS

#define MXC_F_DMA_CFG_CTZIEN_POS 31

CFG_CTZIEN Position

◆ MXC_F_DMA_CFG_DSTINC

#define MXC_F_DMA_CFG_DSTINC ((uint32_t)(0x1UL << MXC_F_DMA_CFG_DSTINC_POS))

CFG_DSTINC Mask

◆ MXC_F_DMA_CFG_DSTINC_POS

#define MXC_F_DMA_CFG_DSTINC_POS 22

CFG_DSTINC Position

◆ MXC_F_DMA_CFG_DSTWD

#define MXC_F_DMA_CFG_DSTWD ((uint32_t)(0x3UL << MXC_F_DMA_CFG_DSTWD_POS))

CFG_DSTWD Mask

◆ MXC_F_DMA_CFG_DSTWD_POS

#define MXC_F_DMA_CFG_DSTWD_POS 20

CFG_DSTWD Position

◆ MXC_F_DMA_CFG_PRI

#define MXC_F_DMA_CFG_PRI ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PRI_POS))

CFG_PRI Mask

◆ MXC_F_DMA_CFG_PRI_POS

#define MXC_F_DMA_CFG_PRI_POS 2

CFG_PRI Position

◆ MXC_F_DMA_CFG_PSSEL

#define MXC_F_DMA_CFG_PSSEL ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PSSEL_POS))

CFG_PSSEL Mask

◆ MXC_F_DMA_CFG_PSSEL_POS

#define MXC_F_DMA_CFG_PSSEL_POS 14

CFG_PSSEL Position

◆ MXC_F_DMA_CFG_REQSEL

#define MXC_F_DMA_CFG_REQSEL ((uint32_t)(0x3FUL << MXC_F_DMA_CFG_REQSEL_POS))

CFG_REQSEL Mask

◆ MXC_F_DMA_CFG_REQSEL_POS

#define MXC_F_DMA_CFG_REQSEL_POS 4

CFG_REQSEL Position

◆ MXC_F_DMA_CFG_REQWAIT

#define MXC_F_DMA_CFG_REQWAIT ((uint32_t)(0x1UL << MXC_F_DMA_CFG_REQWAIT_POS))

CFG_REQWAIT Mask

◆ MXC_F_DMA_CFG_REQWAIT_POS

#define MXC_F_DMA_CFG_REQWAIT_POS 10

CFG_REQWAIT Position

◆ MXC_F_DMA_CFG_RLDEN

#define MXC_F_DMA_CFG_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_RLDEN_POS))

CFG_RLDEN Mask

◆ MXC_F_DMA_CFG_RLDEN_POS

#define MXC_F_DMA_CFG_RLDEN_POS 1

CFG_RLDEN Position

◆ MXC_F_DMA_CFG_SRCINC

#define MXC_F_DMA_CFG_SRCINC ((uint32_t)(0x1UL << MXC_F_DMA_CFG_SRCINC_POS))

CFG_SRCINC Mask

◆ MXC_F_DMA_CFG_SRCINC_POS

#define MXC_F_DMA_CFG_SRCINC_POS 18

CFG_SRCINC Position

◆ MXC_F_DMA_CFG_SRCWD

#define MXC_F_DMA_CFG_SRCWD ((uint32_t)(0x3UL << MXC_F_DMA_CFG_SRCWD_POS))

CFG_SRCWD Mask

◆ MXC_F_DMA_CFG_SRCWD_POS

#define MXC_F_DMA_CFG_SRCWD_POS 16

CFG_SRCWD Position

◆ MXC_F_DMA_CFG_TOSEL

#define MXC_F_DMA_CFG_TOSEL ((uint32_t)(0x7UL << MXC_F_DMA_CFG_TOSEL_POS))

CFG_TOSEL Mask

◆ MXC_F_DMA_CFG_TOSEL_POS

#define MXC_F_DMA_CFG_TOSEL_POS 11

CFG_TOSEL Position

◆ MXC_S_DMA_CFG_DSTWD_BYTE

#define MXC_S_DMA_CFG_DSTWD_BYTE (MXC_V_DMA_CFG_DSTWD_BYTE << MXC_F_DMA_CFG_DSTWD_POS)

CFG_DSTWD_BYTE Setting

◆ MXC_S_DMA_CFG_DSTWD_HALFWORD

#define MXC_S_DMA_CFG_DSTWD_HALFWORD (MXC_V_DMA_CFG_DSTWD_HALFWORD << MXC_F_DMA_CFG_DSTWD_POS)

CFG_DSTWD_HALFWORD Setting

◆ MXC_S_DMA_CFG_DSTWD_WORD

#define MXC_S_DMA_CFG_DSTWD_WORD (MXC_V_DMA_CFG_DSTWD_WORD << MXC_F_DMA_CFG_DSTWD_POS)

CFG_DSTWD_WORD Setting

◆ MXC_S_DMA_CFG_PRI_HIGH

#define MXC_S_DMA_CFG_PRI_HIGH (MXC_V_DMA_CFG_PRI_HIGH << MXC_F_DMA_CFG_PRI_POS)

CFG_PRI_HIGH Setting

◆ MXC_S_DMA_CFG_PRI_LOW

#define MXC_S_DMA_CFG_PRI_LOW (MXC_V_DMA_CFG_PRI_LOW << MXC_F_DMA_CFG_PRI_POS)

CFG_PRI_LOW Setting

◆ MXC_S_DMA_CFG_PRI_MEDHIGH

#define MXC_S_DMA_CFG_PRI_MEDHIGH (MXC_V_DMA_CFG_PRI_MEDHIGH << MXC_F_DMA_CFG_PRI_POS)

CFG_PRI_MEDHIGH Setting

◆ MXC_S_DMA_CFG_PRI_MEDLOW

#define MXC_S_DMA_CFG_PRI_MEDLOW (MXC_V_DMA_CFG_PRI_MEDLOW << MXC_F_DMA_CFG_PRI_POS)

CFG_PRI_MEDLOW Setting

◆ MXC_S_DMA_CFG_PSSEL_DIS

#define MXC_S_DMA_CFG_PSSEL_DIS (MXC_V_DMA_CFG_PSSEL_DIS << MXC_F_DMA_CFG_PSSEL_POS)

CFG_PSSEL_DIS Setting

◆ MXC_S_DMA_CFG_PSSEL_DIV16M

#define MXC_S_DMA_CFG_PSSEL_DIV16M (MXC_V_DMA_CFG_PSSEL_DIV16M << MXC_F_DMA_CFG_PSSEL_POS)

CFG_PSSEL_DIV16M Setting

◆ MXC_S_DMA_CFG_PSSEL_DIV256

#define MXC_S_DMA_CFG_PSSEL_DIV256 (MXC_V_DMA_CFG_PSSEL_DIV256 << MXC_F_DMA_CFG_PSSEL_POS)

CFG_PSSEL_DIV256 Setting

◆ MXC_S_DMA_CFG_PSSEL_DIV64K

#define MXC_S_DMA_CFG_PSSEL_DIV64K (MXC_V_DMA_CFG_PSSEL_DIV64K << MXC_F_DMA_CFG_PSSEL_POS)

CFG_PSSEL_DIV64K Setting

◆ MXC_S_DMA_CFG_REQSEL_I2C0RX

#define MXC_S_DMA_CFG_REQSEL_I2C0RX (MXC_V_DMA_CFG_REQSEL_I2C0RX << MXC_F_DMA_CFG_REQSEL_POS)

CFG_REQSEL_I2C0RX Setting

◆ MXC_S_DMA_CFG_REQSEL_I2C0TX

#define MXC_S_DMA_CFG_REQSEL_I2C0TX (MXC_V_DMA_CFG_REQSEL_I2C0TX << MXC_F_DMA_CFG_REQSEL_POS)

CFG_REQSEL_I2C0TX Setting

◆ MXC_S_DMA_CFG_REQSEL_MEMTOMEM

#define MXC_S_DMA_CFG_REQSEL_MEMTOMEM (MXC_V_DMA_CFG_REQSEL_MEMTOMEM << MXC_F_DMA_CFG_REQSEL_POS)

CFG_REQSEL_MEMTOMEM Setting

◆ MXC_S_DMA_CFG_REQSEL_SPI0RX

#define MXC_S_DMA_CFG_REQSEL_SPI0RX (MXC_V_DMA_CFG_REQSEL_SPI0RX << MXC_F_DMA_CFG_REQSEL_POS)

CFG_REQSEL_SPI0RX Setting

◆ MXC_S_DMA_CFG_REQSEL_SPI0TX

#define MXC_S_DMA_CFG_REQSEL_SPI0TX (MXC_V_DMA_CFG_REQSEL_SPI0TX << MXC_F_DMA_CFG_REQSEL_POS)

CFG_REQSEL_SPI0TX Setting

◆ MXC_S_DMA_CFG_REQSEL_SPI1RX

#define MXC_S_DMA_CFG_REQSEL_SPI1RX (MXC_V_DMA_CFG_REQSEL_SPI1RX << MXC_F_DMA_CFG_REQSEL_POS)

CFG_REQSEL_SPI1RX Setting

◆ MXC_S_DMA_CFG_REQSEL_SPI1TX

#define MXC_S_DMA_CFG_REQSEL_SPI1TX (MXC_V_DMA_CFG_REQSEL_SPI1TX << MXC_F_DMA_CFG_REQSEL_POS)

CFG_REQSEL_SPI1TX Setting

◆ MXC_S_DMA_CFG_REQSEL_UART0RX

#define MXC_S_DMA_CFG_REQSEL_UART0RX (MXC_V_DMA_CFG_REQSEL_UART0RX << MXC_F_DMA_CFG_REQSEL_POS)

CFG_REQSEL_UART0RX Setting

◆ MXC_S_DMA_CFG_REQSEL_UART0TX

#define MXC_S_DMA_CFG_REQSEL_UART0TX (MXC_V_DMA_CFG_REQSEL_UART0TX << MXC_F_DMA_CFG_REQSEL_POS)

CFG_REQSEL_UART0TX Setting

◆ MXC_S_DMA_CFG_SRCWD_BYTE

#define MXC_S_DMA_CFG_SRCWD_BYTE (MXC_V_DMA_CFG_SRCWD_BYTE << MXC_F_DMA_CFG_SRCWD_POS)

CFG_SRCWD_BYTE Setting

◆ MXC_S_DMA_CFG_SRCWD_HALFWORD

#define MXC_S_DMA_CFG_SRCWD_HALFWORD (MXC_V_DMA_CFG_SRCWD_HALFWORD << MXC_F_DMA_CFG_SRCWD_POS)

CFG_SRCWD_HALFWORD Setting

◆ MXC_S_DMA_CFG_SRCWD_WORD

#define MXC_S_DMA_CFG_SRCWD_WORD (MXC_V_DMA_CFG_SRCWD_WORD << MXC_F_DMA_CFG_SRCWD_POS)

CFG_SRCWD_WORD Setting

◆ MXC_S_DMA_CFG_TOSEL_TO128

#define MXC_S_DMA_CFG_TOSEL_TO128 (MXC_V_DMA_CFG_TOSEL_TO128 << MXC_F_DMA_CFG_TOSEL_POS)

CFG_TOSEL_TO128 Setting

◆ MXC_S_DMA_CFG_TOSEL_TO16

#define MXC_S_DMA_CFG_TOSEL_TO16 (MXC_V_DMA_CFG_TOSEL_TO16 << MXC_F_DMA_CFG_TOSEL_POS)

CFG_TOSEL_TO16 Setting

◆ MXC_S_DMA_CFG_TOSEL_TO256

#define MXC_S_DMA_CFG_TOSEL_TO256 (MXC_V_DMA_CFG_TOSEL_TO256 << MXC_F_DMA_CFG_TOSEL_POS)

CFG_TOSEL_TO256 Setting

◆ MXC_S_DMA_CFG_TOSEL_TO32

#define MXC_S_DMA_CFG_TOSEL_TO32 (MXC_V_DMA_CFG_TOSEL_TO32 << MXC_F_DMA_CFG_TOSEL_POS)

CFG_TOSEL_TO32 Setting

◆ MXC_S_DMA_CFG_TOSEL_TO4

#define MXC_S_DMA_CFG_TOSEL_TO4 (MXC_V_DMA_CFG_TOSEL_TO4 << MXC_F_DMA_CFG_TOSEL_POS)

CFG_TOSEL_TO4 Setting

◆ MXC_S_DMA_CFG_TOSEL_TO512

#define MXC_S_DMA_CFG_TOSEL_TO512 (MXC_V_DMA_CFG_TOSEL_TO512 << MXC_F_DMA_CFG_TOSEL_POS)

CFG_TOSEL_TO512 Setting

◆ MXC_S_DMA_CFG_TOSEL_TO64

#define MXC_S_DMA_CFG_TOSEL_TO64 (MXC_V_DMA_CFG_TOSEL_TO64 << MXC_F_DMA_CFG_TOSEL_POS)

CFG_TOSEL_TO64 Setting

◆ MXC_S_DMA_CFG_TOSEL_TO8

#define MXC_S_DMA_CFG_TOSEL_TO8 (MXC_V_DMA_CFG_TOSEL_TO8 << MXC_F_DMA_CFG_TOSEL_POS)

CFG_TOSEL_TO8 Setting

◆ MXC_V_DMA_CFG_DSTWD_BYTE

#define MXC_V_DMA_CFG_DSTWD_BYTE ((uint32_t)0x0UL)

CFG_DSTWD_BYTE Value

◆ MXC_V_DMA_CFG_DSTWD_HALFWORD

#define MXC_V_DMA_CFG_DSTWD_HALFWORD ((uint32_t)0x1UL)

CFG_DSTWD_HALFWORD Value

◆ MXC_V_DMA_CFG_DSTWD_WORD

#define MXC_V_DMA_CFG_DSTWD_WORD ((uint32_t)0x2UL)

CFG_DSTWD_WORD Value

◆ MXC_V_DMA_CFG_PRI_HIGH

#define MXC_V_DMA_CFG_PRI_HIGH ((uint32_t)0x0UL)

CFG_PRI_HIGH Value

◆ MXC_V_DMA_CFG_PRI_LOW

#define MXC_V_DMA_CFG_PRI_LOW ((uint32_t)0x3UL)

CFG_PRI_LOW Value

◆ MXC_V_DMA_CFG_PRI_MEDHIGH

#define MXC_V_DMA_CFG_PRI_MEDHIGH ((uint32_t)0x1UL)

CFG_PRI_MEDHIGH Value

◆ MXC_V_DMA_CFG_PRI_MEDLOW

#define MXC_V_DMA_CFG_PRI_MEDLOW ((uint32_t)0x2UL)

CFG_PRI_MEDLOW Value

◆ MXC_V_DMA_CFG_PSSEL_DIS

#define MXC_V_DMA_CFG_PSSEL_DIS ((uint32_t)0x0UL)

CFG_PSSEL_DIS Value

◆ MXC_V_DMA_CFG_PSSEL_DIV16M

#define MXC_V_DMA_CFG_PSSEL_DIV16M ((uint32_t)0x3UL)

CFG_PSSEL_DIV16M Value

◆ MXC_V_DMA_CFG_PSSEL_DIV256

#define MXC_V_DMA_CFG_PSSEL_DIV256 ((uint32_t)0x1UL)

CFG_PSSEL_DIV256 Value

◆ MXC_V_DMA_CFG_PSSEL_DIV64K

#define MXC_V_DMA_CFG_PSSEL_DIV64K ((uint32_t)0x2UL)

CFG_PSSEL_DIV64K Value

◆ MXC_V_DMA_CFG_REQSEL_I2C0RX

#define MXC_V_DMA_CFG_REQSEL_I2C0RX ((uint32_t)0x7UL)

CFG_REQSEL_I2C0RX Value

◆ MXC_V_DMA_CFG_REQSEL_I2C0TX

#define MXC_V_DMA_CFG_REQSEL_I2C0TX ((uint32_t)0x27UL)

CFG_REQSEL_I2C0TX Value

◆ MXC_V_DMA_CFG_REQSEL_MEMTOMEM

#define MXC_V_DMA_CFG_REQSEL_MEMTOMEM ((uint32_t)0x0UL)

CFG_REQSEL_MEMTOMEM Value

◆ MXC_V_DMA_CFG_REQSEL_SPI0RX

#define MXC_V_DMA_CFG_REQSEL_SPI0RX ((uint32_t)0x1UL)

CFG_REQSEL_SPI0RX Value

◆ MXC_V_DMA_CFG_REQSEL_SPI0TX

#define MXC_V_DMA_CFG_REQSEL_SPI0TX ((uint32_t)0x21UL)

CFG_REQSEL_SPI0TX Value

◆ MXC_V_DMA_CFG_REQSEL_SPI1RX

#define MXC_V_DMA_CFG_REQSEL_SPI1RX ((uint32_t)0x2UL)

CFG_REQSEL_SPI1RX Value

◆ MXC_V_DMA_CFG_REQSEL_SPI1TX

#define MXC_V_DMA_CFG_REQSEL_SPI1TX ((uint32_t)0x22UL)

CFG_REQSEL_SPI1TX Value

◆ MXC_V_DMA_CFG_REQSEL_UART0RX

#define MXC_V_DMA_CFG_REQSEL_UART0RX ((uint32_t)0x1CUL)

CFG_REQSEL_UART0RX Value

◆ MXC_V_DMA_CFG_REQSEL_UART0TX

#define MXC_V_DMA_CFG_REQSEL_UART0TX ((uint32_t)0x3CUL)

CFG_REQSEL_UART0TX Value

◆ MXC_V_DMA_CFG_SRCWD_BYTE

#define MXC_V_DMA_CFG_SRCWD_BYTE ((uint32_t)0x0UL)

CFG_SRCWD_BYTE Value

◆ MXC_V_DMA_CFG_SRCWD_HALFWORD

#define MXC_V_DMA_CFG_SRCWD_HALFWORD ((uint32_t)0x1UL)

CFG_SRCWD_HALFWORD Value

◆ MXC_V_DMA_CFG_SRCWD_WORD

#define MXC_V_DMA_CFG_SRCWD_WORD ((uint32_t)0x2UL)

CFG_SRCWD_WORD Value

◆ MXC_V_DMA_CFG_TOSEL_TO128

#define MXC_V_DMA_CFG_TOSEL_TO128 ((uint32_t)0x5UL)

CFG_TOSEL_TO128 Value

◆ MXC_V_DMA_CFG_TOSEL_TO16

#define MXC_V_DMA_CFG_TOSEL_TO16 ((uint32_t)0x2UL)

CFG_TOSEL_TO16 Value

◆ MXC_V_DMA_CFG_TOSEL_TO256

#define MXC_V_DMA_CFG_TOSEL_TO256 ((uint32_t)0x6UL)

CFG_TOSEL_TO256 Value

◆ MXC_V_DMA_CFG_TOSEL_TO32

#define MXC_V_DMA_CFG_TOSEL_TO32 ((uint32_t)0x3UL)

CFG_TOSEL_TO32 Value

◆ MXC_V_DMA_CFG_TOSEL_TO4

#define MXC_V_DMA_CFG_TOSEL_TO4 ((uint32_t)0x0UL)

CFG_TOSEL_TO4 Value

◆ MXC_V_DMA_CFG_TOSEL_TO512

#define MXC_V_DMA_CFG_TOSEL_TO512 ((uint32_t)0x7UL)

CFG_TOSEL_TO512 Value

◆ MXC_V_DMA_CFG_TOSEL_TO64

#define MXC_V_DMA_CFG_TOSEL_TO64 ((uint32_t)0x4UL)

CFG_TOSEL_TO64 Value

◆ MXC_V_DMA_CFG_TOSEL_TO8

#define MXC_V_DMA_CFG_TOSEL_TO8 ((uint32_t)0x1UL)

CFG_TOSEL_TO8 Value

Macros