Macros
#define	MXC_F_SFE_CFG_DRLE_POS 0

#define	MXC_F_SFE_CFG_DRLE ((uint32_t)(0x1UL << MXC_F_SFE_CFG_DRLE_POS))

#define	MXC_F_SFE_CFG_FLOCK_POS 15

#define	MXC_F_SFE_CFG_FLOCK ((uint32_t)(0x1UL << MXC_F_SFE_CFG_FLOCK_POS))

#define	MXC_F_SFE_CFG_RD_EN_POS 16

#define	MXC_F_SFE_CFG_RD_EN ((uint32_t)(0x1UL << MXC_F_SFE_CFG_RD_EN_POS))

#define	MXC_F_SFE_CFG_WR_EN_POS 17

#define	MXC_F_SFE_CFG_WR_EN ((uint32_t)(0x1UL << MXC_F_SFE_CFG_WR_EN_POS))

#define	MXC_F_SFE_CFG_RRLOCK_POS 22

#define	MXC_F_SFE_CFG_RRLOCK ((uint32_t)(0x1UL << MXC_F_SFE_CFG_RRLOCK_POS))

#define	MXC_F_SFE_CFG_RWLOCK_POS 23

#define	MXC_F_SFE_CFG_RWLOCK ((uint32_t)(0x1UL << MXC_F_SFE_CFG_RWLOCK_POS))

Detailed Description

SFE Configuration Register.

Macro Definition Documentation

◆ MXC_F_SFE_CFG_DRLE

#define MXC_F_SFE_CFG_DRLE ((uint32_t)(0x1UL << MXC_F_SFE_CFG_DRLE_POS))

CFG_DRLE Mask

◆ MXC_F_SFE_CFG_DRLE_POS

#define MXC_F_SFE_CFG_DRLE_POS 0

CFG_DRLE Position

◆ MXC_F_SFE_CFG_FLOCK

#define MXC_F_SFE_CFG_FLOCK ((uint32_t)(0x1UL << MXC_F_SFE_CFG_FLOCK_POS))

CFG_FLOCK Mask

◆ MXC_F_SFE_CFG_FLOCK_POS

#define MXC_F_SFE_CFG_FLOCK_POS 15

CFG_FLOCK Position

◆ MXC_F_SFE_CFG_RD_EN

#define MXC_F_SFE_CFG_RD_EN ((uint32_t)(0x1UL << MXC_F_SFE_CFG_RD_EN_POS))

CFG_RD_EN Mask

◆ MXC_F_SFE_CFG_RD_EN_POS

#define MXC_F_SFE_CFG_RD_EN_POS 16

CFG_RD_EN Position

◆ MXC_F_SFE_CFG_RRLOCK

#define MXC_F_SFE_CFG_RRLOCK ((uint32_t)(0x1UL << MXC_F_SFE_CFG_RRLOCK_POS))

CFG_RRLOCK Mask

◆ MXC_F_SFE_CFG_RRLOCK_POS

#define MXC_F_SFE_CFG_RRLOCK_POS 22

CFG_RRLOCK Position

◆ MXC_F_SFE_CFG_RWLOCK

#define MXC_F_SFE_CFG_RWLOCK ((uint32_t)(0x1UL << MXC_F_SFE_CFG_RWLOCK_POS))

CFG_RWLOCK Mask

◆ MXC_F_SFE_CFG_RWLOCK_POS

#define MXC_F_SFE_CFG_RWLOCK_POS 23

CFG_RWLOCK Position

◆ MXC_F_SFE_CFG_WR_EN

#define MXC_F_SFE_CFG_WR_EN ((uint32_t)(0x1UL << MXC_F_SFE_CFG_WR_EN_POS))

CFG_WR_EN Mask

◆ MXC_F_SFE_CFG_WR_EN_POS

#define MXC_F_SFE_CFG_WR_EN_POS 17

CFG_WR_EN Position

Macros