MAX32650 Peripheral Driver API
Peripheral Driver API for the MAX32650
emcc_regs.h
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1
8/******************************************************************************
9 *
10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
11 * Analog Devices, Inc.),
12 * Copyright (C) 2023-2024 Analog Devices, Inc.
13 *
14 * Licensed under the Apache License, Version 2.0 (the "License");
15 * you may not use this file except in compliance with the License.
16 * You may obtain a copy of the License at
17 *
18 * http://www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an "AS IS" BASIS,
22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *
26 ******************************************************************************/
27
28#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_EMCC_REGS_H_
29#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_EMCC_REGS_H_
30
31/* **** Includes **** */
32#include <stdint.h>
33
34#ifdef __cplusplus
35extern "C" {
36#endif
37
38#if defined (__ICCARM__)
39 #pragma system_include
40#endif
41
42#if defined (__CC_ARM)
43 #pragma anon_unions
44#endif
46/*
47 If types are not defined elsewhere (CMSIS) define them here
48*/
49#ifndef __IO
50#define __IO volatile
51#endif
52#ifndef __I
53#define __I volatile const
54#endif
55#ifndef __O
56#define __O volatile
57#endif
58#ifndef __R
59#define __R volatile const
60#endif
62
63/* **** Definitions **** */
64
76typedef struct {
77 __I uint32_t cache_id;
78 __I uint32_t mem_size;
79 __R uint32_t rsv_0x8_0xff[62];
80 __IO uint32_t cache_ctrl;
81 __R uint32_t rsv_0x104_0x6ff[383];
82 __IO uint32_t invalidate;
83} mxc_emcc_regs_t;
84
85/* Register offsets for module EMCC */
92#define MXC_R_EMCC_CACHE_ID ((uint32_t)0x00000000UL)
93#define MXC_R_EMCC_MEM_SIZE ((uint32_t)0x00000004UL)
94#define MXC_R_EMCC_CACHE_CTRL ((uint32_t)0x00000100UL)
95#define MXC_R_EMCC_INVALIDATE ((uint32_t)0x00000700UL)
104#define MXC_F_EMCC_CACHE_ID_RELNUM_POS 0
105#define MXC_F_EMCC_CACHE_ID_RELNUM ((uint32_t)(0x3FUL << MXC_F_EMCC_CACHE_ID_RELNUM_POS))
107#define MXC_F_EMCC_CACHE_ID_PARTNUM_POS 6
108#define MXC_F_EMCC_CACHE_ID_PARTNUM ((uint32_t)(0xFUL << MXC_F_EMCC_CACHE_ID_PARTNUM_POS))
110#define MXC_F_EMCC_CACHE_ID_CCHID_POS 10
111#define MXC_F_EMCC_CACHE_ID_CCHID ((uint32_t)(0x3FUL << MXC_F_EMCC_CACHE_ID_CCHID_POS))
121#define MXC_F_EMCC_MEM_SIZE_CCHSZ_POS 0
122#define MXC_F_EMCC_MEM_SIZE_CCHSZ ((uint32_t)(0xFFFFUL << MXC_F_EMCC_MEM_SIZE_CCHSZ_POS))
124#define MXC_F_EMCC_MEM_SIZE_MEMSZ_POS 16
125#define MXC_F_EMCC_MEM_SIZE_MEMSZ ((uint32_t)(0xFFFFUL << MXC_F_EMCC_MEM_SIZE_MEMSZ_POS))
135#define MXC_F_EMCC_CACHE_CTRL_ENABLE_POS 0
136#define MXC_F_EMCC_CACHE_CTRL_ENABLE ((uint32_t)(0x1UL << MXC_F_EMCC_CACHE_CTRL_ENABLE_POS))
137#define MXC_V_EMCC_CACHE_CTRL_ENABLE_DIS ((uint32_t)0x0UL)
138#define MXC_S_EMCC_CACHE_CTRL_ENABLE_DIS (MXC_V_EMCC_CACHE_CTRL_ENABLE_DIS << MXC_F_EMCC_CACHE_CTRL_ENABLE_POS)
139#define MXC_V_EMCC_CACHE_CTRL_ENABLE_EN ((uint32_t)0x1UL)
140#define MXC_S_EMCC_CACHE_CTRL_ENABLE_EN (MXC_V_EMCC_CACHE_CTRL_ENABLE_EN << MXC_F_EMCC_CACHE_CTRL_ENABLE_POS)
142#define MXC_F_EMCC_CACHE_CTRL_WRITE_ALLOC_POS 1
143#define MXC_F_EMCC_CACHE_CTRL_WRITE_ALLOC ((uint32_t)(0x1UL << MXC_F_EMCC_CACHE_CTRL_WRITE_ALLOC_POS))
144#define MXC_V_EMCC_CACHE_CTRL_WRITE_ALLOC_DIS ((uint32_t)0x0UL)
145#define MXC_S_EMCC_CACHE_CTRL_WRITE_ALLOC_DIS (MXC_V_EMCC_CACHE_CTRL_WRITE_ALLOC_DIS << MXC_F_EMCC_CACHE_CTRL_WRITE_ALLOC_POS)
146#define MXC_V_EMCC_CACHE_CTRL_WRITE_ALLOC_EN ((uint32_t)0x1UL)
147#define MXC_S_EMCC_CACHE_CTRL_WRITE_ALLOC_EN (MXC_V_EMCC_CACHE_CTRL_WRITE_ALLOC_EN << MXC_F_EMCC_CACHE_CTRL_WRITE_ALLOC_POS)
149#define MXC_F_EMCC_CACHE_CTRL_CWFST_DIS_POS 2
150#define MXC_F_EMCC_CACHE_CTRL_CWFST_DIS ((uint32_t)(0x1UL << MXC_F_EMCC_CACHE_CTRL_CWFST_DIS_POS))
151#define MXC_V_EMCC_CACHE_CTRL_CWFST_DIS_DIS ((uint32_t)0x1UL)
152#define MXC_S_EMCC_CACHE_CTRL_CWFST_DIS_DIS (MXC_V_EMCC_CACHE_CTRL_CWFST_DIS_DIS << MXC_F_EMCC_CACHE_CTRL_CWFST_DIS_POS)
153#define MXC_V_EMCC_CACHE_CTRL_CWFST_DIS_EN ((uint32_t)0x0UL)
154#define MXC_S_EMCC_CACHE_CTRL_CWFST_DIS_EN (MXC_V_EMCC_CACHE_CTRL_CWFST_DIS_EN << MXC_F_EMCC_CACHE_CTRL_CWFST_DIS_POS)
156#define MXC_F_EMCC_CACHE_CTRL_READY_POS 16
157#define MXC_F_EMCC_CACHE_CTRL_READY ((uint32_t)(0x1UL << MXC_F_EMCC_CACHE_CTRL_READY_POS))
158#define MXC_V_EMCC_CACHE_CTRL_READY_NOTREADY ((uint32_t)0x0UL)
159#define MXC_S_EMCC_CACHE_CTRL_READY_NOTREADY (MXC_V_EMCC_CACHE_CTRL_READY_NOTREADY << MXC_F_EMCC_CACHE_CTRL_READY_POS)
160#define MXC_V_EMCC_CACHE_CTRL_READY_READY ((uint32_t)0x1UL)
161#define MXC_S_EMCC_CACHE_CTRL_READY_READY (MXC_V_EMCC_CACHE_CTRL_READY_READY << MXC_F_EMCC_CACHE_CTRL_READY_POS)
178#define MXC_F_EMCC_INVALIDATE_IA_POS 0
179#define MXC_F_EMCC_INVALIDATE_IA ((uint32_t)(0xFFFFFFFFUL << MXC_F_EMCC_INVALIDATE_IA_POS))
183#ifdef __cplusplus
184}
185#endif
186
187#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_EMCC_REGS_H_
mxc_emcc_regs_t::cache_ctrl
__IO uint32_t cache_ctrl
Definition: emcc_regs.h:80
mxc_emcc_regs_t::cache_id
__I uint32_t cache_id
Definition: emcc_regs.h:77
mxc_emcc_regs_t::mem_size
__I uint32_t mem_size
Definition: emcc_regs.h:78
mxc_emcc_regs_t::invalidate
__IO uint32_t invalidate
Definition: emcc_regs.h:82
mxc_emcc_regs_t
Definition: emcc_regs.h:76