![]() |
MAX32650 Peripheral Driver API
Peripheral Driver API for the MAX32650
|
LCD Control Register.
#define MXC_F_CLCD_CTRL_BPP ((uint32_t)(0x7UL << MXC_F_CLCD_CTRL_BPP_POS)) |
CTRL_BPP Mask
#define MXC_F_CLCD_CTRL_BPP_POS 8 |
CTRL_BPP Position
#define MXC_F_CLCD_CTRL_BURST_SIZE ((uint32_t)(0x3UL << MXC_F_CLCD_CTRL_BURST_SIZE_POS)) |
CTRL_BURST_SIZE Mask
#define MXC_F_CLCD_CTRL_BURST_SIZE_POS 19 |
CTRL_BURST_SIZE Position
#define MXC_F_CLCD_CTRL_CLCD_ENABLE ((uint32_t)(0x1UL << MXC_F_CLCD_CTRL_CLCD_ENABLE_POS)) |
CTRL_CLCD_ENABLE Mask
#define MXC_F_CLCD_CTRL_CLCD_ENABLE_POS 0 |
CTRL_CLCD_ENABLE Position
#define MXC_F_CLCD_CTRL_COMPACT_24B ((uint32_t)(0x1UL << MXC_F_CLCD_CTRL_COMPACT_24B_POS)) |
CTRL_COMPACT_24B Mask
#define MXC_F_CLCD_CTRL_COMPACT_24B_POS 15 |
CTRL_COMPACT_24B Position
#define MXC_F_CLCD_CTRL_DISPTYPE ((uint32_t)(0xFUL << MXC_F_CLCD_CTRL_DISPTYPE_POS)) |
CTRL_DISPTYPE Mask
#define MXC_F_CLCD_CTRL_DISPTYPE_POS 4 |
CTRL_DISPTYPE Position
#define MXC_F_CLCD_CTRL_ENDIAN ((uint32_t)(0x3UL << MXC_F_CLCD_CTRL_ENDIAN_POS)) |
CTRL_ENDIAN Mask
#define MXC_F_CLCD_CTRL_ENDIAN_POS 12 |
CTRL_ENDIAN Position
#define MXC_F_CLCD_CTRL_LEND_POL ((uint32_t)(0x1UL << MXC_F_CLCD_CTRL_LEND_POL_POS)) |
CTRL_LEND_POL Mask
#define MXC_F_CLCD_CTRL_LEND_POL_POS 21 |
CTRL_LEND_POL Position
#define MXC_F_CLCD_CTRL_MODE565 ((uint32_t)(0x1UL << MXC_F_CLCD_CTRL_MODE565_POS)) |
CTRL_MODE565 Mask
#define MXC_F_CLCD_CTRL_MODE565_POS 11 |
CTRL_MODE565 Position
#define MXC_F_CLCD_CTRL_PWR_ENABLE ((uint32_t)(0x1UL << MXC_F_CLCD_CTRL_PWR_ENABLE_POS)) |
CTRL_PWR_ENABLE Mask
#define MXC_F_CLCD_CTRL_PWR_ENABLE_POS 22 |
CTRL_PWR_ENABLE Position
#define MXC_F_CLCD_CTRL_VCI_SEL ((uint32_t)(0x3UL << MXC_F_CLCD_CTRL_VCI_SEL_POS)) |
CTRL_VCI_SEL Mask
#define MXC_F_CLCD_CTRL_VCI_SEL_POS 1 |
CTRL_VCI_SEL Position
#define MXC_S_CLCD_CTRL_BPP_BPP1 (MXC_V_CLCD_CTRL_BPP_BPP1 << MXC_F_CLCD_CTRL_BPP_POS) |
CTRL_BPP_BPP1 Setting
#define MXC_S_CLCD_CTRL_BPP_BPP16 (MXC_V_CLCD_CTRL_BPP_BPP16 << MXC_F_CLCD_CTRL_BPP_POS) |
CTRL_BPP_BPP16 Setting
#define MXC_S_CLCD_CTRL_BPP_BPP2 (MXC_V_CLCD_CTRL_BPP_BPP2 << MXC_F_CLCD_CTRL_BPP_POS) |
CTRL_BPP_BPP2 Setting
#define MXC_S_CLCD_CTRL_BPP_BPP24 (MXC_V_CLCD_CTRL_BPP_BPP24 << MXC_F_CLCD_CTRL_BPP_POS) |
CTRL_BPP_BPP24 Setting
#define MXC_S_CLCD_CTRL_BPP_BPP4 (MXC_V_CLCD_CTRL_BPP_BPP4 << MXC_F_CLCD_CTRL_BPP_POS) |
CTRL_BPP_BPP4 Setting
#define MXC_S_CLCD_CTRL_BPP_BPP8 (MXC_V_CLCD_CTRL_BPP_BPP8 << MXC_F_CLCD_CTRL_BPP_POS) |
CTRL_BPP_BPP8 Setting
#define MXC_S_CLCD_CTRL_BURST_SIZE_16WORDS (MXC_V_CLCD_CTRL_BURST_SIZE_16WORDS << MXC_F_CLCD_CTRL_BURST_SIZE_POS) |
CTRL_BURST_SIZE_16WORDS Setting
#define MXC_S_CLCD_CTRL_BURST_SIZE_4WORDS (MXC_V_CLCD_CTRL_BURST_SIZE_4WORDS << MXC_F_CLCD_CTRL_BURST_SIZE_POS) |
CTRL_BURST_SIZE_4WORDS Setting
#define MXC_S_CLCD_CTRL_BURST_SIZE_8WORDS (MXC_V_CLCD_CTRL_BURST_SIZE_8WORDS << MXC_F_CLCD_CTRL_BURST_SIZE_POS) |
CTRL_BURST_SIZE_8WORDS Setting
#define MXC_S_CLCD_CTRL_CLCD_ENABLE_DIS (MXC_V_CLCD_CTRL_CLCD_ENABLE_DIS << MXC_F_CLCD_CTRL_CLCD_ENABLE_POS) |
CTRL_CLCD_ENABLE_DIS Setting
#define MXC_S_CLCD_CTRL_CLCD_ENABLE_EN (MXC_V_CLCD_CTRL_CLCD_ENABLE_EN << MXC_F_CLCD_CTRL_CLCD_ENABLE_POS) |
CTRL_CLCD_ENABLE_EN Setting
#define MXC_S_CLCD_CTRL_COMPACT_24B_1_PFR (MXC_V_CLCD_CTRL_COMPACT_24B_1_PFR << MXC_F_CLCD_CTRL_COMPACT_24B_POS) |
CTRL_COMPACT_24B_1_PFR Setting
#define MXC_S_CLCD_CTRL_COMPACT_24B_1ANDA3RD_PFR (MXC_V_CLCD_CTRL_COMPACT_24B_1ANDA3RD_PFR << MXC_F_CLCD_CTRL_COMPACT_24B_POS) |
CTRL_COMPACT_24B_1ANDA3RD_PFR Setting
#define MXC_S_CLCD_CTRL_DISPTYPE_8BITCOLORSTN (MXC_V_CLCD_CTRL_DISPTYPE_8BITCOLORSTN << MXC_F_CLCD_CTRL_DISPTYPE_POS) |
CTRL_DISPTYPE_8BITCOLORSTN Setting
#define MXC_S_CLCD_CTRL_DISPTYPE_TFT (MXC_V_CLCD_CTRL_DISPTYPE_TFT << MXC_F_CLCD_CTRL_DISPTYPE_POS) |
CTRL_DISPTYPE_TFT Setting
#define MXC_S_CLCD_CTRL_ENDIAN_BBBP (MXC_V_CLCD_CTRL_ENDIAN_BBBP << MXC_F_CLCD_CTRL_ENDIAN_POS) |
CTRL_ENDIAN_BBBP Setting
#define MXC_S_CLCD_CTRL_ENDIAN_LBBP (MXC_V_CLCD_CTRL_ENDIAN_LBBP << MXC_F_CLCD_CTRL_ENDIAN_POS) |
CTRL_ENDIAN_LBBP Setting
#define MXC_S_CLCD_CTRL_ENDIAN_LBLP (MXC_V_CLCD_CTRL_ENDIAN_LBLP << MXC_F_CLCD_CTRL_ENDIAN_POS) |
CTRL_ENDIAN_LBLP Setting
#define MXC_S_CLCD_CTRL_ENDIAN_RFU (MXC_V_CLCD_CTRL_ENDIAN_RFU << MXC_F_CLCD_CTRL_ENDIAN_POS) |
CTRL_ENDIAN_RFU Setting
#define MXC_S_CLCD_CTRL_LEND_POL_ACTIVEHI (MXC_V_CLCD_CTRL_LEND_POL_ACTIVEHI << MXC_F_CLCD_CTRL_LEND_POL_POS) |
CTRL_LEND_POL_ACTIVEHI Setting
#define MXC_S_CLCD_CTRL_LEND_POL_ACTIVELO (MXC_V_CLCD_CTRL_LEND_POL_ACTIVELO << MXC_F_CLCD_CTRL_LEND_POL_POS) |
CTRL_LEND_POL_ACTIVELO Setting
#define MXC_S_CLCD_CTRL_MODE565_BGR556 (MXC_V_CLCD_CTRL_MODE565_BGR556 << MXC_F_CLCD_CTRL_MODE565_POS) |
CTRL_MODE565_BGR556 Setting
#define MXC_S_CLCD_CTRL_MODE565_RGB565 (MXC_V_CLCD_CTRL_MODE565_RGB565 << MXC_F_CLCD_CTRL_MODE565_POS) |
CTRL_MODE565_RGB565 Setting
#define MXC_S_CLCD_CTRL_PWR_ENABLE_HI (MXC_V_CLCD_CTRL_PWR_ENABLE_HI << MXC_F_CLCD_CTRL_PWR_ENABLE_POS) |
CTRL_PWR_ENABLE_HI Setting
#define MXC_S_CLCD_CTRL_PWR_ENABLE_LO (MXC_V_CLCD_CTRL_PWR_ENABLE_LO << MXC_F_CLCD_CTRL_PWR_ENABLE_POS) |
CTRL_PWR_ENABLE_LO Setting
#define MXC_S_CLCD_CTRL_VCI_SEL_ON_VBP (MXC_V_CLCD_CTRL_VCI_SEL_ON_VBP << MXC_F_CLCD_CTRL_VCI_SEL_POS) |
CTRL_VCI_SEL_ON_VBP Setting
#define MXC_S_CLCD_CTRL_VCI_SEL_ON_VDEN (MXC_V_CLCD_CTRL_VCI_SEL_ON_VDEN << MXC_F_CLCD_CTRL_VCI_SEL_POS) |
CTRL_VCI_SEL_ON_VDEN Setting
#define MXC_S_CLCD_CTRL_VCI_SEL_ON_VFP (MXC_V_CLCD_CTRL_VCI_SEL_ON_VFP << MXC_F_CLCD_CTRL_VCI_SEL_POS) |
CTRL_VCI_SEL_ON_VFP Setting
#define MXC_S_CLCD_CTRL_VCI_SEL_ON_VSYNC (MXC_V_CLCD_CTRL_VCI_SEL_ON_VSYNC << MXC_F_CLCD_CTRL_VCI_SEL_POS) |
CTRL_VCI_SEL_ON_VSYNC Setting
#define MXC_V_CLCD_CTRL_BPP_BPP1 ((uint32_t)0x0UL) |
CTRL_BPP_BPP1 Value
#define MXC_V_CLCD_CTRL_BPP_BPP16 ((uint32_t)0x4UL) |
CTRL_BPP_BPP16 Value
#define MXC_V_CLCD_CTRL_BPP_BPP2 ((uint32_t)0x1UL) |
CTRL_BPP_BPP2 Value
#define MXC_V_CLCD_CTRL_BPP_BPP24 ((uint32_t)0x5UL) |
CTRL_BPP_BPP24 Value
#define MXC_V_CLCD_CTRL_BPP_BPP4 ((uint32_t)0x2UL) |
CTRL_BPP_BPP4 Value
#define MXC_V_CLCD_CTRL_BPP_BPP8 ((uint32_t)0x3UL) |
CTRL_BPP_BPP8 Value
#define MXC_V_CLCD_CTRL_BURST_SIZE_16WORDS ((uint32_t)0x2UL) |
CTRL_BURST_SIZE_16WORDS Value
#define MXC_V_CLCD_CTRL_BURST_SIZE_4WORDS ((uint32_t)0x0UL) |
CTRL_BURST_SIZE_4WORDS Value
#define MXC_V_CLCD_CTRL_BURST_SIZE_8WORDS ((uint32_t)0x1UL) |
CTRL_BURST_SIZE_8WORDS Value
#define MXC_V_CLCD_CTRL_CLCD_ENABLE_DIS ((uint32_t)0x0UL) |
CTRL_CLCD_ENABLE_DIS Value
#define MXC_V_CLCD_CTRL_CLCD_ENABLE_EN ((uint32_t)0x1UL) |
CTRL_CLCD_ENABLE_EN Value
#define MXC_V_CLCD_CTRL_COMPACT_24B_1_PFR ((uint32_t)0x0UL) |
CTRL_COMPACT_24B_1_PFR Value
#define MXC_V_CLCD_CTRL_COMPACT_24B_1ANDA3RD_PFR ((uint32_t)0x1UL) |
CTRL_COMPACT_24B_1ANDA3RD_PFR Value
#define MXC_V_CLCD_CTRL_DISPTYPE_8BITCOLORSTN ((uint32_t)0x4UL) |
CTRL_DISPTYPE_8BITCOLORSTN Value
#define MXC_V_CLCD_CTRL_DISPTYPE_TFT ((uint32_t)0x8UL) |
CTRL_DISPTYPE_TFT Value
#define MXC_V_CLCD_CTRL_ENDIAN_BBBP ((uint32_t)0x1UL) |
CTRL_ENDIAN_BBBP Value
#define MXC_V_CLCD_CTRL_ENDIAN_LBBP ((uint32_t)0x2UL) |
CTRL_ENDIAN_LBBP Value
#define MXC_V_CLCD_CTRL_ENDIAN_LBLP ((uint32_t)0x0UL) |
CTRL_ENDIAN_LBLP Value
#define MXC_V_CLCD_CTRL_ENDIAN_RFU ((uint32_t)0x3UL) |
CTRL_ENDIAN_RFU Value
#define MXC_V_CLCD_CTRL_LEND_POL_ACTIVEHI ((uint32_t)0x1UL) |
CTRL_LEND_POL_ACTIVEHI Value
#define MXC_V_CLCD_CTRL_LEND_POL_ACTIVELO ((uint32_t)0x0UL) |
CTRL_LEND_POL_ACTIVELO Value
#define MXC_V_CLCD_CTRL_MODE565_BGR556 ((uint32_t)0x0UL) |
CTRL_MODE565_BGR556 Value
#define MXC_V_CLCD_CTRL_MODE565_RGB565 ((uint32_t)0x1UL) |
CTRL_MODE565_RGB565 Value
#define MXC_V_CLCD_CTRL_PWR_ENABLE_HI ((uint32_t)0x1UL) |
CTRL_PWR_ENABLE_HI Value
#define MXC_V_CLCD_CTRL_PWR_ENABLE_LO ((uint32_t)0x0UL) |
CTRL_PWR_ENABLE_LO Value
#define MXC_V_CLCD_CTRL_VCI_SEL_ON_VBP ((uint32_t)0x1UL) |
CTRL_VCI_SEL_ON_VBP Value
#define MXC_V_CLCD_CTRL_VCI_SEL_ON_VDEN ((uint32_t)0x2UL) |
CTRL_VCI_SEL_ON_VDEN Value
#define MXC_V_CLCD_CTRL_VCI_SEL_ON_VFP ((uint32_t)0x3UL) |
CTRL_VCI_SEL_ON_VFP Value
#define MXC_V_CLCD_CTRL_VCI_SEL_ON_VSYNC ((uint32_t)0x0UL) |
CTRL_VCI_SEL_ON_VSYNC Value