Register Offsets

Macros
#define	MXC_R_CLCD_CLK_CTRL   ((uint32_t)0x00000000UL)
#define	MXC_R_CLCD_VTIM_0   ((uint32_t)0x00000004UL)
#define	MXC_R_CLCD_VTIM_1   ((uint32_t)0x00000008UL)
#define	MXC_R_CLCD_HTIM   ((uint32_t)0x0000000CUL)
#define	MXC_R_CLCD_CTRL   ((uint32_t)0x00000010UL)
#define	MXC_R_CLCD_FRBUF   ((uint32_t)0x00000018UL)
#define	MXC_R_CLCD_INT_EN   ((uint32_t)0x00000020UL)
#define	MXC_R_CLCD_INT_STAT   ((uint32_t)0x00000024UL)
#define	MXC_R_CLCD_PALETTE_RAM   ((uint32_t)0x00000400UL)

Detailed Description

CLCD Peripheral Register Offsets from the CLCD Base Peripheral Address.

Macro Definition Documentation

MXC_R_CLCD_CLK_CTRL

#define MXC_R_CLCD_CLK_CTRL   ((uint32_t)0x00000000UL)

Offset from CLCD Base Address: 0x0000

MXC_R_CLCD_CTRL

#define MXC_R_CLCD_CTRL   ((uint32_t)0x00000010UL)

Offset from CLCD Base Address: 0x0010

MXC_R_CLCD_FRBUF

#define MXC_R_CLCD_FRBUF   ((uint32_t)0x00000018UL)

Offset from CLCD Base Address: 0x0018

MXC_R_CLCD_HTIM

#define MXC_R_CLCD_HTIM   ((uint32_t)0x0000000CUL)

Offset from CLCD Base Address: 0x000C

MXC_R_CLCD_INT_EN

#define MXC_R_CLCD_INT_EN   ((uint32_t)0x00000020UL)

Offset from CLCD Base Address: 0x0020

MXC_R_CLCD_INT_STAT

#define MXC_R_CLCD_INT_STAT   ((uint32_t)0x00000024UL)

Offset from CLCD Base Address: 0x0024

MXC_R_CLCD_PALETTE_RAM

#define MXC_R_CLCD_PALETTE_RAM   ((uint32_t)0x00000400UL)

Offset from CLCD Base Address: 0x0400

MXC_R_CLCD_VTIM_0

#define MXC_R_CLCD_VTIM_0   ((uint32_t)0x00000004UL)

Offset from CLCD Base Address: 0x0004

MXC_R_CLCD_VTIM_1

#define MXC_R_CLCD_VTIM_1   ((uint32_t)0x00000008UL)

Offset from CLCD Base Address: 0x0008