Macros
#define	MXC_F_DMA_INTR_CH0_IPEND_POS 0

#define	MXC_F_DMA_INTR_CH0_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH0_IPEND_POS))

#define	MXC_V_DMA_INTR_CH0_IPEND_INACTIVE ((uint32_t)0x0UL)

#define	MXC_S_DMA_INTR_CH0_IPEND_INACTIVE (MXC_V_DMA_INTR_CH0_IPEND_INACTIVE << MXC_F_DMA_INTR_CH0_IPEND_POS)

#define	MXC_V_DMA_INTR_CH0_IPEND_PENDING ((uint32_t)0x1UL)

#define	MXC_S_DMA_INTR_CH0_IPEND_PENDING (MXC_V_DMA_INTR_CH0_IPEND_PENDING << MXC_F_DMA_INTR_CH0_IPEND_POS)

#define	MXC_F_DMA_INTR_CH1_IPEND_POS 1

#define	MXC_F_DMA_INTR_CH1_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH1_IPEND_POS))

#define	MXC_V_DMA_INTR_CH1_IPEND_INACTIVE ((uint32_t)0x0UL)

#define	MXC_S_DMA_INTR_CH1_IPEND_INACTIVE (MXC_V_DMA_INTR_CH1_IPEND_INACTIVE << MXC_F_DMA_INTR_CH1_IPEND_POS)

#define	MXC_V_DMA_INTR_CH1_IPEND_PENDING ((uint32_t)0x1UL)

#define	MXC_S_DMA_INTR_CH1_IPEND_PENDING (MXC_V_DMA_INTR_CH1_IPEND_PENDING << MXC_F_DMA_INTR_CH1_IPEND_POS)

#define	MXC_F_DMA_INTR_CH2_IPEND_POS 2

#define	MXC_F_DMA_INTR_CH2_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH2_IPEND_POS))

#define	MXC_V_DMA_INTR_CH2_IPEND_INACTIVE ((uint32_t)0x0UL)

#define	MXC_S_DMA_INTR_CH2_IPEND_INACTIVE (MXC_V_DMA_INTR_CH2_IPEND_INACTIVE << MXC_F_DMA_INTR_CH2_IPEND_POS)

#define	MXC_V_DMA_INTR_CH2_IPEND_PENDING ((uint32_t)0x1UL)

#define	MXC_S_DMA_INTR_CH2_IPEND_PENDING (MXC_V_DMA_INTR_CH2_IPEND_PENDING << MXC_F_DMA_INTR_CH2_IPEND_POS)

#define	MXC_F_DMA_INTR_CH3_IPEND_POS 3

#define	MXC_F_DMA_INTR_CH3_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH3_IPEND_POS))

#define	MXC_V_DMA_INTR_CH3_IPEND_INACTIVE ((uint32_t)0x0UL)

#define	MXC_S_DMA_INTR_CH3_IPEND_INACTIVE (MXC_V_DMA_INTR_CH3_IPEND_INACTIVE << MXC_F_DMA_INTR_CH3_IPEND_POS)

#define	MXC_V_DMA_INTR_CH3_IPEND_PENDING ((uint32_t)0x1UL)

#define	MXC_S_DMA_INTR_CH3_IPEND_PENDING (MXC_V_DMA_INTR_CH3_IPEND_PENDING << MXC_F_DMA_INTR_CH3_IPEND_POS)

#define	MXC_F_DMA_INTR_CH4_IPEND_POS 4

#define	MXC_F_DMA_INTR_CH4_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH4_IPEND_POS))

#define	MXC_V_DMA_INTR_CH4_IPEND_INACTIVE ((uint32_t)0x0UL)

#define	MXC_S_DMA_INTR_CH4_IPEND_INACTIVE (MXC_V_DMA_INTR_CH4_IPEND_INACTIVE << MXC_F_DMA_INTR_CH4_IPEND_POS)

#define	MXC_V_DMA_INTR_CH4_IPEND_PENDING ((uint32_t)0x1UL)

#define	MXC_S_DMA_INTR_CH4_IPEND_PENDING (MXC_V_DMA_INTR_CH4_IPEND_PENDING << MXC_F_DMA_INTR_CH4_IPEND_POS)

#define	MXC_F_DMA_INTR_CH5_IPEND_POS 5

#define	MXC_F_DMA_INTR_CH5_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH5_IPEND_POS))

#define	MXC_V_DMA_INTR_CH5_IPEND_INACTIVE ((uint32_t)0x0UL)

#define	MXC_S_DMA_INTR_CH5_IPEND_INACTIVE (MXC_V_DMA_INTR_CH5_IPEND_INACTIVE << MXC_F_DMA_INTR_CH5_IPEND_POS)

#define	MXC_V_DMA_INTR_CH5_IPEND_PENDING ((uint32_t)0x1UL)

#define	MXC_S_DMA_INTR_CH5_IPEND_PENDING (MXC_V_DMA_INTR_CH5_IPEND_PENDING << MXC_F_DMA_INTR_CH5_IPEND_POS)

#define	MXC_F_DMA_INTR_CH6_IPEND_POS 6

#define	MXC_F_DMA_INTR_CH6_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH6_IPEND_POS))

#define	MXC_V_DMA_INTR_CH6_IPEND_INACTIVE ((uint32_t)0x0UL)

#define	MXC_S_DMA_INTR_CH6_IPEND_INACTIVE (MXC_V_DMA_INTR_CH6_IPEND_INACTIVE << MXC_F_DMA_INTR_CH6_IPEND_POS)

#define	MXC_V_DMA_INTR_CH6_IPEND_PENDING ((uint32_t)0x1UL)

#define	MXC_S_DMA_INTR_CH6_IPEND_PENDING (MXC_V_DMA_INTR_CH6_IPEND_PENDING << MXC_F_DMA_INTR_CH6_IPEND_POS)

#define	MXC_F_DMA_INTR_CH7_IPEND_POS 7

#define	MXC_F_DMA_INTR_CH7_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH7_IPEND_POS))

#define	MXC_V_DMA_INTR_CH7_IPEND_INACTIVE ((uint32_t)0x0UL)

#define	MXC_S_DMA_INTR_CH7_IPEND_INACTIVE (MXC_V_DMA_INTR_CH7_IPEND_INACTIVE << MXC_F_DMA_INTR_CH7_IPEND_POS)

#define	MXC_V_DMA_INTR_CH7_IPEND_PENDING ((uint32_t)0x1UL)

#define	MXC_S_DMA_INTR_CH7_IPEND_PENDING (MXC_V_DMA_INTR_CH7_IPEND_PENDING << MXC_F_DMA_INTR_CH7_IPEND_POS)

#define	MXC_F_DMA_INTR_CH8_IPEND_POS 8

#define	MXC_F_DMA_INTR_CH8_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH8_IPEND_POS))

#define	MXC_V_DMA_INTR_CH8_IPEND_INACTIVE ((uint32_t)0x0UL)

#define	MXC_S_DMA_INTR_CH8_IPEND_INACTIVE (MXC_V_DMA_INTR_CH8_IPEND_INACTIVE << MXC_F_DMA_INTR_CH8_IPEND_POS)

#define	MXC_V_DMA_INTR_CH8_IPEND_PENDING ((uint32_t)0x1UL)

#define	MXC_S_DMA_INTR_CH8_IPEND_PENDING (MXC_V_DMA_INTR_CH8_IPEND_PENDING << MXC_F_DMA_INTR_CH8_IPEND_POS)

#define	MXC_F_DMA_INTR_CH9_IPEND_POS 9

#define	MXC_F_DMA_INTR_CH9_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH9_IPEND_POS))

#define	MXC_V_DMA_INTR_CH9_IPEND_INACTIVE ((uint32_t)0x0UL)

#define	MXC_S_DMA_INTR_CH9_IPEND_INACTIVE (MXC_V_DMA_INTR_CH9_IPEND_INACTIVE << MXC_F_DMA_INTR_CH9_IPEND_POS)

#define	MXC_V_DMA_INTR_CH9_IPEND_PENDING ((uint32_t)0x1UL)

#define	MXC_S_DMA_INTR_CH9_IPEND_PENDING (MXC_V_DMA_INTR_CH9_IPEND_PENDING << MXC_F_DMA_INTR_CH9_IPEND_POS)

#define	MXC_F_DMA_INTR_CH10_IPEND_POS 10

#define	MXC_F_DMA_INTR_CH10_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH10_IPEND_POS))

#define	MXC_V_DMA_INTR_CH10_IPEND_INACTIVE ((uint32_t)0x0UL)

#define	MXC_S_DMA_INTR_CH10_IPEND_INACTIVE (MXC_V_DMA_INTR_CH10_IPEND_INACTIVE << MXC_F_DMA_INTR_CH10_IPEND_POS)

#define	MXC_V_DMA_INTR_CH10_IPEND_PENDING ((uint32_t)0x1UL)

#define	MXC_S_DMA_INTR_CH10_IPEND_PENDING (MXC_V_DMA_INTR_CH10_IPEND_PENDING << MXC_F_DMA_INTR_CH10_IPEND_POS)

#define	MXC_F_DMA_INTR_CH11_IPEND_POS 11

#define	MXC_F_DMA_INTR_CH11_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH11_IPEND_POS))

#define	MXC_V_DMA_INTR_CH11_IPEND_INACTIVE ((uint32_t)0x0UL)

#define	MXC_S_DMA_INTR_CH11_IPEND_INACTIVE (MXC_V_DMA_INTR_CH11_IPEND_INACTIVE << MXC_F_DMA_INTR_CH11_IPEND_POS)

#define	MXC_V_DMA_INTR_CH11_IPEND_PENDING ((uint32_t)0x1UL)

#define	MXC_S_DMA_INTR_CH11_IPEND_PENDING (MXC_V_DMA_INTR_CH11_IPEND_PENDING << MXC_F_DMA_INTR_CH11_IPEND_POS)

#define	MXC_F_DMA_INTR_CH12_IPEND_POS 12

#define	MXC_F_DMA_INTR_CH12_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH12_IPEND_POS))

#define	MXC_V_DMA_INTR_CH12_IPEND_INACTIVE ((uint32_t)0x0UL)

#define	MXC_S_DMA_INTR_CH12_IPEND_INACTIVE (MXC_V_DMA_INTR_CH12_IPEND_INACTIVE << MXC_F_DMA_INTR_CH12_IPEND_POS)

#define	MXC_V_DMA_INTR_CH12_IPEND_PENDING ((uint32_t)0x1UL)

#define	MXC_S_DMA_INTR_CH12_IPEND_PENDING (MXC_V_DMA_INTR_CH12_IPEND_PENDING << MXC_F_DMA_INTR_CH12_IPEND_POS)

#define	MXC_F_DMA_INTR_CH13_IPEND_POS 13

#define	MXC_F_DMA_INTR_CH13_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH13_IPEND_POS))

#define	MXC_V_DMA_INTR_CH13_IPEND_INACTIVE ((uint32_t)0x0UL)

#define	MXC_S_DMA_INTR_CH13_IPEND_INACTIVE (MXC_V_DMA_INTR_CH13_IPEND_INACTIVE << MXC_F_DMA_INTR_CH13_IPEND_POS)

#define	MXC_V_DMA_INTR_CH13_IPEND_PENDING ((uint32_t)0x1UL)

#define	MXC_S_DMA_INTR_CH13_IPEND_PENDING (MXC_V_DMA_INTR_CH13_IPEND_PENDING << MXC_F_DMA_INTR_CH13_IPEND_POS)

#define	MXC_F_DMA_INTR_CH14_IPEND_POS 14

#define	MXC_F_DMA_INTR_CH14_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH14_IPEND_POS))

#define	MXC_V_DMA_INTR_CH14_IPEND_INACTIVE ((uint32_t)0x0UL)

#define	MXC_S_DMA_INTR_CH14_IPEND_INACTIVE (MXC_V_DMA_INTR_CH14_IPEND_INACTIVE << MXC_F_DMA_INTR_CH14_IPEND_POS)

#define	MXC_V_DMA_INTR_CH14_IPEND_PENDING ((uint32_t)0x1UL)

#define	MXC_S_DMA_INTR_CH14_IPEND_PENDING (MXC_V_DMA_INTR_CH14_IPEND_PENDING << MXC_F_DMA_INTR_CH14_IPEND_POS)

#define	MXC_F_DMA_INTR_CH15_IPEND_POS 15

#define	MXC_F_DMA_INTR_CH15_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH15_IPEND_POS))

#define	MXC_V_DMA_INTR_CH15_IPEND_INACTIVE ((uint32_t)0x0UL)

#define	MXC_S_DMA_INTR_CH15_IPEND_INACTIVE (MXC_V_DMA_INTR_CH15_IPEND_INACTIVE << MXC_F_DMA_INTR_CH15_IPEND_POS)

#define	MXC_V_DMA_INTR_CH15_IPEND_PENDING ((uint32_t)0x1UL)

#define	MXC_S_DMA_INTR_CH15_IPEND_PENDING (MXC_V_DMA_INTR_CH15_IPEND_PENDING << MXC_F_DMA_INTR_CH15_IPEND_POS)

Detailed Description

DMA Interrupt Register.

Macro Definition Documentation

◆ MXC_F_DMA_INTR_CH0_IPEND

#define MXC_F_DMA_INTR_CH0_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH0_IPEND_POS))

INTR_CH0_IPEND Mask

◆ MXC_F_DMA_INTR_CH0_IPEND_POS

#define MXC_F_DMA_INTR_CH0_IPEND_POS 0

INTR_CH0_IPEND Position

◆ MXC_F_DMA_INTR_CH10_IPEND

#define MXC_F_DMA_INTR_CH10_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH10_IPEND_POS))

INTR_CH10_IPEND Mask

◆ MXC_F_DMA_INTR_CH10_IPEND_POS

#define MXC_F_DMA_INTR_CH10_IPEND_POS 10

INTR_CH10_IPEND Position

◆ MXC_F_DMA_INTR_CH11_IPEND

#define MXC_F_DMA_INTR_CH11_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH11_IPEND_POS))

INTR_CH11_IPEND Mask

◆ MXC_F_DMA_INTR_CH11_IPEND_POS

#define MXC_F_DMA_INTR_CH11_IPEND_POS 11

INTR_CH11_IPEND Position

◆ MXC_F_DMA_INTR_CH12_IPEND

#define MXC_F_DMA_INTR_CH12_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH12_IPEND_POS))

INTR_CH12_IPEND Mask

◆ MXC_F_DMA_INTR_CH12_IPEND_POS

#define MXC_F_DMA_INTR_CH12_IPEND_POS 12

INTR_CH12_IPEND Position

◆ MXC_F_DMA_INTR_CH13_IPEND

#define MXC_F_DMA_INTR_CH13_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH13_IPEND_POS))

INTR_CH13_IPEND Mask

◆ MXC_F_DMA_INTR_CH13_IPEND_POS

#define MXC_F_DMA_INTR_CH13_IPEND_POS 13

INTR_CH13_IPEND Position

◆ MXC_F_DMA_INTR_CH14_IPEND

#define MXC_F_DMA_INTR_CH14_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH14_IPEND_POS))

INTR_CH14_IPEND Mask

◆ MXC_F_DMA_INTR_CH14_IPEND_POS

#define MXC_F_DMA_INTR_CH14_IPEND_POS 14

INTR_CH14_IPEND Position

◆ MXC_F_DMA_INTR_CH15_IPEND

#define MXC_F_DMA_INTR_CH15_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH15_IPEND_POS))

INTR_CH15_IPEND Mask

◆ MXC_F_DMA_INTR_CH15_IPEND_POS

#define MXC_F_DMA_INTR_CH15_IPEND_POS 15

INTR_CH15_IPEND Position

◆ MXC_F_DMA_INTR_CH1_IPEND

#define MXC_F_DMA_INTR_CH1_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH1_IPEND_POS))

INTR_CH1_IPEND Mask

◆ MXC_F_DMA_INTR_CH1_IPEND_POS

#define MXC_F_DMA_INTR_CH1_IPEND_POS 1

INTR_CH1_IPEND Position

◆ MXC_F_DMA_INTR_CH2_IPEND

#define MXC_F_DMA_INTR_CH2_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH2_IPEND_POS))

INTR_CH2_IPEND Mask

◆ MXC_F_DMA_INTR_CH2_IPEND_POS

#define MXC_F_DMA_INTR_CH2_IPEND_POS 2

INTR_CH2_IPEND Position

◆ MXC_F_DMA_INTR_CH3_IPEND

#define MXC_F_DMA_INTR_CH3_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH3_IPEND_POS))

INTR_CH3_IPEND Mask

◆ MXC_F_DMA_INTR_CH3_IPEND_POS

#define MXC_F_DMA_INTR_CH3_IPEND_POS 3

INTR_CH3_IPEND Position

◆ MXC_F_DMA_INTR_CH4_IPEND

#define MXC_F_DMA_INTR_CH4_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH4_IPEND_POS))

INTR_CH4_IPEND Mask

◆ MXC_F_DMA_INTR_CH4_IPEND_POS

#define MXC_F_DMA_INTR_CH4_IPEND_POS 4

INTR_CH4_IPEND Position

◆ MXC_F_DMA_INTR_CH5_IPEND

#define MXC_F_DMA_INTR_CH5_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH5_IPEND_POS))

INTR_CH5_IPEND Mask

◆ MXC_F_DMA_INTR_CH5_IPEND_POS

#define MXC_F_DMA_INTR_CH5_IPEND_POS 5

INTR_CH5_IPEND Position

◆ MXC_F_DMA_INTR_CH6_IPEND

#define MXC_F_DMA_INTR_CH6_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH6_IPEND_POS))

INTR_CH6_IPEND Mask

◆ MXC_F_DMA_INTR_CH6_IPEND_POS

#define MXC_F_DMA_INTR_CH6_IPEND_POS 6

INTR_CH6_IPEND Position

◆ MXC_F_DMA_INTR_CH7_IPEND

#define MXC_F_DMA_INTR_CH7_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH7_IPEND_POS))

INTR_CH7_IPEND Mask

◆ MXC_F_DMA_INTR_CH7_IPEND_POS

#define MXC_F_DMA_INTR_CH7_IPEND_POS 7

INTR_CH7_IPEND Position

◆ MXC_F_DMA_INTR_CH8_IPEND

#define MXC_F_DMA_INTR_CH8_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH8_IPEND_POS))

INTR_CH8_IPEND Mask

◆ MXC_F_DMA_INTR_CH8_IPEND_POS

#define MXC_F_DMA_INTR_CH8_IPEND_POS 8

INTR_CH8_IPEND Position

◆ MXC_F_DMA_INTR_CH9_IPEND

#define MXC_F_DMA_INTR_CH9_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH9_IPEND_POS))

INTR_CH9_IPEND Mask

◆ MXC_F_DMA_INTR_CH9_IPEND_POS

#define MXC_F_DMA_INTR_CH9_IPEND_POS 9

INTR_CH9_IPEND Position

◆ MXC_S_DMA_INTR_CH0_IPEND_INACTIVE

#define MXC_S_DMA_INTR_CH0_IPEND_INACTIVE (MXC_V_DMA_INTR_CH0_IPEND_INACTIVE << MXC_F_DMA_INTR_CH0_IPEND_POS)

INTR_CH0_IPEND_INACTIVE Setting

◆ MXC_S_DMA_INTR_CH0_IPEND_PENDING

#define MXC_S_DMA_INTR_CH0_IPEND_PENDING (MXC_V_DMA_INTR_CH0_IPEND_PENDING << MXC_F_DMA_INTR_CH0_IPEND_POS)

INTR_CH0_IPEND_PENDING Setting

◆ MXC_S_DMA_INTR_CH10_IPEND_INACTIVE

#define MXC_S_DMA_INTR_CH10_IPEND_INACTIVE (MXC_V_DMA_INTR_CH10_IPEND_INACTIVE << MXC_F_DMA_INTR_CH10_IPEND_POS)

INTR_CH10_IPEND_INACTIVE Setting

◆ MXC_S_DMA_INTR_CH10_IPEND_PENDING

#define MXC_S_DMA_INTR_CH10_IPEND_PENDING (MXC_V_DMA_INTR_CH10_IPEND_PENDING << MXC_F_DMA_INTR_CH10_IPEND_POS)

INTR_CH10_IPEND_PENDING Setting

◆ MXC_S_DMA_INTR_CH11_IPEND_INACTIVE

#define MXC_S_DMA_INTR_CH11_IPEND_INACTIVE (MXC_V_DMA_INTR_CH11_IPEND_INACTIVE << MXC_F_DMA_INTR_CH11_IPEND_POS)

INTR_CH11_IPEND_INACTIVE Setting

◆ MXC_S_DMA_INTR_CH11_IPEND_PENDING

#define MXC_S_DMA_INTR_CH11_IPEND_PENDING (MXC_V_DMA_INTR_CH11_IPEND_PENDING << MXC_F_DMA_INTR_CH11_IPEND_POS)

INTR_CH11_IPEND_PENDING Setting

◆ MXC_S_DMA_INTR_CH12_IPEND_INACTIVE

#define MXC_S_DMA_INTR_CH12_IPEND_INACTIVE (MXC_V_DMA_INTR_CH12_IPEND_INACTIVE << MXC_F_DMA_INTR_CH12_IPEND_POS)

INTR_CH12_IPEND_INACTIVE Setting

◆ MXC_S_DMA_INTR_CH12_IPEND_PENDING

#define MXC_S_DMA_INTR_CH12_IPEND_PENDING (MXC_V_DMA_INTR_CH12_IPEND_PENDING << MXC_F_DMA_INTR_CH12_IPEND_POS)

INTR_CH12_IPEND_PENDING Setting

◆ MXC_S_DMA_INTR_CH13_IPEND_INACTIVE

#define MXC_S_DMA_INTR_CH13_IPEND_INACTIVE (MXC_V_DMA_INTR_CH13_IPEND_INACTIVE << MXC_F_DMA_INTR_CH13_IPEND_POS)

INTR_CH13_IPEND_INACTIVE Setting

◆ MXC_S_DMA_INTR_CH13_IPEND_PENDING

#define MXC_S_DMA_INTR_CH13_IPEND_PENDING (MXC_V_DMA_INTR_CH13_IPEND_PENDING << MXC_F_DMA_INTR_CH13_IPEND_POS)

INTR_CH13_IPEND_PENDING Setting

◆ MXC_S_DMA_INTR_CH14_IPEND_INACTIVE

#define MXC_S_DMA_INTR_CH14_IPEND_INACTIVE (MXC_V_DMA_INTR_CH14_IPEND_INACTIVE << MXC_F_DMA_INTR_CH14_IPEND_POS)

INTR_CH14_IPEND_INACTIVE Setting

◆ MXC_S_DMA_INTR_CH14_IPEND_PENDING

#define MXC_S_DMA_INTR_CH14_IPEND_PENDING (MXC_V_DMA_INTR_CH14_IPEND_PENDING << MXC_F_DMA_INTR_CH14_IPEND_POS)

INTR_CH14_IPEND_PENDING Setting

◆ MXC_S_DMA_INTR_CH15_IPEND_INACTIVE

#define MXC_S_DMA_INTR_CH15_IPEND_INACTIVE (MXC_V_DMA_INTR_CH15_IPEND_INACTIVE << MXC_F_DMA_INTR_CH15_IPEND_POS)

INTR_CH15_IPEND_INACTIVE Setting

◆ MXC_S_DMA_INTR_CH15_IPEND_PENDING

#define MXC_S_DMA_INTR_CH15_IPEND_PENDING (MXC_V_DMA_INTR_CH15_IPEND_PENDING << MXC_F_DMA_INTR_CH15_IPEND_POS)

INTR_CH15_IPEND_PENDING Setting

◆ MXC_S_DMA_INTR_CH1_IPEND_INACTIVE

#define MXC_S_DMA_INTR_CH1_IPEND_INACTIVE (MXC_V_DMA_INTR_CH1_IPEND_INACTIVE << MXC_F_DMA_INTR_CH1_IPEND_POS)

INTR_CH1_IPEND_INACTIVE Setting

◆ MXC_S_DMA_INTR_CH1_IPEND_PENDING

#define MXC_S_DMA_INTR_CH1_IPEND_PENDING (MXC_V_DMA_INTR_CH1_IPEND_PENDING << MXC_F_DMA_INTR_CH1_IPEND_POS)

INTR_CH1_IPEND_PENDING Setting

◆ MXC_S_DMA_INTR_CH2_IPEND_INACTIVE

#define MXC_S_DMA_INTR_CH2_IPEND_INACTIVE (MXC_V_DMA_INTR_CH2_IPEND_INACTIVE << MXC_F_DMA_INTR_CH2_IPEND_POS)

INTR_CH2_IPEND_INACTIVE Setting

◆ MXC_S_DMA_INTR_CH2_IPEND_PENDING

#define MXC_S_DMA_INTR_CH2_IPEND_PENDING (MXC_V_DMA_INTR_CH2_IPEND_PENDING << MXC_F_DMA_INTR_CH2_IPEND_POS)

INTR_CH2_IPEND_PENDING Setting

◆ MXC_S_DMA_INTR_CH3_IPEND_INACTIVE

#define MXC_S_DMA_INTR_CH3_IPEND_INACTIVE (MXC_V_DMA_INTR_CH3_IPEND_INACTIVE << MXC_F_DMA_INTR_CH3_IPEND_POS)

INTR_CH3_IPEND_INACTIVE Setting

◆ MXC_S_DMA_INTR_CH3_IPEND_PENDING

#define MXC_S_DMA_INTR_CH3_IPEND_PENDING (MXC_V_DMA_INTR_CH3_IPEND_PENDING << MXC_F_DMA_INTR_CH3_IPEND_POS)

INTR_CH3_IPEND_PENDING Setting

◆ MXC_S_DMA_INTR_CH4_IPEND_INACTIVE

#define MXC_S_DMA_INTR_CH4_IPEND_INACTIVE (MXC_V_DMA_INTR_CH4_IPEND_INACTIVE << MXC_F_DMA_INTR_CH4_IPEND_POS)

INTR_CH4_IPEND_INACTIVE Setting

◆ MXC_S_DMA_INTR_CH4_IPEND_PENDING

#define MXC_S_DMA_INTR_CH4_IPEND_PENDING (MXC_V_DMA_INTR_CH4_IPEND_PENDING << MXC_F_DMA_INTR_CH4_IPEND_POS)

INTR_CH4_IPEND_PENDING Setting

◆ MXC_S_DMA_INTR_CH5_IPEND_INACTIVE

#define MXC_S_DMA_INTR_CH5_IPEND_INACTIVE (MXC_V_DMA_INTR_CH5_IPEND_INACTIVE << MXC_F_DMA_INTR_CH5_IPEND_POS)

INTR_CH5_IPEND_INACTIVE Setting

◆ MXC_S_DMA_INTR_CH5_IPEND_PENDING

#define MXC_S_DMA_INTR_CH5_IPEND_PENDING (MXC_V_DMA_INTR_CH5_IPEND_PENDING << MXC_F_DMA_INTR_CH5_IPEND_POS)

INTR_CH5_IPEND_PENDING Setting

◆ MXC_S_DMA_INTR_CH6_IPEND_INACTIVE

#define MXC_S_DMA_INTR_CH6_IPEND_INACTIVE (MXC_V_DMA_INTR_CH6_IPEND_INACTIVE << MXC_F_DMA_INTR_CH6_IPEND_POS)

INTR_CH6_IPEND_INACTIVE Setting

◆ MXC_S_DMA_INTR_CH6_IPEND_PENDING

#define MXC_S_DMA_INTR_CH6_IPEND_PENDING (MXC_V_DMA_INTR_CH6_IPEND_PENDING << MXC_F_DMA_INTR_CH6_IPEND_POS)

INTR_CH6_IPEND_PENDING Setting

◆ MXC_S_DMA_INTR_CH7_IPEND_INACTIVE

#define MXC_S_DMA_INTR_CH7_IPEND_INACTIVE (MXC_V_DMA_INTR_CH7_IPEND_INACTIVE << MXC_F_DMA_INTR_CH7_IPEND_POS)

INTR_CH7_IPEND_INACTIVE Setting

◆ MXC_S_DMA_INTR_CH7_IPEND_PENDING

#define MXC_S_DMA_INTR_CH7_IPEND_PENDING (MXC_V_DMA_INTR_CH7_IPEND_PENDING << MXC_F_DMA_INTR_CH7_IPEND_POS)

INTR_CH7_IPEND_PENDING Setting

◆ MXC_S_DMA_INTR_CH8_IPEND_INACTIVE

#define MXC_S_DMA_INTR_CH8_IPEND_INACTIVE (MXC_V_DMA_INTR_CH8_IPEND_INACTIVE << MXC_F_DMA_INTR_CH8_IPEND_POS)

INTR_CH8_IPEND_INACTIVE Setting

◆ MXC_S_DMA_INTR_CH8_IPEND_PENDING

#define MXC_S_DMA_INTR_CH8_IPEND_PENDING (MXC_V_DMA_INTR_CH8_IPEND_PENDING << MXC_F_DMA_INTR_CH8_IPEND_POS)

INTR_CH8_IPEND_PENDING Setting

◆ MXC_S_DMA_INTR_CH9_IPEND_INACTIVE

#define MXC_S_DMA_INTR_CH9_IPEND_INACTIVE (MXC_V_DMA_INTR_CH9_IPEND_INACTIVE << MXC_F_DMA_INTR_CH9_IPEND_POS)

INTR_CH9_IPEND_INACTIVE Setting

◆ MXC_S_DMA_INTR_CH9_IPEND_PENDING

#define MXC_S_DMA_INTR_CH9_IPEND_PENDING (MXC_V_DMA_INTR_CH9_IPEND_PENDING << MXC_F_DMA_INTR_CH9_IPEND_POS)

INTR_CH9_IPEND_PENDING Setting

◆ MXC_V_DMA_INTR_CH0_IPEND_INACTIVE

#define MXC_V_DMA_INTR_CH0_IPEND_INACTIVE ((uint32_t)0x0UL)

INTR_CH0_IPEND_INACTIVE Value

◆ MXC_V_DMA_INTR_CH0_IPEND_PENDING

#define MXC_V_DMA_INTR_CH0_IPEND_PENDING ((uint32_t)0x1UL)

INTR_CH0_IPEND_PENDING Value

◆ MXC_V_DMA_INTR_CH10_IPEND_INACTIVE

#define MXC_V_DMA_INTR_CH10_IPEND_INACTIVE ((uint32_t)0x0UL)

INTR_CH10_IPEND_INACTIVE Value

◆ MXC_V_DMA_INTR_CH10_IPEND_PENDING

#define MXC_V_DMA_INTR_CH10_IPEND_PENDING ((uint32_t)0x1UL)

INTR_CH10_IPEND_PENDING Value

◆ MXC_V_DMA_INTR_CH11_IPEND_INACTIVE

#define MXC_V_DMA_INTR_CH11_IPEND_INACTIVE ((uint32_t)0x0UL)

INTR_CH11_IPEND_INACTIVE Value

◆ MXC_V_DMA_INTR_CH11_IPEND_PENDING

#define MXC_V_DMA_INTR_CH11_IPEND_PENDING ((uint32_t)0x1UL)

INTR_CH11_IPEND_PENDING Value

◆ MXC_V_DMA_INTR_CH12_IPEND_INACTIVE

#define MXC_V_DMA_INTR_CH12_IPEND_INACTIVE ((uint32_t)0x0UL)

INTR_CH12_IPEND_INACTIVE Value

◆ MXC_V_DMA_INTR_CH12_IPEND_PENDING

#define MXC_V_DMA_INTR_CH12_IPEND_PENDING ((uint32_t)0x1UL)

INTR_CH12_IPEND_PENDING Value

◆ MXC_V_DMA_INTR_CH13_IPEND_INACTIVE

#define MXC_V_DMA_INTR_CH13_IPEND_INACTIVE ((uint32_t)0x0UL)

INTR_CH13_IPEND_INACTIVE Value

◆ MXC_V_DMA_INTR_CH13_IPEND_PENDING

#define MXC_V_DMA_INTR_CH13_IPEND_PENDING ((uint32_t)0x1UL)

INTR_CH13_IPEND_PENDING Value

◆ MXC_V_DMA_INTR_CH14_IPEND_INACTIVE

#define MXC_V_DMA_INTR_CH14_IPEND_INACTIVE ((uint32_t)0x0UL)

INTR_CH14_IPEND_INACTIVE Value

◆ MXC_V_DMA_INTR_CH14_IPEND_PENDING

#define MXC_V_DMA_INTR_CH14_IPEND_PENDING ((uint32_t)0x1UL)

INTR_CH14_IPEND_PENDING Value

◆ MXC_V_DMA_INTR_CH15_IPEND_INACTIVE

#define MXC_V_DMA_INTR_CH15_IPEND_INACTIVE ((uint32_t)0x0UL)

INTR_CH15_IPEND_INACTIVE Value

◆ MXC_V_DMA_INTR_CH15_IPEND_PENDING

#define MXC_V_DMA_INTR_CH15_IPEND_PENDING ((uint32_t)0x1UL)

INTR_CH15_IPEND_PENDING Value

◆ MXC_V_DMA_INTR_CH1_IPEND_INACTIVE

#define MXC_V_DMA_INTR_CH1_IPEND_INACTIVE ((uint32_t)0x0UL)

INTR_CH1_IPEND_INACTIVE Value

◆ MXC_V_DMA_INTR_CH1_IPEND_PENDING

#define MXC_V_DMA_INTR_CH1_IPEND_PENDING ((uint32_t)0x1UL)

INTR_CH1_IPEND_PENDING Value

◆ MXC_V_DMA_INTR_CH2_IPEND_INACTIVE

#define MXC_V_DMA_INTR_CH2_IPEND_INACTIVE ((uint32_t)0x0UL)

INTR_CH2_IPEND_INACTIVE Value

◆ MXC_V_DMA_INTR_CH2_IPEND_PENDING

#define MXC_V_DMA_INTR_CH2_IPEND_PENDING ((uint32_t)0x1UL)

INTR_CH2_IPEND_PENDING Value

◆ MXC_V_DMA_INTR_CH3_IPEND_INACTIVE

#define MXC_V_DMA_INTR_CH3_IPEND_INACTIVE ((uint32_t)0x0UL)

INTR_CH3_IPEND_INACTIVE Value

◆ MXC_V_DMA_INTR_CH3_IPEND_PENDING

#define MXC_V_DMA_INTR_CH3_IPEND_PENDING ((uint32_t)0x1UL)

INTR_CH3_IPEND_PENDING Value

◆ MXC_V_DMA_INTR_CH4_IPEND_INACTIVE

#define MXC_V_DMA_INTR_CH4_IPEND_INACTIVE ((uint32_t)0x0UL)

INTR_CH4_IPEND_INACTIVE Value

◆ MXC_V_DMA_INTR_CH4_IPEND_PENDING

#define MXC_V_DMA_INTR_CH4_IPEND_PENDING ((uint32_t)0x1UL)

INTR_CH4_IPEND_PENDING Value

◆ MXC_V_DMA_INTR_CH5_IPEND_INACTIVE

#define MXC_V_DMA_INTR_CH5_IPEND_INACTIVE ((uint32_t)0x0UL)

INTR_CH5_IPEND_INACTIVE Value

◆ MXC_V_DMA_INTR_CH5_IPEND_PENDING

#define MXC_V_DMA_INTR_CH5_IPEND_PENDING ((uint32_t)0x1UL)

INTR_CH5_IPEND_PENDING Value

◆ MXC_V_DMA_INTR_CH6_IPEND_INACTIVE

#define MXC_V_DMA_INTR_CH6_IPEND_INACTIVE ((uint32_t)0x0UL)

INTR_CH6_IPEND_INACTIVE Value

◆ MXC_V_DMA_INTR_CH6_IPEND_PENDING

#define MXC_V_DMA_INTR_CH6_IPEND_PENDING ((uint32_t)0x1UL)

INTR_CH6_IPEND_PENDING Value

◆ MXC_V_DMA_INTR_CH7_IPEND_INACTIVE

#define MXC_V_DMA_INTR_CH7_IPEND_INACTIVE ((uint32_t)0x0UL)

INTR_CH7_IPEND_INACTIVE Value

◆ MXC_V_DMA_INTR_CH7_IPEND_PENDING

#define MXC_V_DMA_INTR_CH7_IPEND_PENDING ((uint32_t)0x1UL)

INTR_CH7_IPEND_PENDING Value

◆ MXC_V_DMA_INTR_CH8_IPEND_INACTIVE

#define MXC_V_DMA_INTR_CH8_IPEND_INACTIVE ((uint32_t)0x0UL)

INTR_CH8_IPEND_INACTIVE Value

◆ MXC_V_DMA_INTR_CH8_IPEND_PENDING

#define MXC_V_DMA_INTR_CH8_IPEND_PENDING ((uint32_t)0x1UL)

INTR_CH8_IPEND_PENDING Value

◆ MXC_V_DMA_INTR_CH9_IPEND_INACTIVE

#define MXC_V_DMA_INTR_CH9_IPEND_INACTIVE ((uint32_t)0x0UL)

INTR_CH9_IPEND_INACTIVE Value

◆ MXC_V_DMA_INTR_CH9_IPEND_PENDING

#define MXC_V_DMA_INTR_CH9_IPEND_PENDING ((uint32_t)0x1UL)

INTR_CH9_IPEND_PENDING Value

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