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MAX32650 Peripheral Driver API
Peripheral Driver API for the MAX32650
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HPB Memory Configuration Register.
#define MXC_F_HPB_MCR_CRT ((uint32_t)(0x1UL << MXC_F_HPB_MCR_CRT_POS)) |
MCR_CRT Mask
#define MXC_F_HPB_MCR_CRT_POS 5 |
MCR_CRT Position
#define MXC_F_HPB_MCR_DEV_TYPE ((uint32_t)(0x3UL << MXC_F_HPB_MCR_DEV_TYPE_POS)) |
MCR_DEV_TYPE Mask
#define MXC_F_HPB_MCR_DEV_TYPE_POS 3 |
MCR_DEV_TYPE Position
#define MXC_F_HPB_MCR_HSE ((uint32_t)(0x1UL << MXC_F_HPB_MCR_HSE_POS)) |
MCR_HSE Mask
#define MXC_F_HPB_MCR_HSE_POS 7 |
MCR_HSE Position
#define MXC_F_HPB_MCR_MAXLEN ((uint32_t)(0x1FFUL << MXC_F_HPB_MCR_MAXLEN_POS)) |
MCR_MAXLEN Mask
#define MXC_F_HPB_MCR_MAXLEN_EN ((uint32_t)(0x1UL << MXC_F_HPB_MCR_MAXLEN_EN_POS)) |
MCR_MAXLEN_EN Mask
#define MXC_F_HPB_MCR_MAXLEN_EN_POS 31 |
MCR_MAXLEN_EN Position
#define MXC_F_HPB_MCR_MAXLEN_POS 18 |
MCR_MAXLEN Position
#define MXC_F_HPB_MCR_READ_LATENCY ((uint32_t)(0x1UL << MXC_F_HPB_MCR_READ_LATENCY_POS)) |
MCR_READ_LATENCY Mask
#define MXC_F_HPB_MCR_READ_LATENCY_POS 6 |
MCR_READ_LATENCY Position
#define MXC_S_HPB_MCR_CRT_CONFIG_REG_SPACE (MXC_V_HPB_MCR_CRT_CONFIG_REG_SPACE << MXC_F_HPB_MCR_CRT_POS) |
MCR_CRT_CONFIG_REG_SPACE Setting
#define MXC_S_HPB_MCR_CRT_MEM_SPACE (MXC_V_HPB_MCR_CRT_MEM_SPACE << MXC_F_HPB_MCR_CRT_POS) |
MCR_CRT_MEM_SPACE Setting
#define MXC_S_HPB_MCR_DEV_TYPE_HYPERFLASH (MXC_V_HPB_MCR_DEV_TYPE_HYPERFLASH << MXC_F_HPB_MCR_DEV_TYPE_POS) |
MCR_DEV_TYPE_HYPERFLASH Setting
#define MXC_S_HPB_MCR_DEV_TYPE_HYPERRAM (MXC_V_HPB_MCR_DEV_TYPE_HYPERRAM << MXC_F_HPB_MCR_DEV_TYPE_POS) |
MCR_DEV_TYPE_HYPERRAM Setting
#define MXC_S_HPB_MCR_DEV_TYPE_XCCELAPSRAM (MXC_V_HPB_MCR_DEV_TYPE_XCCELAPSRAM << MXC_F_HPB_MCR_DEV_TYPE_POS) |
MCR_DEV_TYPE_XCCELAPSRAM Setting
#define MXC_S_HPB_MCR_HSE_DIS (MXC_V_HPB_MCR_HSE_DIS << MXC_F_HPB_MCR_HSE_POS) |
MCR_HSE_DIS Setting
#define MXC_S_HPB_MCR_HSE_EN (MXC_V_HPB_MCR_HSE_EN << MXC_F_HPB_MCR_HSE_POS) |
MCR_HSE_EN Setting
#define MXC_S_HPB_MCR_MAXLEN_EN_DIS (MXC_V_HPB_MCR_MAXLEN_EN_DIS << MXC_F_HPB_MCR_MAXLEN_EN_POS) |
MCR_MAXLEN_EN_DIS Setting
#define MXC_S_HPB_MCR_MAXLEN_EN_EN (MXC_V_HPB_MCR_MAXLEN_EN_EN << MXC_F_HPB_MCR_MAXLEN_EN_POS) |
MCR_MAXLEN_EN_EN Setting
#define MXC_S_HPB_MCR_READ_LATENCY_FIXED (MXC_V_HPB_MCR_READ_LATENCY_FIXED << MXC_F_HPB_MCR_READ_LATENCY_POS) |
MCR_READ_LATENCY_FIXED Setting
#define MXC_S_HPB_MCR_READ_LATENCY_VARIABLE (MXC_V_HPB_MCR_READ_LATENCY_VARIABLE << MXC_F_HPB_MCR_READ_LATENCY_POS) |
MCR_READ_LATENCY_VARIABLE Setting
#define MXC_V_HPB_MCR_CRT_CONFIG_REG_SPACE ((uint32_t)0x1UL) |
MCR_CRT_CONFIG_REG_SPACE Value
#define MXC_V_HPB_MCR_CRT_MEM_SPACE ((uint32_t)0x0UL) |
MCR_CRT_MEM_SPACE Value
#define MXC_V_HPB_MCR_DEV_TYPE_HYPERFLASH ((uint32_t)0x0UL) |
MCR_DEV_TYPE_HYPERFLASH Value
#define MXC_V_HPB_MCR_DEV_TYPE_HYPERRAM ((uint32_t)0x2UL) |
MCR_DEV_TYPE_HYPERRAM Value
#define MXC_V_HPB_MCR_DEV_TYPE_XCCELAPSRAM ((uint32_t)0x1UL) |
MCR_DEV_TYPE_XCCELAPSRAM Value
#define MXC_V_HPB_MCR_HSE_DIS ((uint32_t)0x0UL) |
MCR_HSE_DIS Value
#define MXC_V_HPB_MCR_HSE_EN ((uint32_t)0x1UL) |
MCR_HSE_EN Value
#define MXC_V_HPB_MCR_MAXLEN_EN_DIS ((uint32_t)0x0UL) |
MCR_MAXLEN_EN_DIS Value
#define MXC_V_HPB_MCR_MAXLEN_EN_EN ((uint32_t)0x1UL) |
MCR_MAXLEN_EN_EN Value
#define MXC_V_HPB_MCR_READ_LATENCY_FIXED ((uint32_t)0x1UL) |
MCR_READ_LATENCY_FIXED Value
#define MXC_V_HPB_MCR_READ_LATENCY_VARIABLE ((uint32_t)0x0UL) |
MCR_READ_LATENCY_VARIABLE Value