I2C_RX_CTRL0

Macros
#define	MXC_F_I2C_RX_CTRL0_DNR_POS   0
#define	MXC_F_I2C_RX_CTRL0_DNR   ((uint32_t)(0x1UL << MXC_F_I2C_RX_CTRL0_DNR_POS))
#define	MXC_V_I2C_RX_CTRL0_DNR_RESPOND   ((uint32_t)0x0UL)
#define	MXC_S_I2C_RX_CTRL0_DNR_RESPOND   (MXC_V_I2C_RX_CTRL0_DNR_RESPOND << MXC_F_I2C_RX_CTRL0_DNR_POS)
#define	MXC_V_I2C_RX_CTRL0_DNR_DONT_RESPOND   ((uint32_t)0x1UL)
#define	MXC_S_I2C_RX_CTRL0_DNR_DONT_RESPOND   (MXC_V_I2C_RX_CTRL0_DNR_DONT_RESPOND << MXC_F_I2C_RX_CTRL0_DNR_POS)
#define	MXC_F_I2C_RX_CTRL0_RXFSH_POS   7
#define	MXC_F_I2C_RX_CTRL0_RXFSH   ((uint32_t)(0x1UL << MXC_F_I2C_RX_CTRL0_RXFSH_POS))
#define	MXC_V_I2C_RX_CTRL0_RXFSH_NOT_FLUSHED   ((uint32_t)0x0UL)
#define	MXC_S_I2C_RX_CTRL0_RXFSH_NOT_FLUSHED   (MXC_V_I2C_RX_CTRL0_RXFSH_NOT_FLUSHED << MXC_F_I2C_RX_CTRL0_RXFSH_POS)
#define	MXC_V_I2C_RX_CTRL0_RXFSH_FLUSH   ((uint32_t)0x1UL)
#define	MXC_S_I2C_RX_CTRL0_RXFSH_FLUSH   (MXC_V_I2C_RX_CTRL0_RXFSH_FLUSH << MXC_F_I2C_RX_CTRL0_RXFSH_POS)
#define	MXC_F_I2C_RX_CTRL0_RXTH_POS   8
#define	MXC_F_I2C_RX_CTRL0_RXTH   ((uint32_t)(0xFUL << MXC_F_I2C_RX_CTRL0_RXTH_POS))

Detailed Description

Receive Control Register 0.

Macro Definition Documentation

MXC_F_I2C_RX_CTRL0_DNR

#define MXC_F_I2C_RX_CTRL0_DNR   ((uint32_t)(0x1UL << MXC_F_I2C_RX_CTRL0_DNR_POS))

RX_CTRL0_DNR Mask

MXC_F_I2C_RX_CTRL0_DNR_POS

#define MXC_F_I2C_RX_CTRL0_DNR_POS   0

RX_CTRL0_DNR Position

MXC_F_I2C_RX_CTRL0_RXFSH

#define MXC_F_I2C_RX_CTRL0_RXFSH   ((uint32_t)(0x1UL << MXC_F_I2C_RX_CTRL0_RXFSH_POS))

RX_CTRL0_RXFSH Mask

MXC_F_I2C_RX_CTRL0_RXFSH_POS

#define MXC_F_I2C_RX_CTRL0_RXFSH_POS   7

RX_CTRL0_RXFSH Position

MXC_F_I2C_RX_CTRL0_RXTH

#define MXC_F_I2C_RX_CTRL0_RXTH   ((uint32_t)(0xFUL << MXC_F_I2C_RX_CTRL0_RXTH_POS))

RX_CTRL0_RXTH Mask

MXC_F_I2C_RX_CTRL0_RXTH_POS

#define MXC_F_I2C_RX_CTRL0_RXTH_POS   8

RX_CTRL0_RXTH Position

MXC_S_I2C_RX_CTRL0_DNR_DONT_RESPOND

#define MXC_S_I2C_RX_CTRL0_DNR_DONT_RESPOND   (MXC_V_I2C_RX_CTRL0_DNR_DONT_RESPOND << MXC_F_I2C_RX_CTRL0_DNR_POS)

RX_CTRL0_DNR_DONT_RESPOND Setting

MXC_S_I2C_RX_CTRL0_DNR_RESPOND

#define MXC_S_I2C_RX_CTRL0_DNR_RESPOND   (MXC_V_I2C_RX_CTRL0_DNR_RESPOND << MXC_F_I2C_RX_CTRL0_DNR_POS)

RX_CTRL0_DNR_RESPOND Setting

MXC_S_I2C_RX_CTRL0_RXFSH_FLUSH

#define MXC_S_I2C_RX_CTRL0_RXFSH_FLUSH   (MXC_V_I2C_RX_CTRL0_RXFSH_FLUSH << MXC_F_I2C_RX_CTRL0_RXFSH_POS)

RX_CTRL0_RXFSH_FLUSH Setting

MXC_S_I2C_RX_CTRL0_RXFSH_NOT_FLUSHED

#define MXC_S_I2C_RX_CTRL0_RXFSH_NOT_FLUSHED   (MXC_V_I2C_RX_CTRL0_RXFSH_NOT_FLUSHED << MXC_F_I2C_RX_CTRL0_RXFSH_POS)

RX_CTRL0_RXFSH_NOT_FLUSHED Setting

MXC_V_I2C_RX_CTRL0_DNR_DONT_RESPOND

#define MXC_V_I2C_RX_CTRL0_DNR_DONT_RESPOND   ((uint32_t)0x1UL)

RX_CTRL0_DNR_DONT_RESPOND Value

MXC_V_I2C_RX_CTRL0_DNR_RESPOND

#define MXC_V_I2C_RX_CTRL0_DNR_RESPOND   ((uint32_t)0x0UL)

RX_CTRL0_DNR_RESPOND Value

MXC_V_I2C_RX_CTRL0_RXFSH_FLUSH

#define MXC_V_I2C_RX_CTRL0_RXFSH_FLUSH   ((uint32_t)0x1UL)

RX_CTRL0_RXFSH_FLUSH Value

MXC_V_I2C_RX_CTRL0_RXFSH_NOT_FLUSHED

#define MXC_V_I2C_RX_CTRL0_RXFSH_NOT_FLUSHED   ((uint32_t)0x0UL)

RX_CTRL0_RXFSH_NOT_FLUSHED Value