Macros
#define	MXC_F_NBBFC_REG0_RDSGCSEL_POS 0

#define	MXC_F_NBBFC_REG0_RDSGCSEL ((uint32_t)(0x3FUL << MXC_F_NBBFC_REG0_RDSGCSEL_POS))

#define	MXC_F_NBBFC_REG0_RDSGCSET_POS 6

#define	MXC_F_NBBFC_REG0_RDSGCSET ((uint32_t)(0x1UL << MXC_F_NBBFC_REG0_RDSGCSET_POS))

#define	MXC_V_NBBFC_REG0_RDSGCSET_INTERNAL ((uint32_t)0x0UL)

#define	MXC_S_NBBFC_REG0_RDSGCSET_INTERNAL (MXC_V_NBBFC_REG0_RDSGCSET_INTERNAL << MXC_F_NBBFC_REG0_RDSGCSET_POS)

#define	MXC_V_NBBFC_REG0_RDSGCSET_GRAY_CODE ((uint32_t)0x1UL)

#define	MXC_S_NBBFC_REG0_RDSGCSET_GRAY_CODE (MXC_V_NBBFC_REG0_RDSGCSET_GRAY_CODE << MXC_F_NBBFC_REG0_RDSGCSET_POS)

#define	MXC_F_NBBFC_REG0_HYPCGDLY_POS 8

#define	MXC_F_NBBFC_REG0_HYPCGDLY ((uint32_t)(0x3FUL << MXC_F_NBBFC_REG0_HYPCGDLY_POS))

#define	MXC_F_NBBFC_REG0_USBRCKSEL_POS 16

#define	MXC_F_NBBFC_REG0_USBRCKSEL ((uint32_t)(0x1UL << MXC_F_NBBFC_REG0_USBRCKSEL_POS))

#define	MXC_V_NBBFC_REG0_USBRCKSEL_SYS ((uint32_t)0x0UL)

#define	MXC_S_NBBFC_REG0_USBRCKSEL_SYS (MXC_V_NBBFC_REG0_USBRCKSEL_SYS << MXC_F_NBBFC_REG0_USBRCKSEL_POS)

#define	MXC_V_NBBFC_REG0_USBRCKSEL_DIG ((uint32_t)0x1UL)

#define	MXC_S_NBBFC_REG0_USBRCKSEL_DIG (MXC_V_NBBFC_REG0_USBRCKSEL_DIG << MXC_F_NBBFC_REG0_USBRCKSEL_POS)

#define	MXC_F_NBBFC_REG0_QSPI0SEL_POS 17

#define	MXC_F_NBBFC_REG0_QSPI0SEL ((uint32_t)(0x1UL << MXC_F_NBBFC_REG0_QSPI0SEL_POS))

#define	MXC_V_NBBFC_REG0_QSPI0SEL_MED ((uint32_t)0x0UL)

#define	MXC_S_NBBFC_REG0_QSPI0SEL_MED (MXC_V_NBBFC_REG0_QSPI0SEL_MED << MXC_F_NBBFC_REG0_QSPI0SEL_POS)

#define	MXC_V_NBBFC_REG0_QSPI0SEL_QSPI0 ((uint32_t)0x1UL)

#define	MXC_S_NBBFC_REG0_QSPI0SEL_QSPI0 (MXC_V_NBBFC_REG0_QSPI0SEL_QSPI0 << MXC_F_NBBFC_REG0_QSPI0SEL_POS)

#define	MXC_F_NBBFC_REG0_I2C0DGEN0_POS 20

#define	MXC_F_NBBFC_REG0_I2C0DGEN0 ((uint32_t)(0x1UL << MXC_F_NBBFC_REG0_I2C0DGEN0_POS))

#define	MXC_V_NBBFC_REG0_I2C0DGEN0_DIS ((uint32_t)0x0UL)

#define	MXC_S_NBBFC_REG0_I2C0DGEN0_DIS (MXC_V_NBBFC_REG0_I2C0DGEN0_DIS << MXC_F_NBBFC_REG0_I2C0DGEN0_POS)

#define	MXC_V_NBBFC_REG0_I2C0DGEN0_EN ((uint32_t)0x1UL)

#define	MXC_S_NBBFC_REG0_I2C0DGEN0_EN (MXC_V_NBBFC_REG0_I2C0DGEN0_EN << MXC_F_NBBFC_REG0_I2C0DGEN0_POS)

#define	MXC_F_NBBFC_REG0_I2C0DGEN1_POS 21

#define	MXC_F_NBBFC_REG0_I2C0DGEN1 ((uint32_t)(0x1UL << MXC_F_NBBFC_REG0_I2C0DGEN1_POS))

#define	MXC_V_NBBFC_REG0_I2C0DGEN1_DIS ((uint32_t)0x0UL)

#define	MXC_S_NBBFC_REG0_I2C0DGEN1_DIS (MXC_V_NBBFC_REG0_I2C0DGEN1_DIS << MXC_F_NBBFC_REG0_I2C0DGEN1_POS)

#define	MXC_V_NBBFC_REG0_I2C0DGEN1_EN ((uint32_t)0x1UL)

#define	MXC_S_NBBFC_REG0_I2C0DGEN1_EN (MXC_V_NBBFC_REG0_I2C0DGEN1_EN << MXC_F_NBBFC_REG0_I2C0DGEN1_POS)

#define	MXC_F_NBBFC_REG0_I2C1DGEN0_POS 22

#define	MXC_F_NBBFC_REG0_I2C1DGEN0 ((uint32_t)(0x1UL << MXC_F_NBBFC_REG0_I2C1DGEN0_POS))

#define	MXC_V_NBBFC_REG0_I2C1DGEN0_DIS ((uint32_t)0x0UL)

#define	MXC_S_NBBFC_REG0_I2C1DGEN0_DIS (MXC_V_NBBFC_REG0_I2C1DGEN0_DIS << MXC_F_NBBFC_REG0_I2C1DGEN0_POS)

#define	MXC_V_NBBFC_REG0_I2C1DGEN0_EN ((uint32_t)0x1UL)

#define	MXC_S_NBBFC_REG0_I2C1DGEN0_EN (MXC_V_NBBFC_REG0_I2C1DGEN0_EN << MXC_F_NBBFC_REG0_I2C1DGEN0_POS)

#define	MXC_F_NBBFC_REG0_I2C1DGEN1_POS 23

#define	MXC_F_NBBFC_REG0_I2C1DGEN1 ((uint32_t)(0x1UL << MXC_F_NBBFC_REG0_I2C1DGEN1_POS))

#define	MXC_V_NBBFC_REG0_I2C1DGEN1_DIS ((uint32_t)0x0UL)

#define	MXC_S_NBBFC_REG0_I2C1DGEN1_DIS (MXC_V_NBBFC_REG0_I2C1DGEN1_DIS << MXC_F_NBBFC_REG0_I2C1DGEN1_POS)

#define	MXC_V_NBBFC_REG0_I2C1DGEN1_EN ((uint32_t)0x1UL)

#define	MXC_S_NBBFC_REG0_I2C1DGEN1_EN (MXC_V_NBBFC_REG0_I2C1DGEN1_EN << MXC_F_NBBFC_REG0_I2C1DGEN1_POS)

Detailed Description

Register 0.

Macro Definition Documentation

◆ MXC_F_NBBFC_REG0_HYPCGDLY

#define MXC_F_NBBFC_REG0_HYPCGDLY ((uint32_t)(0x3FUL << MXC_F_NBBFC_REG0_HYPCGDLY_POS))

REG0_HYPCGDLY Mask

◆ MXC_F_NBBFC_REG0_HYPCGDLY_POS

#define MXC_F_NBBFC_REG0_HYPCGDLY_POS 8

REG0_HYPCGDLY Position

◆ MXC_F_NBBFC_REG0_I2C0DGEN0

#define MXC_F_NBBFC_REG0_I2C0DGEN0 ((uint32_t)(0x1UL << MXC_F_NBBFC_REG0_I2C0DGEN0_POS))

REG0_I2C0DGEN0 Mask

◆ MXC_F_NBBFC_REG0_I2C0DGEN0_POS

#define MXC_F_NBBFC_REG0_I2C0DGEN0_POS 20

REG0_I2C0DGEN0 Position

◆ MXC_F_NBBFC_REG0_I2C0DGEN1

#define MXC_F_NBBFC_REG0_I2C0DGEN1 ((uint32_t)(0x1UL << MXC_F_NBBFC_REG0_I2C0DGEN1_POS))

REG0_I2C0DGEN1 Mask

◆ MXC_F_NBBFC_REG0_I2C0DGEN1_POS

#define MXC_F_NBBFC_REG0_I2C0DGEN1_POS 21

REG0_I2C0DGEN1 Position

◆ MXC_F_NBBFC_REG0_I2C1DGEN0

#define MXC_F_NBBFC_REG0_I2C1DGEN0 ((uint32_t)(0x1UL << MXC_F_NBBFC_REG0_I2C1DGEN0_POS))

REG0_I2C1DGEN0 Mask

◆ MXC_F_NBBFC_REG0_I2C1DGEN0_POS

#define MXC_F_NBBFC_REG0_I2C1DGEN0_POS 22

REG0_I2C1DGEN0 Position

◆ MXC_F_NBBFC_REG0_I2C1DGEN1

#define MXC_F_NBBFC_REG0_I2C1DGEN1 ((uint32_t)(0x1UL << MXC_F_NBBFC_REG0_I2C1DGEN1_POS))

REG0_I2C1DGEN1 Mask

◆ MXC_F_NBBFC_REG0_I2C1DGEN1_POS

#define MXC_F_NBBFC_REG0_I2C1DGEN1_POS 23

REG0_I2C1DGEN1 Position

◆ MXC_F_NBBFC_REG0_QSPI0SEL

#define MXC_F_NBBFC_REG0_QSPI0SEL ((uint32_t)(0x1UL << MXC_F_NBBFC_REG0_QSPI0SEL_POS))

REG0_QSPI0SEL Mask

◆ MXC_F_NBBFC_REG0_QSPI0SEL_POS

#define MXC_F_NBBFC_REG0_QSPI0SEL_POS 17

REG0_QSPI0SEL Position

◆ MXC_F_NBBFC_REG0_RDSGCSEL

#define MXC_F_NBBFC_REG0_RDSGCSEL ((uint32_t)(0x3FUL << MXC_F_NBBFC_REG0_RDSGCSEL_POS))

REG0_RDSGCSEL Mask

◆ MXC_F_NBBFC_REG0_RDSGCSEL_POS

#define MXC_F_NBBFC_REG0_RDSGCSEL_POS 0

REG0_RDSGCSEL Position

◆ MXC_F_NBBFC_REG0_RDSGCSET

#define MXC_F_NBBFC_REG0_RDSGCSET ((uint32_t)(0x1UL << MXC_F_NBBFC_REG0_RDSGCSET_POS))

REG0_RDSGCSET Mask

◆ MXC_F_NBBFC_REG0_RDSGCSET_POS

#define MXC_F_NBBFC_REG0_RDSGCSET_POS 6

REG0_RDSGCSET Position

◆ MXC_F_NBBFC_REG0_USBRCKSEL

#define MXC_F_NBBFC_REG0_USBRCKSEL ((uint32_t)(0x1UL << MXC_F_NBBFC_REG0_USBRCKSEL_POS))

REG0_USBRCKSEL Mask

◆ MXC_F_NBBFC_REG0_USBRCKSEL_POS

#define MXC_F_NBBFC_REG0_USBRCKSEL_POS 16

REG0_USBRCKSEL Position

◆ MXC_S_NBBFC_REG0_I2C0DGEN0_DIS

#define MXC_S_NBBFC_REG0_I2C0DGEN0_DIS (MXC_V_NBBFC_REG0_I2C0DGEN0_DIS << MXC_F_NBBFC_REG0_I2C0DGEN0_POS)

REG0_I2C0DGEN0_DIS Setting

◆ MXC_S_NBBFC_REG0_I2C0DGEN0_EN

#define MXC_S_NBBFC_REG0_I2C0DGEN0_EN (MXC_V_NBBFC_REG0_I2C0DGEN0_EN << MXC_F_NBBFC_REG0_I2C0DGEN0_POS)

REG0_I2C0DGEN0_EN Setting

◆ MXC_S_NBBFC_REG0_I2C0DGEN1_DIS

#define MXC_S_NBBFC_REG0_I2C0DGEN1_DIS (MXC_V_NBBFC_REG0_I2C0DGEN1_DIS << MXC_F_NBBFC_REG0_I2C0DGEN1_POS)

REG0_I2C0DGEN1_DIS Setting

◆ MXC_S_NBBFC_REG0_I2C0DGEN1_EN

#define MXC_S_NBBFC_REG0_I2C0DGEN1_EN (MXC_V_NBBFC_REG0_I2C0DGEN1_EN << MXC_F_NBBFC_REG0_I2C0DGEN1_POS)

REG0_I2C0DGEN1_EN Setting

◆ MXC_S_NBBFC_REG0_I2C1DGEN0_DIS

#define MXC_S_NBBFC_REG0_I2C1DGEN0_DIS (MXC_V_NBBFC_REG0_I2C1DGEN0_DIS << MXC_F_NBBFC_REG0_I2C1DGEN0_POS)

REG0_I2C1DGEN0_DIS Setting

◆ MXC_S_NBBFC_REG0_I2C1DGEN0_EN

#define MXC_S_NBBFC_REG0_I2C1DGEN0_EN (MXC_V_NBBFC_REG0_I2C1DGEN0_EN << MXC_F_NBBFC_REG0_I2C1DGEN0_POS)

REG0_I2C1DGEN0_EN Setting

◆ MXC_S_NBBFC_REG0_I2C1DGEN1_DIS

#define MXC_S_NBBFC_REG0_I2C1DGEN1_DIS (MXC_V_NBBFC_REG0_I2C1DGEN1_DIS << MXC_F_NBBFC_REG0_I2C1DGEN1_POS)

REG0_I2C1DGEN1_DIS Setting

◆ MXC_S_NBBFC_REG0_I2C1DGEN1_EN

#define MXC_S_NBBFC_REG0_I2C1DGEN1_EN (MXC_V_NBBFC_REG0_I2C1DGEN1_EN << MXC_F_NBBFC_REG0_I2C1DGEN1_POS)

REG0_I2C1DGEN1_EN Setting

◆ MXC_S_NBBFC_REG0_QSPI0SEL_MED

#define MXC_S_NBBFC_REG0_QSPI0SEL_MED (MXC_V_NBBFC_REG0_QSPI0SEL_MED << MXC_F_NBBFC_REG0_QSPI0SEL_POS)

REG0_QSPI0SEL_MED Setting

◆ MXC_S_NBBFC_REG0_QSPI0SEL_QSPI0

#define MXC_S_NBBFC_REG0_QSPI0SEL_QSPI0 (MXC_V_NBBFC_REG0_QSPI0SEL_QSPI0 << MXC_F_NBBFC_REG0_QSPI0SEL_POS)

REG0_QSPI0SEL_QSPI0 Setting

◆ MXC_S_NBBFC_REG0_RDSGCSET_GRAY_CODE

#define MXC_S_NBBFC_REG0_RDSGCSET_GRAY_CODE (MXC_V_NBBFC_REG0_RDSGCSET_GRAY_CODE << MXC_F_NBBFC_REG0_RDSGCSET_POS)

REG0_RDSGCSET_GRAY_CODE Setting

◆ MXC_S_NBBFC_REG0_RDSGCSET_INTERNAL

#define MXC_S_NBBFC_REG0_RDSGCSET_INTERNAL (MXC_V_NBBFC_REG0_RDSGCSET_INTERNAL << MXC_F_NBBFC_REG0_RDSGCSET_POS)

REG0_RDSGCSET_INTERNAL Setting

◆ MXC_S_NBBFC_REG0_USBRCKSEL_DIG

#define MXC_S_NBBFC_REG0_USBRCKSEL_DIG (MXC_V_NBBFC_REG0_USBRCKSEL_DIG << MXC_F_NBBFC_REG0_USBRCKSEL_POS)

REG0_USBRCKSEL_DIG Setting

◆ MXC_S_NBBFC_REG0_USBRCKSEL_SYS

#define MXC_S_NBBFC_REG0_USBRCKSEL_SYS (MXC_V_NBBFC_REG0_USBRCKSEL_SYS << MXC_F_NBBFC_REG0_USBRCKSEL_POS)

REG0_USBRCKSEL_SYS Setting

◆ MXC_V_NBBFC_REG0_I2C0DGEN0_DIS

#define MXC_V_NBBFC_REG0_I2C0DGEN0_DIS ((uint32_t)0x0UL)

REG0_I2C0DGEN0_DIS Value

◆ MXC_V_NBBFC_REG0_I2C0DGEN0_EN

#define MXC_V_NBBFC_REG0_I2C0DGEN0_EN ((uint32_t)0x1UL)

REG0_I2C0DGEN0_EN Value

◆ MXC_V_NBBFC_REG0_I2C0DGEN1_DIS

#define MXC_V_NBBFC_REG0_I2C0DGEN1_DIS ((uint32_t)0x0UL)

REG0_I2C0DGEN1_DIS Value

◆ MXC_V_NBBFC_REG0_I2C0DGEN1_EN

#define MXC_V_NBBFC_REG0_I2C0DGEN1_EN ((uint32_t)0x1UL)

REG0_I2C0DGEN1_EN Value

◆ MXC_V_NBBFC_REG0_I2C1DGEN0_DIS

#define MXC_V_NBBFC_REG0_I2C1DGEN0_DIS ((uint32_t)0x0UL)

REG0_I2C1DGEN0_DIS Value

◆ MXC_V_NBBFC_REG0_I2C1DGEN0_EN

#define MXC_V_NBBFC_REG0_I2C1DGEN0_EN ((uint32_t)0x1UL)

REG0_I2C1DGEN0_EN Value

◆ MXC_V_NBBFC_REG0_I2C1DGEN1_DIS

#define MXC_V_NBBFC_REG0_I2C1DGEN1_DIS ((uint32_t)0x0UL)

REG0_I2C1DGEN1_DIS Value

◆ MXC_V_NBBFC_REG0_I2C1DGEN1_EN

#define MXC_V_NBBFC_REG0_I2C1DGEN1_EN ((uint32_t)0x1UL)

REG0_I2C1DGEN1_EN Value

◆ MXC_V_NBBFC_REG0_QSPI0SEL_MED

#define MXC_V_NBBFC_REG0_QSPI0SEL_MED ((uint32_t)0x0UL)

REG0_QSPI0SEL_MED Value

◆ MXC_V_NBBFC_REG0_QSPI0SEL_QSPI0

#define MXC_V_NBBFC_REG0_QSPI0SEL_QSPI0 ((uint32_t)0x1UL)

REG0_QSPI0SEL_QSPI0 Value

◆ MXC_V_NBBFC_REG0_RDSGCSET_GRAY_CODE

#define MXC_V_NBBFC_REG0_RDSGCSET_GRAY_CODE ((uint32_t)0x1UL)

REG0_RDSGCSET_GRAY_CODE Value

◆ MXC_V_NBBFC_REG0_RDSGCSET_INTERNAL

#define MXC_V_NBBFC_REG0_RDSGCSET_INTERNAL ((uint32_t)0x0UL)

REG0_RDSGCSET_INTERNAL Value

◆ MXC_V_NBBFC_REG0_USBRCKSEL_DIG

#define MXC_V_NBBFC_REG0_USBRCKSEL_DIG ((uint32_t)0x1UL)

REG0_USBRCKSEL_DIG Value

◆ MXC_V_NBBFC_REG0_USBRCKSEL_SYS

#define MXC_V_NBBFC_REG0_USBRCKSEL_SYS ((uint32_t)0x0UL)

REG0_USBRCKSEL_SYS Value

Macros