MAX32650 Peripheral Driver API
Peripheral Driver API for the MAX32650
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Register Offsets

Macros

#define MXC_R_PWRSEQ_CTRL   ((uint32_t)0x00000000UL)
 
#define MXC_R_PWRSEQ_GPIO0_WK_FL   ((uint32_t)0x00000004UL)
 
#define MXC_R_PWRSEQ_GPIO0_WK_EN   ((uint32_t)0x00000008UL)
 
#define MXC_R_PWRSEQ_GPIO1_WK_FL   ((uint32_t)0x0000000CUL)
 
#define MXC_R_PWRSEQ_GPIO1_WK_EN   ((uint32_t)0x00000010UL)
 
#define MXC_R_PWRSEQ_GPIO2_WK_FL   ((uint32_t)0x00000014UL)
 
#define MXC_R_PWRSEQ_GPIO2_WK_EN   ((uint32_t)0x00000018UL)
 
#define MXC_R_PWRSEQ_GPIO3_WK_FL   ((uint32_t)0x0000001CUL)
 
#define MXC_R_PWRSEQ_GPIO3_WK_EN   ((uint32_t)0x00000020UL)
 
#define MXC_R_PWRSEQ_USB_WK_FL   ((uint32_t)0x00000030UL)
 
#define MXC_R_PWRSEQ_USB_WK_EN   ((uint32_t)0x00000034UL)
 
#define MXC_R_PWRSEQ_MEM_PWR   ((uint32_t)0x00000040UL)
 

Detailed Description

PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address.

Macro Definition Documentation

◆ MXC_R_PWRSEQ_CTRL

#define MXC_R_PWRSEQ_CTRL   ((uint32_t)0x00000000UL)

Offset from PWRSEQ Base Address: 0x0000

◆ MXC_R_PWRSEQ_GPIO0_WK_EN

#define MXC_R_PWRSEQ_GPIO0_WK_EN   ((uint32_t)0x00000008UL)

Offset from PWRSEQ Base Address: 0x0008

◆ MXC_R_PWRSEQ_GPIO0_WK_FL

#define MXC_R_PWRSEQ_GPIO0_WK_FL   ((uint32_t)0x00000004UL)

Offset from PWRSEQ Base Address: 0x0004

◆ MXC_R_PWRSEQ_GPIO1_WK_EN

#define MXC_R_PWRSEQ_GPIO1_WK_EN   ((uint32_t)0x00000010UL)

Offset from PWRSEQ Base Address: 0x0010

◆ MXC_R_PWRSEQ_GPIO1_WK_FL

#define MXC_R_PWRSEQ_GPIO1_WK_FL   ((uint32_t)0x0000000CUL)

Offset from PWRSEQ Base Address: 0x000C

◆ MXC_R_PWRSEQ_GPIO2_WK_EN

#define MXC_R_PWRSEQ_GPIO2_WK_EN   ((uint32_t)0x00000018UL)

Offset from PWRSEQ Base Address: 0x0018

◆ MXC_R_PWRSEQ_GPIO2_WK_FL

#define MXC_R_PWRSEQ_GPIO2_WK_FL   ((uint32_t)0x00000014UL)

Offset from PWRSEQ Base Address: 0x0014

◆ MXC_R_PWRSEQ_GPIO3_WK_EN

#define MXC_R_PWRSEQ_GPIO3_WK_EN   ((uint32_t)0x00000020UL)

Offset from PWRSEQ Base Address: 0x0020

◆ MXC_R_PWRSEQ_GPIO3_WK_FL

#define MXC_R_PWRSEQ_GPIO3_WK_FL   ((uint32_t)0x0000001CUL)

Offset from PWRSEQ Base Address: 0x001C

◆ MXC_R_PWRSEQ_MEM_PWR

#define MXC_R_PWRSEQ_MEM_PWR   ((uint32_t)0x00000040UL)

Offset from PWRSEQ Base Address: 0x0040

◆ MXC_R_PWRSEQ_USB_WK_EN

#define MXC_R_PWRSEQ_USB_WK_EN   ((uint32_t)0x00000034UL)

Offset from PWRSEQ Base Address: 0x0034

◆ MXC_R_PWRSEQ_USB_WK_FL

#define MXC_R_PWRSEQ_USB_WK_FL   ((uint32_t)0x00000030UL)

Offset from PWRSEQ Base Address: 0x0030