MAX32650 Peripheral Driver API
Peripheral Driver API for the MAX32650
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SDHC_CFG_0
Secure Digital High Capacity(SDHC) » SDHC_Registers

Macros

#define MXC_F_SDHC_CFG_0_TO_FREQ_POS   0
 
#define MXC_F_SDHC_CFG_0_TO_FREQ   ((uint32_t)(0x3FUL << MXC_F_SDHC_CFG_0_TO_FREQ_POS))
 
#define MXC_V_SDHC_CFG_0_TO_FREQ_1MHZ   ((uint32_t)0x1UL)
 
#define MXC_S_SDHC_CFG_0_TO_FREQ_1MHZ   (MXC_V_SDHC_CFG_0_TO_FREQ_1MHZ << MXC_F_SDHC_CFG_0_TO_FREQ_POS)
 
#define MXC_F_SDHC_CFG_0_CLK_UNIT_POS   7
 
#define MXC_F_SDHC_CFG_0_CLK_UNIT   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_CLK_UNIT_POS))
 
#define MXC_F_SDHC_CFG_0_CLK_FREQ_POS   8
 
#define MXC_F_SDHC_CFG_0_CLK_FREQ   ((uint32_t)(0xFFUL << MXC_F_SDHC_CFG_0_CLK_FREQ_POS))
 
#define MXC_F_SDHC_CFG_0_MAX_BLK_LEN_POS   16
 
#define MXC_F_SDHC_CFG_0_MAX_BLK_LEN   ((uint32_t)(0x3UL << MXC_F_SDHC_CFG_0_MAX_BLK_LEN_POS))
 
#define MXC_V_SDHC_CFG_0_MAX_BLK_LEN_2048_BYTES   ((uint32_t)0x2UL)
 
#define MXC_S_SDHC_CFG_0_MAX_BLK_LEN_2048_BYTES   (MXC_V_SDHC_CFG_0_MAX_BLK_LEN_2048_BYTES << MXC_F_SDHC_CFG_0_MAX_BLK_LEN_POS)
 
#define MXC_F_SDHC_CFG_0_8_BIT_POS   18
 
#define MXC_F_SDHC_CFG_0_8_BIT   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_8_BIT_POS))
 
#define MXC_F_SDHC_CFG_0_ADMA2_POS   19
 
#define MXC_F_SDHC_CFG_0_ADMA2   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_ADMA2_POS))
 
#define MXC_F_SDHC_CFG_0_HS_POS   21
 
#define MXC_F_SDHC_CFG_0_HS   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_HS_POS))
 
#define MXC_F_SDHC_CFG_0_SDMA_POS   22
 
#define MXC_F_SDHC_CFG_0_SDMA   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_SDMA_POS))
 
#define MXC_F_SDHC_CFG_0_SUSPEND_POS   23
 
#define MXC_F_SDHC_CFG_0_SUSPEND   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_SUSPEND_POS))
 
#define MXC_F_SDHC_CFG_0_3_3V_POS   24
 
#define MXC_F_SDHC_CFG_0_3_3V   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_3_3V_POS))
 
#define MXC_F_SDHC_CFG_0_3_0V_POS   25
 
#define MXC_F_SDHC_CFG_0_3_0V   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_3_0V_POS))
 
#define MXC_F_SDHC_CFG_0_1_8V_POS   26
 
#define MXC_F_SDHC_CFG_0_1_8V   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_1_8V_POS))
 
#define MXC_F_SDHC_CFG_0_64_BIT_SYS_BUS_POS   28
 
#define MXC_F_SDHC_CFG_0_64_BIT_SYS_BUS   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_64_BIT_SYS_BUS_POS))
 
#define MXC_F_SDHC_CFG_0_ASYNC_INT_POS   29
 
#define MXC_F_SDHC_CFG_0_ASYNC_INT   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_ASYNC_INT_POS))
 
#define MXC_F_SDHC_CFG_0_SLOT_TYPE_POS   30
 
#define MXC_F_SDHC_CFG_0_SLOT_TYPE   ((uint32_t)(0x3UL << MXC_F_SDHC_CFG_0_SLOT_TYPE_POS))
 

Detailed Description

Capabilities 0-31.

Macro Definition Documentation

◆ MXC_F_SDHC_CFG_0_1_8V

#define MXC_F_SDHC_CFG_0_1_8V   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_1_8V_POS))

CFG_0_1_8V Mask

◆ MXC_F_SDHC_CFG_0_1_8V_POS

#define MXC_F_SDHC_CFG_0_1_8V_POS   26

CFG_0_1_8V Position

◆ MXC_F_SDHC_CFG_0_3_0V

#define MXC_F_SDHC_CFG_0_3_0V   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_3_0V_POS))

CFG_0_3_0V Mask

◆ MXC_F_SDHC_CFG_0_3_0V_POS

#define MXC_F_SDHC_CFG_0_3_0V_POS   25

CFG_0_3_0V Position

◆ MXC_F_SDHC_CFG_0_3_3V

#define MXC_F_SDHC_CFG_0_3_3V   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_3_3V_POS))

CFG_0_3_3V Mask

◆ MXC_F_SDHC_CFG_0_3_3V_POS

#define MXC_F_SDHC_CFG_0_3_3V_POS   24

CFG_0_3_3V Position

◆ MXC_F_SDHC_CFG_0_64_BIT_SYS_BUS

#define MXC_F_SDHC_CFG_0_64_BIT_SYS_BUS   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_64_BIT_SYS_BUS_POS))

CFG_0_64_BIT_SYS_BUS Mask

◆ MXC_F_SDHC_CFG_0_64_BIT_SYS_BUS_POS

#define MXC_F_SDHC_CFG_0_64_BIT_SYS_BUS_POS   28

CFG_0_64_BIT_SYS_BUS Position

◆ MXC_F_SDHC_CFG_0_8_BIT

#define MXC_F_SDHC_CFG_0_8_BIT   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_8_BIT_POS))

CFG_0_8_BIT Mask

◆ MXC_F_SDHC_CFG_0_8_BIT_POS

#define MXC_F_SDHC_CFG_0_8_BIT_POS   18

CFG_0_8_BIT Position

◆ MXC_F_SDHC_CFG_0_ADMA2

#define MXC_F_SDHC_CFG_0_ADMA2   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_ADMA2_POS))

CFG_0_ADMA2 Mask

◆ MXC_F_SDHC_CFG_0_ADMA2_POS

#define MXC_F_SDHC_CFG_0_ADMA2_POS   19

CFG_0_ADMA2 Position

◆ MXC_F_SDHC_CFG_0_ASYNC_INT

#define MXC_F_SDHC_CFG_0_ASYNC_INT   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_ASYNC_INT_POS))

CFG_0_ASYNC_INT Mask

◆ MXC_F_SDHC_CFG_0_ASYNC_INT_POS

#define MXC_F_SDHC_CFG_0_ASYNC_INT_POS   29

CFG_0_ASYNC_INT Position

◆ MXC_F_SDHC_CFG_0_CLK_FREQ

#define MXC_F_SDHC_CFG_0_CLK_FREQ   ((uint32_t)(0xFFUL << MXC_F_SDHC_CFG_0_CLK_FREQ_POS))

CFG_0_CLK_FREQ Mask

◆ MXC_F_SDHC_CFG_0_CLK_FREQ_POS

#define MXC_F_SDHC_CFG_0_CLK_FREQ_POS   8

CFG_0_CLK_FREQ Position

◆ MXC_F_SDHC_CFG_0_CLK_UNIT

#define MXC_F_SDHC_CFG_0_CLK_UNIT   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_CLK_UNIT_POS))

CFG_0_CLK_UNIT Mask

◆ MXC_F_SDHC_CFG_0_CLK_UNIT_POS

#define MXC_F_SDHC_CFG_0_CLK_UNIT_POS   7

CFG_0_CLK_UNIT Position

◆ MXC_F_SDHC_CFG_0_HS

#define MXC_F_SDHC_CFG_0_HS   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_HS_POS))

CFG_0_HS Mask

◆ MXC_F_SDHC_CFG_0_HS_POS

#define MXC_F_SDHC_CFG_0_HS_POS   21

CFG_0_HS Position

◆ MXC_F_SDHC_CFG_0_MAX_BLK_LEN

#define MXC_F_SDHC_CFG_0_MAX_BLK_LEN   ((uint32_t)(0x3UL << MXC_F_SDHC_CFG_0_MAX_BLK_LEN_POS))

CFG_0_MAX_BLK_LEN Mask

◆ MXC_F_SDHC_CFG_0_MAX_BLK_LEN_POS

#define MXC_F_SDHC_CFG_0_MAX_BLK_LEN_POS   16

CFG_0_MAX_BLK_LEN Position

◆ MXC_F_SDHC_CFG_0_SDMA

#define MXC_F_SDHC_CFG_0_SDMA   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_SDMA_POS))

CFG_0_SDMA Mask

◆ MXC_F_SDHC_CFG_0_SDMA_POS

#define MXC_F_SDHC_CFG_0_SDMA_POS   22

CFG_0_SDMA Position

◆ MXC_F_SDHC_CFG_0_SLOT_TYPE

#define MXC_F_SDHC_CFG_0_SLOT_TYPE   ((uint32_t)(0x3UL << MXC_F_SDHC_CFG_0_SLOT_TYPE_POS))

CFG_0_SLOT_TYPE Mask

◆ MXC_F_SDHC_CFG_0_SLOT_TYPE_POS

#define MXC_F_SDHC_CFG_0_SLOT_TYPE_POS   30

CFG_0_SLOT_TYPE Position

◆ MXC_F_SDHC_CFG_0_SUSPEND

#define MXC_F_SDHC_CFG_0_SUSPEND   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_SUSPEND_POS))

CFG_0_SUSPEND Mask

◆ MXC_F_SDHC_CFG_0_SUSPEND_POS

#define MXC_F_SDHC_CFG_0_SUSPEND_POS   23

CFG_0_SUSPEND Position

◆ MXC_F_SDHC_CFG_0_TO_FREQ

#define MXC_F_SDHC_CFG_0_TO_FREQ   ((uint32_t)(0x3FUL << MXC_F_SDHC_CFG_0_TO_FREQ_POS))

CFG_0_TO_FREQ Mask

◆ MXC_F_SDHC_CFG_0_TO_FREQ_POS

#define MXC_F_SDHC_CFG_0_TO_FREQ_POS   0

CFG_0_TO_FREQ Position

◆ MXC_S_SDHC_CFG_0_MAX_BLK_LEN_2048_BYTES

#define MXC_S_SDHC_CFG_0_MAX_BLK_LEN_2048_BYTES   (MXC_V_SDHC_CFG_0_MAX_BLK_LEN_2048_BYTES << MXC_F_SDHC_CFG_0_MAX_BLK_LEN_POS)

CFG_0_MAX_BLK_LEN_2048_BYTES Setting

◆ MXC_S_SDHC_CFG_0_TO_FREQ_1MHZ

#define MXC_S_SDHC_CFG_0_TO_FREQ_1MHZ   (MXC_V_SDHC_CFG_0_TO_FREQ_1MHZ << MXC_F_SDHC_CFG_0_TO_FREQ_POS)

CFG_0_TO_FREQ_1MHZ Setting

◆ MXC_V_SDHC_CFG_0_MAX_BLK_LEN_2048_BYTES

#define MXC_V_SDHC_CFG_0_MAX_BLK_LEN_2048_BYTES   ((uint32_t)0x2UL)

CFG_0_MAX_BLK_LEN_2048_BYTES Value

◆ MXC_V_SDHC_CFG_0_TO_FREQ_1MHZ

#define MXC_V_SDHC_CFG_0_TO_FREQ_1MHZ   ((uint32_t)0x1UL)

CFG_0_TO_FREQ_1MHZ Value