SDHC_CFG_1

Macros
#define	MXC_F_SDHC_CFG_1_SDR50_POS   0
#define	MXC_F_SDHC_CFG_1_SDR50   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_SDR50_POS))
#define	MXC_F_SDHC_CFG_1_SDR104_POS   1
#define	MXC_F_SDHC_CFG_1_SDR104   ((uint32_t)(0x0UL << MXC_F_SDHC_CFG_1_SDR104_POS))
#define	MXC_F_SDHC_CFG_1_DDR50_POS   2
#define	MXC_F_SDHC_CFG_1_DDR50   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_DDR50_POS))
#define	MXC_F_SDHC_CFG_1_DRIVER_A_POS   4
#define	MXC_F_SDHC_CFG_1_DRIVER_A   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_DRIVER_A_POS))
#define	MXC_F_SDHC_CFG_1_DRIVER_C_POS   5
#define	MXC_F_SDHC_CFG_1_DRIVER_C   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_DRIVER_C_POS))
#define	MXC_F_SDHC_CFG_1_DRIVER_D_POS   6
#define	MXC_F_SDHC_CFG_1_DRIVER_D   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_DRIVER_D_POS))
#define	MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS   8
#define	MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING   ((uint32_t)(0xFUL << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS))
#define	MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_DIS   ((uint32_t)0x0UL)
#define	MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_DIS   (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_DIS << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS)
#define	MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_1SEC   ((uint32_t)0x1UL)
#define	MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_1SEC   (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_1SEC << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS)
#define	MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_2SEC   ((uint32_t)0x2UL)
#define	MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_2SEC   (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_2SEC << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS)
#define	MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_4SEC   ((uint32_t)0x3UL)
#define	MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_4SEC   (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_4SEC << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS)
#define	MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_8SEC   ((uint32_t)0x4UL)
#define	MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_8SEC   (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_8SEC << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS)
#define	MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_16SEC   ((uint32_t)0x5UL)
#define	MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_16SEC   (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_16SEC << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS)
#define	MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_32SEC   ((uint32_t)0x6UL)
#define	MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_32SEC   (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_32SEC << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS)
#define	MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_64SEC   ((uint32_t)0x7UL)
#define	MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_64SEC   (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_64SEC << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS)
#define	MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_128SEC   ((uint32_t)0x8UL)
#define	MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_128SEC   (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_128SEC << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS)
#define	MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_256SEC   ((uint32_t)0x9UL)
#define	MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_256SEC   (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_256SEC << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS)
#define	MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_512SEC   ((uint32_t)0xAUL)
#define	MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_512SEC   (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_512SEC << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS)
#define	MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_1024SEC   ((uint32_t)0xBUL)
#define	MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_1024SEC   (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_1024SEC << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS)
#define	MXC_F_SDHC_CFG_1_TUNING_SDR50_POS   13
#define	MXC_F_SDHC_CFG_1_TUNING_SDR50   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_TUNING_SDR50_POS))
#define	MXC_F_SDHC_CFG_1_RETUNING_POS   14
#define	MXC_F_SDHC_CFG_1_RETUNING   ((uint32_t)(0x3UL << MXC_F_SDHC_CFG_1_RETUNING_POS))
#define	MXC_F_SDHC_CFG_1_CLK_MULTI_POS   16
#define	MXC_F_SDHC_CFG_1_CLK_MULTI   ((uint32_t)(0xFFUL << MXC_F_SDHC_CFG_1_CLK_MULTI_POS))

Detailed Description

Capabilities 32-63.

Macro Definition Documentation

MXC_F_SDHC_CFG_1_CLK_MULTI

#define MXC_F_SDHC_CFG_1_CLK_MULTI   ((uint32_t)(0xFFUL << MXC_F_SDHC_CFG_1_CLK_MULTI_POS))

CFG_1_CLK_MULTI Mask

MXC_F_SDHC_CFG_1_CLK_MULTI_POS

#define MXC_F_SDHC_CFG_1_CLK_MULTI_POS   16

CFG_1_CLK_MULTI Position

MXC_F_SDHC_CFG_1_DDR50

#define MXC_F_SDHC_CFG_1_DDR50   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_DDR50_POS))

CFG_1_DDR50 Mask

MXC_F_SDHC_CFG_1_DDR50_POS

#define MXC_F_SDHC_CFG_1_DDR50_POS   2

CFG_1_DDR50 Position

MXC_F_SDHC_CFG_1_DRIVER_A

#define MXC_F_SDHC_CFG_1_DRIVER_A   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_DRIVER_A_POS))

CFG_1_DRIVER_A Mask

MXC_F_SDHC_CFG_1_DRIVER_A_POS

#define MXC_F_SDHC_CFG_1_DRIVER_A_POS   4

CFG_1_DRIVER_A Position

MXC_F_SDHC_CFG_1_DRIVER_C

#define MXC_F_SDHC_CFG_1_DRIVER_C   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_DRIVER_C_POS))

CFG_1_DRIVER_C Mask

MXC_F_SDHC_CFG_1_DRIVER_C_POS

#define MXC_F_SDHC_CFG_1_DRIVER_C_POS   5

CFG_1_DRIVER_C Position

MXC_F_SDHC_CFG_1_DRIVER_D

#define MXC_F_SDHC_CFG_1_DRIVER_D   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_DRIVER_D_POS))

CFG_1_DRIVER_D Mask

MXC_F_SDHC_CFG_1_DRIVER_D_POS

#define MXC_F_SDHC_CFG_1_DRIVER_D_POS   6

CFG_1_DRIVER_D Position

MXC_F_SDHC_CFG_1_RETUNING

#define MXC_F_SDHC_CFG_1_RETUNING   ((uint32_t)(0x3UL << MXC_F_SDHC_CFG_1_RETUNING_POS))

CFG_1_RETUNING Mask

MXC_F_SDHC_CFG_1_RETUNING_POS

#define MXC_F_SDHC_CFG_1_RETUNING_POS   14

CFG_1_RETUNING Position

MXC_F_SDHC_CFG_1_SDR104

#define MXC_F_SDHC_CFG_1_SDR104   ((uint32_t)(0x0UL << MXC_F_SDHC_CFG_1_SDR104_POS))

CFG_1_SDR104 Mask

MXC_F_SDHC_CFG_1_SDR104_POS

#define MXC_F_SDHC_CFG_1_SDR104_POS   1

CFG_1_SDR104 Position

MXC_F_SDHC_CFG_1_SDR50

#define MXC_F_SDHC_CFG_1_SDR50   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_SDR50_POS))

CFG_1_SDR50 Mask

MXC_F_SDHC_CFG_1_SDR50_POS

#define MXC_F_SDHC_CFG_1_SDR50_POS   0

CFG_1_SDR50 Position

MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING

#define MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING   ((uint32_t)(0xFUL << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS))

CFG_1_TIMER_CNT_TUNING Mask

MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS

#define MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS   8

CFG_1_TIMER_CNT_TUNING Position

MXC_F_SDHC_CFG_1_TUNING_SDR50

#define MXC_F_SDHC_CFG_1_TUNING_SDR50   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_TUNING_SDR50_POS))

CFG_1_TUNING_SDR50 Mask

MXC_F_SDHC_CFG_1_TUNING_SDR50_POS

#define MXC_F_SDHC_CFG_1_TUNING_SDR50_POS   13

CFG_1_TUNING_SDR50 Position

MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_1024SEC

#define MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_1024SEC   (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_1024SEC << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS)

CFG_1_TIMER_CNT_TUNING_1024SEC Setting

MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_128SEC

#define MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_128SEC   (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_128SEC << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS)

CFG_1_TIMER_CNT_TUNING_128SEC Setting

MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_16SEC

#define MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_16SEC   (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_16SEC << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS)

CFG_1_TIMER_CNT_TUNING_16SEC Setting

MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_1SEC

#define MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_1SEC   (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_1SEC << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS)

CFG_1_TIMER_CNT_TUNING_1SEC Setting

MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_256SEC

#define MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_256SEC   (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_256SEC << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS)

CFG_1_TIMER_CNT_TUNING_256SEC Setting

MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_2SEC

#define MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_2SEC   (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_2SEC << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS)

CFG_1_TIMER_CNT_TUNING_2SEC Setting

MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_32SEC

#define MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_32SEC   (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_32SEC << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS)

CFG_1_TIMER_CNT_TUNING_32SEC Setting

MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_4SEC

#define MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_4SEC   (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_4SEC << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS)

CFG_1_TIMER_CNT_TUNING_4SEC Setting

MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_512SEC

#define MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_512SEC   (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_512SEC << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS)

CFG_1_TIMER_CNT_TUNING_512SEC Setting

MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_64SEC

#define MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_64SEC   (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_64SEC << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS)

CFG_1_TIMER_CNT_TUNING_64SEC Setting

MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_8SEC

#define MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_8SEC   (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_8SEC << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS)

CFG_1_TIMER_CNT_TUNING_8SEC Setting

MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_DIS

#define MXC_S_SDHC_CFG_1_TIMER_CNT_TUNING_DIS   (MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_DIS << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS)

CFG_1_TIMER_CNT_TUNING_DIS Setting

MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_1024SEC

#define MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_1024SEC   ((uint32_t)0xBUL)

CFG_1_TIMER_CNT_TUNING_1024SEC Value

MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_128SEC

#define MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_128SEC   ((uint32_t)0x8UL)

CFG_1_TIMER_CNT_TUNING_128SEC Value

MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_16SEC

#define MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_16SEC   ((uint32_t)0x5UL)

CFG_1_TIMER_CNT_TUNING_16SEC Value

MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_1SEC

#define MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_1SEC   ((uint32_t)0x1UL)

CFG_1_TIMER_CNT_TUNING_1SEC Value

MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_256SEC

#define MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_256SEC   ((uint32_t)0x9UL)

CFG_1_TIMER_CNT_TUNING_256SEC Value

MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_2SEC

#define MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_2SEC   ((uint32_t)0x2UL)

CFG_1_TIMER_CNT_TUNING_2SEC Value

MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_32SEC

#define MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_32SEC   ((uint32_t)0x6UL)

CFG_1_TIMER_CNT_TUNING_32SEC Value

MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_4SEC

#define MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_4SEC   ((uint32_t)0x3UL)

CFG_1_TIMER_CNT_TUNING_4SEC Value

MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_512SEC

#define MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_512SEC   ((uint32_t)0xAUL)

CFG_1_TIMER_CNT_TUNING_512SEC Value

MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_64SEC

#define MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_64SEC   ((uint32_t)0x7UL)

CFG_1_TIMER_CNT_TUNING_64SEC Value

MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_8SEC

#define MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_8SEC   ((uint32_t)0x4UL)

CFG_1_TIMER_CNT_TUNING_8SEC Value

MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_DIS

#define MXC_V_SDHC_CFG_1_TIMER_CNT_TUNING_DIS   ((uint32_t)0x0UL)

CFG_1_TIMER_CNT_TUNING_DIS Value