Register Offsets

Macros
#define	MXC_R_SPIXFC_CFG   ((uint32_t)0x00000000UL)
#define	MXC_R_SPIXFC_SS_POL   ((uint32_t)0x00000004UL)
#define	MXC_R_SPIXFC_GEN_CTRL   ((uint32_t)0x00000008UL)
#define	MXC_R_SPIXFC_FIFO_CTRL   ((uint32_t)0x0000000CUL)
#define	MXC_R_SPIXFC_SP_CTRL   ((uint32_t)0x00000010UL)
#define	MXC_R_SPIXFC_INT_FL   ((uint32_t)0x00000014UL)
#define	MXC_R_SPIXFC_INT_EN   ((uint32_t)0x00000018UL)

Detailed Description

SPIXFC Peripheral Register Offsets from the SPIXFC Base Peripheral Address.

Macro Definition Documentation

MXC_R_SPIXFC_CFG

#define MXC_R_SPIXFC_CFG   ((uint32_t)0x00000000UL)

Offset from SPIXFC Base Address: 0x0000

MXC_R_SPIXFC_FIFO_CTRL

#define MXC_R_SPIXFC_FIFO_CTRL   ((uint32_t)0x0000000CUL)

Offset from SPIXFC Base Address: 0x000C

MXC_R_SPIXFC_GEN_CTRL

#define MXC_R_SPIXFC_GEN_CTRL   ((uint32_t)0x00000008UL)

Offset from SPIXFC Base Address: 0x0008

MXC_R_SPIXFC_INT_EN

#define MXC_R_SPIXFC_INT_EN   ((uint32_t)0x00000018UL)

Offset from SPIXFC Base Address: 0x0018

MXC_R_SPIXFC_INT_FL

#define MXC_R_SPIXFC_INT_FL   ((uint32_t)0x00000014UL)

Offset from SPIXFC Base Address: 0x0014

MXC_R_SPIXFC_SP_CTRL

#define MXC_R_SPIXFC_SP_CTRL   ((uint32_t)0x00000010UL)

Offset from SPIXFC Base Address: 0x0010

MXC_R_SPIXFC_SS_POL

#define MXC_R_SPIXFC_SS_POL   ((uint32_t)0x00000004UL)

Offset from SPIXFC Base Address: 0x0004