Modules
	Register Offsets

	USBHS_FADDR

	USBHS_POWER

	USBHS_INTRIN

	USBHS_INTROUT

	USBHS_INTRINEN

	USBHS_INTROUTEN

	USBHS_INTRUSB

	USBHS_INTRUSBEN

	USBHS_FRAME

	USBHS_INDEX

	USBHS_TESTMODE

	USBHS_INMAXP

	USBHS_CSR0

	USBHS_INCSRL

	USBHS_INCSRU

	USBHS_OUTMAXP

	USBHS_OUTCSRL

	USBHS_OUTCSRU

	USBHS_COUNT0

	USBHS_OUTCOUNT

	USBHS_FIFO0

	USBHS_FIFO1

	USBHS_FIFO2

	USBHS_FIFO3

	USBHS_FIFO4

	USBHS_FIFO5

	USBHS_FIFO6

	USBHS_FIFO7

	USBHS_FIFO8

	USBHS_FIFO9

	USBHS_FIFO10

	USBHS_FIFO11

	USBHS_FIFO12

	USBHS_FIFO13

	USBHS_FIFO14

	USBHS_FIFO15

	USBHS_HWVERS

	USBHS_EPINFO

	USBHS_RAMINFO

	USBHS_SOFTRESET

	USBHS_CTUCH

	USBHS_CTHSRTN

	USBHS_MXM_INT

	USBHS_MXM_INT_EN

	USBHS_MXM_SUSPEND

	USBHS_MXM_REG_A4

Files
file	usbhs_regs.h

Data Structures
struct	mxc_usbhs_regs_t

Detailed Description

Registers, Bit Masks and Bit Positions for the USBHS Peripheral Module.

USB 2.0 High-speed Controller.

Data Structure Documentation

◆ mxc_usbhs_regs_t

struct mxc_usbhs_regs_t

Structure type to access the USBHS Registers.

Data Fields
__IO uint8_t	faddr

__IO uint8_t	power

__IO uint16_t	intrin

__IO uint16_t	introut

__IO uint16_t	intrinen

__IO uint16_t	introuten

__IO uint8_t	intrusb

__IO uint8_t	intrusben

__IO uint16_t	frame

__IO uint8_t	index

__IO uint8_t	testmode

__IO uint16_t	inmaxp

__IO uint8_t	incsru

__IO uint16_t	outmaxp

__IO uint8_t	outcsrl

__IO uint8_t	outcsru

__IO uint32_t	fifo0

__IO uint32_t	fifo1

__IO uint32_t	fifo2

__IO uint32_t	fifo3

__IO uint32_t	fifo4

__IO uint32_t	fifo5

__IO uint32_t	fifo6

__IO uint32_t	fifo7

__IO uint32_t	fifo8

__IO uint32_t	fifo9

__IO uint32_t	fifo10

__IO uint32_t	fifo11

__IO uint32_t	fifo12

__IO uint32_t	fifo13

__IO uint32_t	fifo14

__IO uint32_t	fifo15

__IO uint16_t	hwvers

__IO uint8_t	epinfo

__IO uint8_t	raminfo

__IO uint8_t	softreset

__IO uint16_t	ctuch

__IO uint16_t	cthsrtn

__IO uint32_t	mxm_usb_reg_00

__IO uint32_t	m31_phy_utmi_reset

__IO uint32_t	m31_phy_utmi_vcontrol

__IO uint32_t	m31_phy_clk_en

__IO uint32_t	m31_phy_ponrst

__IO uint32_t	m31_phy_noncry_rstb

__IO uint32_t	m31_phy_noncry_en

__IO uint32_t	m31_phy_u2_compliance_en

__IO uint32_t	m31_phy_u2_compliance_dac_adj

__IO uint32_t	m31_phy_u2_compliance_dac_adj_en

__IO uint32_t	m31_phy_clk_rdy

__IO uint32_t	m31_phy_pll_en

__IO uint32_t	m31_phy_bist_ok

__IO uint32_t	m31_phy_data_oe

__IO uint32_t	m31_phy_oscouten

__IO uint32_t	m31_phy_lpm_alive

__IO uint32_t	m31_phy_hs_bist_mode

__IO uint32_t	m31_phy_coreclkin

__IO uint32_t	m31_phy_xtlsel

__IO uint32_t	m31_phy_ls_en

__IO uint32_t	m31_phy_debug_sel

__IO uint32_t	m31_phy_debug_out

__IO uint32_t	m31_phy_outclksel

__IO uint32_t	m31_phy_xcfgi_31_0

__IO uint32_t	m31_phy_xcfgi_63_32

__IO uint32_t	m31_phy_xcfgi_95_64

__IO uint32_t	m31_phy_xcfgi_127_96

__IO uint32_t	m31_phy_xcfgi_137_128

__IO uint32_t	m31_phy_xcfg_hs_coarse_tune_num

__IO uint32_t	m31_phy_xcfg_hs_fine_tune_num

__IO uint32_t	m31_phy_xcfg_fs_coarse_tune_num

__IO uint32_t	m31_phy_xcfg_fs_fine_tune_num

__IO uint32_t	m31_phy_xcfg_lock_range_max

__IO uint32_t	m31_phy_xcfgi_lock_range_min

__IO uint32_t	m31_phy_xcfg_ob_rsel

__IO uint32_t	m31_phy_xcfg_oc_rsel

__IO uint32_t	m31_phy_xcfgo

__IO uint32_t	mxm_int

__IO uint32_t	mxm_int_en

__IO uint32_t	mxm_suspend

__IO uint32_t	mxm_reg_a4

__IO uint8_t	csr0

__IO uint8_t	incsrl

__IO uint16_t	count0

__IO uint16_t	outcount

Field Documentation

◆ count0

__IO uint16_t count0

0x18: USBHS COUNT0 Register

◆ csr0

__IO uint8_t csr0

0x12: USBHS CSR0 Register

◆ cthsrtn

__IO uint16_t cthsrtn

0x82: USBHS CTHSRTN Register

◆ ctuch

__IO uint16_t ctuch

0x80: USBHS CTUCH Register

◆ epinfo

__IO uint8_t epinfo

0x78: USBHS EPINFO Register

◆ faddr

__IO uint8_t faddr

0x00: USBHS FADDR Register

◆ fifo0

__IO uint32_t fifo0

0x20: USBHS FIFO0 Register

◆ fifo1

__IO uint32_t fifo1

0x24: USBHS FIFO1 Register

◆ fifo10

__IO uint32_t fifo10

0x48: USBHS FIFO10 Register

◆ fifo11

__IO uint32_t fifo11

0x4c: USBHS FIFO11 Register

◆ fifo12

__IO uint32_t fifo12

0x50: USBHS FIFO12 Register

◆ fifo13

__IO uint32_t fifo13

0x54: USBHS FIFO13 Register

◆ fifo14

__IO uint32_t fifo14

0x58: USBHS FIFO14 Register

◆ fifo15

__IO uint32_t fifo15

0x5c: USBHS FIFO15 Register

◆ fifo2

__IO uint32_t fifo2

0x28: USBHS FIFO2 Register

◆ fifo3

__IO uint32_t fifo3

0x2c: USBHS FIFO3 Register

◆ fifo4

__IO uint32_t fifo4

0x30: USBHS FIFO4 Register

◆ fifo5

__IO uint32_t fifo5

0x34: USBHS FIFO5 Register

◆ fifo6

__IO uint32_t fifo6

0x38: USBHS FIFO6 Register

◆ fifo7

__IO uint32_t fifo7

0x3c: USBHS FIFO7 Register

◆ fifo8

__IO uint32_t fifo8

0x40: USBHS FIFO8 Register

◆ fifo9

__IO uint32_t fifo9

0x44: USBHS FIFO9 Register

◆ frame

__IO uint16_t frame

0x0C: USBHS FRAME Register

◆ hwvers

__IO uint16_t hwvers

0x6c: USBHS HWVERS Register

◆ incsrl

__IO uint8_t incsrl

0x12: USBHS INCSRL Register

◆ incsru

__IO uint8_t incsru

0x13: USBHS INCSRU Register

◆ index

__IO uint8_t index

0x0E: USBHS INDEX Register

◆ inmaxp

__IO uint16_t inmaxp

0x10: USBHS INMAXP Register

◆ intrin

__IO uint16_t intrin

0x02: USBHS INTRIN Register

◆ intrinen

__IO uint16_t intrinen

0x06: USBHS INTRINEN Register

◆ introut

__IO uint16_t introut

0x04: USBHS INTROUT Register

◆ introuten

__IO uint16_t introuten

0x08: USBHS INTROUTEN Register

◆ intrusb

__IO uint8_t intrusb

0x0A: USBHS INTRUSB Register

◆ intrusben

__IO uint8_t intrusben

0x0B: USBHS INTRUSBEN Register

◆ m31_phy_bist_ok

__IO uint32_t m31_phy_bist_ok

0x434: USBHS M31_PHY_BIST_OK Register

◆ m31_phy_clk_en

__IO uint32_t m31_phy_clk_en

0x40C: USBHS M31_PHY_CLK_EN Register

◆ m31_phy_clk_rdy

__IO uint32_t m31_phy_clk_rdy

0x42C: USBHS M31_PHY_CLK_RDY Register

◆ m31_phy_coreclkin

__IO uint32_t m31_phy_coreclkin

0x448: USBHS M31_PHY_CORECLKIN Register

◆ m31_phy_data_oe

__IO uint32_t m31_phy_data_oe

0x438: USBHS M31_PHY_DATA_OE Register

◆ m31_phy_debug_out

__IO uint32_t m31_phy_debug_out

0x458: USBHS M31_PHY_DEBUG_OUT Register

◆ m31_phy_debug_sel

__IO uint32_t m31_phy_debug_sel

0x454: USBHS M31_PHY_DEBUG_SEL Register

◆ m31_phy_hs_bist_mode

__IO uint32_t m31_phy_hs_bist_mode

0x444: USBHS M31_PHY_HS_BIST_MODE Register

◆ m31_phy_lpm_alive

__IO uint32_t m31_phy_lpm_alive

0x440: USBHS M31_PHY_LPM_ALIVE Register

◆ m31_phy_ls_en

__IO uint32_t m31_phy_ls_en

0x450: USBHS M31_PHY_LS_EN Register

◆ m31_phy_noncry_en

__IO uint32_t m31_phy_noncry_en

0x418: USBHS M31_PHY_NONCRY_EN Register

◆ m31_phy_noncry_rstb

__IO uint32_t m31_phy_noncry_rstb

0x414: USBHS M31_PHY_NONCRY_RSTB Register

◆ m31_phy_oscouten

__IO uint32_t m31_phy_oscouten

0x43C: USBHS M31_PHY_OSCOUTEN Register

◆ m31_phy_outclksel

__IO uint32_t m31_phy_outclksel

0x45C: USBHS M31_PHY_OUTCLKSEL Register

◆ m31_phy_pll_en

__IO uint32_t m31_phy_pll_en

0x430: USBHS M31_PHY_PLL_EN Register

◆ m31_phy_ponrst

__IO uint32_t m31_phy_ponrst

0x410: USBHS M31_PHY_PONRST Register

◆ m31_phy_u2_compliance_dac_adj

__IO uint32_t m31_phy_u2_compliance_dac_adj

0x424: USBHS M31_PHY_U2_COMPLIANCE_DAC_ADJ Register

◆ m31_phy_u2_compliance_dac_adj_en

__IO uint32_t m31_phy_u2_compliance_dac_adj_en

0x428: USBHS M31_PHY_U2_COMPLIANCE_DAC_ADJ_EN Register

◆ m31_phy_u2_compliance_en

__IO uint32_t m31_phy_u2_compliance_en

0x420: USBHS M31_PHY_U2_COMPLIANCE_EN Register

◆ m31_phy_utmi_reset

__IO uint32_t m31_phy_utmi_reset

0x404: USBHS M31_PHY_UTMI_RESET Register

◆ m31_phy_utmi_vcontrol

__IO uint32_t m31_phy_utmi_vcontrol

0x408: USBHS M31_PHY_UTMI_VCONTROL Register

◆ m31_phy_xcfg_fs_coarse_tune_num

__IO uint32_t m31_phy_xcfg_fs_coarse_tune_num

0x47C: USBHS M31_PHY_XCFG_FS_COARSE_TUNE_NUM Register

◆ m31_phy_xcfg_fs_fine_tune_num

__IO uint32_t m31_phy_xcfg_fs_fine_tune_num

0x480: USBHS M31_PHY_XCFG_FS_FINE_TUNE_NUM Register

◆ m31_phy_xcfg_hs_coarse_tune_num

__IO uint32_t m31_phy_xcfg_hs_coarse_tune_num

0x474: USBHS M31_PHY_XCFG_HS_COARSE_TUNE_NUM Register

◆ m31_phy_xcfg_hs_fine_tune_num

__IO uint32_t m31_phy_xcfg_hs_fine_tune_num

0x478: USBHS M31_PHY_XCFG_HS_FINE_TUNE_NUM Register

◆ m31_phy_xcfg_lock_range_max

__IO uint32_t m31_phy_xcfg_lock_range_max

0x484: USBHS M31_PHY_XCFG_LOCK_RANGE_MAX Register

◆ m31_phy_xcfg_ob_rsel

__IO uint32_t m31_phy_xcfg_ob_rsel

0x48C: USBHS M31_PHY_XCFG_OB_RSEL Register

◆ m31_phy_xcfg_oc_rsel

__IO uint32_t m31_phy_xcfg_oc_rsel

0x490: USBHS M31_PHY_XCFG_OC_RSEL Register

◆ m31_phy_xcfgi_127_96

__IO uint32_t m31_phy_xcfgi_127_96

0x46C: USBHS M31_PHY_XCFGI_127_96 Register

◆ m31_phy_xcfgi_137_128

__IO uint32_t m31_phy_xcfgi_137_128

0x470: USBHS M31_PHY_XCFGI_137_128 Register

◆ m31_phy_xcfgi_31_0

__IO uint32_t m31_phy_xcfgi_31_0

0x460: USBHS M31_PHY_XCFGI_31_0 Register

◆ m31_phy_xcfgi_63_32

__IO uint32_t m31_phy_xcfgi_63_32

0x464: USBHS M31_PHY_XCFGI_63_32 Register

◆ m31_phy_xcfgi_95_64

__IO uint32_t m31_phy_xcfgi_95_64

0x468: USBHS M31_PHY_XCFGI_95_64 Register

◆ m31_phy_xcfgi_lock_range_min

__IO uint32_t m31_phy_xcfgi_lock_range_min

0x488: USBHS M31_PHY_XCFGI_LOCK_RANGE_MIN Register

◆ m31_phy_xcfgo

__IO uint32_t m31_phy_xcfgo

0x494: USBHS M31_PHY_XCFGO Register

◆ m31_phy_xtlsel

__IO uint32_t m31_phy_xtlsel

0x44C: USBHS M31_PHY_XTLSEL Register

◆ mxm_int

__IO uint32_t mxm_int

0x498: USBHS MXM_INT Register

◆ mxm_int_en

__IO uint32_t mxm_int_en

0x49C: USBHS MXM_INT_EN Register

◆ mxm_reg_a4

__IO uint32_t mxm_reg_a4

0x4A4: USBHS MXM_REG_A4 Register

◆ mxm_suspend

__IO uint32_t mxm_suspend

0x4A0: USBHS MXM_SUSPEND Register

◆ mxm_usb_reg_00

__IO uint32_t mxm_usb_reg_00

0x400: USBHS MXM_USB_REG_00 Register

◆ outcount

__IO uint16_t outcount

0x18: USBHS OUTCOUNT Register

◆ outcsrl

__IO uint8_t outcsrl

0x16: USBHS OUTCSRL Register

◆ outcsru

__IO uint8_t outcsru

0x17: USBHS OUTCSRU Register

◆ outmaxp

__IO uint16_t outmaxp

0x14: USBHS OUTMAXP Register

◆ power

__IO uint8_t power

0x01: USBHS POWER Register

◆ raminfo

__IO uint8_t raminfo

0x79: USBHS RAMINFO Register

◆ softreset

__IO uint8_t softreset

0x7A: USBHS SOFTRESET Register

◆ testmode

__IO uint8_t testmode

0x0F: USBHS TESTMODE Register

Modules

Files

Data Structures