nbbfc_regs.h

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/******************************************************************************
 *
 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 
 * Analog Devices, Inc.),
 * Copyright (C) 2023-2024 Analog Devices, Inc.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 ******************************************************************************/
 
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_NBBFC_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_NBBFC_REGS_H_
 
/* **** Includes **** */
#include <stdint.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
#if defined (__ICCARM__)
  #pragma system_include
#endif
 
#if defined (__CC_ARM)
  #pragma anon_unions
#endif
/*
    If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I  volatile const
#endif
#ifndef __O
#define __O  volatile
#endif
#ifndef __R
#define __R  volatile const
#endif
 
/* **** Definitions **** */
 
typedef struct {
    __IO uint32_t reg0;                 
    __IO uint32_t reg1;                 
    __IO uint32_t reg2;                 
    __IO uint32_t reg3;                 
} mxc_nbbfc_regs_t;
 
/* Register offsets for module NBBFC */
#define MXC_R_NBBFC_REG0                   ((uint32_t)0x00000000UL) 
#define MXC_R_NBBFC_REG1                   ((uint32_t)0x00000004UL) 
#define MXC_R_NBBFC_REG2                   ((uint32_t)0x00000008UL) 
#define MXC_R_NBBFC_REG3                   ((uint32_t)0x0000000CUL) 
#define MXC_F_NBBFC_REG0_RDSGCSEL_POS                  0 
#define MXC_F_NBBFC_REG0_RDSGCSEL                      ((uint32_t)(0x3FUL << MXC_F_NBBFC_REG0_RDSGCSEL_POS)) 
#define MXC_F_NBBFC_REG0_RDSGCSET_POS                  6 
#define MXC_F_NBBFC_REG0_RDSGCSET                      ((uint32_t)(0x1UL << MXC_F_NBBFC_REG0_RDSGCSET_POS)) 
#define MXC_V_NBBFC_REG0_RDSGCSET_INTERNAL             ((uint32_t)0x0UL) 
#define MXC_S_NBBFC_REG0_RDSGCSET_INTERNAL             (MXC_V_NBBFC_REG0_RDSGCSET_INTERNAL << MXC_F_NBBFC_REG0_RDSGCSET_POS) 
#define MXC_V_NBBFC_REG0_RDSGCSET_GRAY_CODE            ((uint32_t)0x1UL) 
#define MXC_S_NBBFC_REG0_RDSGCSET_GRAY_CODE            (MXC_V_NBBFC_REG0_RDSGCSET_GRAY_CODE << MXC_F_NBBFC_REG0_RDSGCSET_POS) 
#define MXC_F_NBBFC_REG0_HYPCGDLY_POS                  8 
#define MXC_F_NBBFC_REG0_HYPCGDLY                      ((uint32_t)(0x3FUL << MXC_F_NBBFC_REG0_HYPCGDLY_POS)) 
#define MXC_F_NBBFC_REG0_USBRCKSEL_POS                 16 
#define MXC_F_NBBFC_REG0_USBRCKSEL                     ((uint32_t)(0x1UL << MXC_F_NBBFC_REG0_USBRCKSEL_POS)) 
#define MXC_V_NBBFC_REG0_USBRCKSEL_SYS                 ((uint32_t)0x0UL) 
#define MXC_S_NBBFC_REG0_USBRCKSEL_SYS                 (MXC_V_NBBFC_REG0_USBRCKSEL_SYS << MXC_F_NBBFC_REG0_USBRCKSEL_POS) 
#define MXC_V_NBBFC_REG0_USBRCKSEL_DIG                 ((uint32_t)0x1UL) 
#define MXC_S_NBBFC_REG0_USBRCKSEL_DIG                 (MXC_V_NBBFC_REG0_USBRCKSEL_DIG << MXC_F_NBBFC_REG0_USBRCKSEL_POS) 
#define MXC_F_NBBFC_REG0_QSPI0SEL_POS                  17 
#define MXC_F_NBBFC_REG0_QSPI0SEL                      ((uint32_t)(0x1UL << MXC_F_NBBFC_REG0_QSPI0SEL_POS)) 
#define MXC_V_NBBFC_REG0_QSPI0SEL_MED                  ((uint32_t)0x0UL) 
#define MXC_S_NBBFC_REG0_QSPI0SEL_MED                  (MXC_V_NBBFC_REG0_QSPI0SEL_MED << MXC_F_NBBFC_REG0_QSPI0SEL_POS) 
#define MXC_V_NBBFC_REG0_QSPI0SEL_QSPI0                ((uint32_t)0x1UL) 
#define MXC_S_NBBFC_REG0_QSPI0SEL_QSPI0                (MXC_V_NBBFC_REG0_QSPI0SEL_QSPI0 << MXC_F_NBBFC_REG0_QSPI0SEL_POS) 
#define MXC_F_NBBFC_REG0_I2C0DGEN0_POS                 20 
#define MXC_F_NBBFC_REG0_I2C0DGEN0                     ((uint32_t)(0x1UL << MXC_F_NBBFC_REG0_I2C0DGEN0_POS)) 
#define MXC_V_NBBFC_REG0_I2C0DGEN0_DIS                 ((uint32_t)0x0UL) 
#define MXC_S_NBBFC_REG0_I2C0DGEN0_DIS                 (MXC_V_NBBFC_REG0_I2C0DGEN0_DIS << MXC_F_NBBFC_REG0_I2C0DGEN0_POS) 
#define MXC_V_NBBFC_REG0_I2C0DGEN0_EN                  ((uint32_t)0x1UL) 
#define MXC_S_NBBFC_REG0_I2C0DGEN0_EN                  (MXC_V_NBBFC_REG0_I2C0DGEN0_EN << MXC_F_NBBFC_REG0_I2C0DGEN0_POS) 
#define MXC_F_NBBFC_REG0_I2C0DGEN1_POS                 21 
#define MXC_F_NBBFC_REG0_I2C0DGEN1                     ((uint32_t)(0x1UL << MXC_F_NBBFC_REG0_I2C0DGEN1_POS)) 
#define MXC_V_NBBFC_REG0_I2C0DGEN1_DIS                 ((uint32_t)0x0UL) 
#define MXC_S_NBBFC_REG0_I2C0DGEN1_DIS                 (MXC_V_NBBFC_REG0_I2C0DGEN1_DIS << MXC_F_NBBFC_REG0_I2C0DGEN1_POS) 
#define MXC_V_NBBFC_REG0_I2C0DGEN1_EN                  ((uint32_t)0x1UL) 
#define MXC_S_NBBFC_REG0_I2C0DGEN1_EN                  (MXC_V_NBBFC_REG0_I2C0DGEN1_EN << MXC_F_NBBFC_REG0_I2C0DGEN1_POS) 
#define MXC_F_NBBFC_REG0_I2C1DGEN0_POS                 22 
#define MXC_F_NBBFC_REG0_I2C1DGEN0                     ((uint32_t)(0x1UL << MXC_F_NBBFC_REG0_I2C1DGEN0_POS)) 
#define MXC_V_NBBFC_REG0_I2C1DGEN0_DIS                 ((uint32_t)0x0UL) 
#define MXC_S_NBBFC_REG0_I2C1DGEN0_DIS                 (MXC_V_NBBFC_REG0_I2C1DGEN0_DIS << MXC_F_NBBFC_REG0_I2C1DGEN0_POS) 
#define MXC_V_NBBFC_REG0_I2C1DGEN0_EN                  ((uint32_t)0x1UL) 
#define MXC_S_NBBFC_REG0_I2C1DGEN0_EN                  (MXC_V_NBBFC_REG0_I2C1DGEN0_EN << MXC_F_NBBFC_REG0_I2C1DGEN0_POS) 
#define MXC_F_NBBFC_REG0_I2C1DGEN1_POS                 23 
#define MXC_F_NBBFC_REG0_I2C1DGEN1                     ((uint32_t)(0x1UL << MXC_F_NBBFC_REG0_I2C1DGEN1_POS)) 
#define MXC_V_NBBFC_REG0_I2C1DGEN1_DIS                 ((uint32_t)0x0UL) 
#define MXC_S_NBBFC_REG0_I2C1DGEN1_DIS                 (MXC_V_NBBFC_REG0_I2C1DGEN1_DIS << MXC_F_NBBFC_REG0_I2C1DGEN1_POS) 
#define MXC_V_NBBFC_REG0_I2C1DGEN1_EN                  ((uint32_t)0x1UL) 
#define MXC_S_NBBFC_REG0_I2C1DGEN1_EN                  (MXC_V_NBBFC_REG0_I2C1DGEN1_EN << MXC_F_NBBFC_REG0_I2C1DGEN1_POS) 
#define MXC_F_NBBFC_REG1_ACEN_POS                      0 
#define MXC_F_NBBFC_REG1_ACEN                          ((uint32_t)(0x1UL << MXC_F_NBBFC_REG1_ACEN_POS)) 
#define MXC_V_NBBFC_REG1_ACEN_DIS                      ((uint32_t)0x0UL) 
#define MXC_S_NBBFC_REG1_ACEN_DIS                      (MXC_V_NBBFC_REG1_ACEN_DIS << MXC_F_NBBFC_REG1_ACEN_POS) 
#define MXC_V_NBBFC_REG1_ACEN_EN                       ((uint32_t)0x1UL) 
#define MXC_S_NBBFC_REG1_ACEN_EN                       (MXC_V_NBBFC_REG1_ACEN_EN << MXC_F_NBBFC_REG1_ACEN_POS) 
#define MXC_F_NBBFC_REG1_ACRUN_POS                     1 
#define MXC_F_NBBFC_REG1_ACRUN                         ((uint32_t)(0x1UL << MXC_F_NBBFC_REG1_ACRUN_POS)) 
#define MXC_V_NBBFC_REG1_ACRUN_NOT                     ((uint32_t)0x0UL) 
#define MXC_S_NBBFC_REG1_ACRUN_NOT                     (MXC_V_NBBFC_REG1_ACRUN_NOT << MXC_F_NBBFC_REG1_ACRUN_POS) 
#define MXC_V_NBBFC_REG1_ACRUN_RUN                     ((uint32_t)0x1UL) 
#define MXC_S_NBBFC_REG1_ACRUN_RUN                     (MXC_V_NBBFC_REG1_ACRUN_RUN << MXC_F_NBBFC_REG1_ACRUN_POS) 
#define MXC_F_NBBFC_REG1_LDTRM_POS                     2 
#define MXC_F_NBBFC_REG1_LDTRM                         ((uint32_t)(0x1UL << MXC_F_NBBFC_REG1_LDTRM_POS)) 
#define MXC_F_NBBFC_REG1_GAININV_POS                   3 
#define MXC_F_NBBFC_REG1_GAININV                       ((uint32_t)(0x1UL << MXC_F_NBBFC_REG1_GAININV_POS)) 
#define MXC_V_NBBFC_REG1_GAININV_NOT                   ((uint32_t)0x0UL) 
#define MXC_S_NBBFC_REG1_GAININV_NOT                   (MXC_V_NBBFC_REG1_GAININV_NOT << MXC_F_NBBFC_REG1_GAININV_POS) 
#define MXC_V_NBBFC_REG1_GAININV_RUN                   ((uint32_t)0x1UL) 
#define MXC_S_NBBFC_REG1_GAININV_RUN                   (MXC_V_NBBFC_REG1_GAININV_RUN << MXC_F_NBBFC_REG1_GAININV_POS) 
#define MXC_F_NBBFC_REG1_ATOMIC_POS                    4 
#define MXC_F_NBBFC_REG1_ATOMIC                        ((uint32_t)(0x1UL << MXC_F_NBBFC_REG1_ATOMIC_POS)) 
#define MXC_V_NBBFC_REG1_ATOMIC_NOT                    ((uint32_t)0x0UL) 
#define MXC_S_NBBFC_REG1_ATOMIC_NOT                    (MXC_V_NBBFC_REG1_ATOMIC_NOT << MXC_F_NBBFC_REG1_ATOMIC_POS) 
#define MXC_V_NBBFC_REG1_ATOMIC_RUN                    ((uint32_t)0x1UL) 
#define MXC_S_NBBFC_REG1_ATOMIC_RUN                    (MXC_V_NBBFC_REG1_ATOMIC_RUN << MXC_F_NBBFC_REG1_ATOMIC_POS) 
#define MXC_F_NBBFC_REG1_MU_POS                        8 
#define MXC_F_NBBFC_REG1_MU                            ((uint32_t)(0xFFFUL << MXC_F_NBBFC_REG1_MU_POS)) 
#define MXC_F_NBBFC_REG2_INTTRIM_POS                   0 
#define MXC_F_NBBFC_REG2_INTTRIM                       ((uint32_t)(0x1FFUL << MXC_F_NBBFC_REG2_INTTRIM_POS)) 
#define MXC_F_NBBFC_REG2_MINTRM_POS                    10 
#define MXC_F_NBBFC_REG2_MINTRM                        ((uint32_t)(0x1FFUL << MXC_F_NBBFC_REG2_MINTRM_POS)) 
#define MXC_F_NBBFC_REG2_MAXTRM_POS                    20 
#define MXC_F_NBBFC_REG2_MAXTRM                        ((uint32_t)(0x1FFUL << MXC_F_NBBFC_REG2_MAXTRM_POS)) 
#define MXC_F_NBBFC_REG3_DONECNT_POS                   0 
#define MXC_F_NBBFC_REG3_DONECNT                       ((uint32_t)(0xFFUL << MXC_F_NBBFC_REG3_DONECNT_POS)) 
#ifdef __cplusplus
}
#endif
 
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_NBBFC_REGS_H_